Ex Parte Gaither et al

Patent Trial and Appeal BoardAug 18, 2014

11554672 (P.T.A.B. Aug. 18, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte BLAINE D. GAITHER and JUDSON E. VEAZEY ____________ Appeal 2014-004524 Application 11/554,672 Technology Center 2100 ____________ Before JOSEPH F. RUGGIERO, JEFFREY S. SMITH, and JOHNNY A. KUMAR, Administrative Patent Judges. SMITH, Administrative Patent Judge. DECISION ON APPEAL Appeal 2014-004524 Application 11/554,672 2 STATEMENT OF THE CASE This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s Final Rejection of claims 1–3, 6–13, and 16–20. The Examiner has objected to claims 4, 5, 14, and 15. Claim 21 has been allowed. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. Representative Claim Claim 1. A method for providing transactional memory, comprising: enforcing a cache coherency protocol upon a cache memory including first cache lines, wherein each first cache line is in one of a modified state, an owned state, an exclusive state, a shared state, and an invalid state; upon initiation of a first transaction accessing at least one of the first cache lines, ensuring each first cache line is in one of the shared state and the invalid state, the ensuring including writing back to main memory each cache line in the modified state and each cache line in the owned state; and during the first transaction, in response to a first external request for any first cache line in the modified state, the owned state, or the exclusive state: invalidating each first cache line in the modified state and each cache line in the owned state without writing the first cache line to a main memory; demoting each first cache line in the exclusive state to one of the shared state and the invalid state; aborting the first transaction; and reattempting the first transaction after the aborting. Appeal 2014-004524 Application 11/554,672 3 Prior Art Edirisooriya US 2004/0128450 A1 July 1, 2004 Jamil US 6,775,748 B2 Aug. 10, 2004 Kruckemyer US 6,993,632 B2 Jan. 31, 2006 Kumar US 2006/0085591 A1 Apr. 20, 2006 Examiner’s Rejections Claims 1–3 and 11–13 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Jamil, Edirisooriya, and Kumar. Claims 6–10 and 16–20 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Jamil, Edirisooriya, Kumar, and Kruckemyer. ANALYSIS Appellants contend the purpose of Jamil is to transfer an owned cache line, rather than writing the owned cache line to main memory, to avoid bus traffic, latency, and power consumption associated with communicating with main memory. App. Br. 7. Appellants further contend modifying Jamil to write back to main memory as taught by Edirisooriya and Kumar would render Jamil unsatisfactory for its intended purpose. App. Br. 7–10; Reply Br. 10–11. Jamil teaches In an effort to further reduce bus traffic to the main memory, many of these cache coherency protocols allow a first cache that is holding locally modified data (i.e., "dirty" data) to directly supply a second cache that is requesting the same block, without updating main memory. Typically, the first cache then puts its memory block in an "owned" state to Appeal 2014-004524 Application 11/554,672 4 indicate that the block is "dirty" and shared. However, when the "owned" block is replaced, the first cache must write the block back to main memory so that the modifications are not lost. This write-back generates bus traffic to the main memory. Bus traffic increase memory latency and power consumption. Subsequent modifications to the memory block in the second cache will also need to be written-back to main memory, thereby generating additional bus traffic. Col. 1, ll. 25–40. Jamil further teaches “the methods and apparatus described herein transfer ownership of a memory block from a first cache to a second cache without performing a writeback to a main memory.” Col. 1, ll. 60–64. The Examiner has not provided persuasive evidence or explanation to show that modifying Jamil to perform a writeback to main memory would still allow Jamil to achieve the intended purpose of avoiding bus traffic, latency, and power consumption associated with writing back to main memory. We do not sustain the rejection of claim 1 under 35 U.S.C. § 103. Independent claim 11 contains a limitation similar to that recited in claim 1 for which the rejection fails. We do not sustain the rejections of claims 1–3, 6–13, and 16–20 under 35 U.S.C. § 103. DECISION The rejection of claims 1–3 and 11–13 under 35 U.S.C. § 103(a) as being unpatentable over Jamil, Edirisooriya, and Kumar is reversed. The rejection of claims 6–10 and 16–20 under 35 U.S.C. § 103(a) as being unpatentable over Jamil, Edirisooriya, Kumar, and Kruckemyer is reversed. Appeal 2014-004524 Application 11/554,672 5 REVERSED kis