Ex Parte FANG et al

Patent Trial and Appeal BoardAug 29, 2017

14340054 (P.T.A.B. Aug. 29, 2017)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/340,054 07/24/2014 Shenqing FANG SPN12029D1 1059 105945 7590 08/30/2017 Sterne, Kessler, Goldstein & Fox P.L.L.C. 1100 New York Avenue, NW Washington, DC 20005 EXAMINER REIDA, MOLLY KAY ART UNIT PAPER NUMBER 2816 MAIL DATE DELIVERY MODE 08/30/2017 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte SHENQING FANG and CHUN CHEN ____________________ Appeal 2016-006192 Application 14/340,054 Technology Center 2800 ____________________ Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and MONTÉ T. SQUIRE Administrative Patent Judges. TIMM, Administrative Patent Judge. DECISION ON APPEAL1 1 In explaining our Decision, we cite to the Specification dated July 24, 2014 (Spec.), Final Office Action dated June 9, 2015 (Final), the Appeal Brief dated November 17, 2015 (Appeal Br.), the Examiner’s Answer dated April 1, 2016 (Ans.), and the Reply Brief dated June 1, 2016 (Reply Br.). Appeal 2016-006192 Application 14/340,054 2 STATEMENT OF CASE Pursuant to 35 U.S.C. § 134(a), Appellants2 appeal from the Examiner’s decision to reject claim 1 under 35 U.S.C. § 102(b) as anticipated by Tanaka.3 We have jurisdiction under 35 U.S.C. § 6(b). For the reasons given by the Examiner, we AFFIRM. We add the following for emphasis. Claim 1 is the only claim pending and reads as follows: 1. A semiconductor device having a memory region, a first substrate region, and a second substrate region, the semiconductor device comprising: first gates in the first substrate region; second gates in the second substrate region; third gates in the memory region; and fourth gates in the memory region, wherein each fourth gate is formed adjacent to a corresponding third gate, and wherein a sidewall of each of the fourth gates is formed before one or more sidewalls of the second gates. Claims Appendix, Appeal Br. 9 (emphasis added). OPINION The Examiner finds that Tanaka describes a semiconductor device having all of the structures required by claim 1. Final 3–4. The Examiner illustrates the location of the structures by reproducing a marked up version of Tanaka’s Figure 57, which we reproduce below: 2 Appellants identify the real party in interest as Cypress Semiconductor Corporation. 3 Tanaka et al., US 2005/0258474 A1, published Nov. 25, 2005. Appeal 2016-006192 Application 14/340,054 3 Annotated Figure 57 is a cross-sectional view of a portion of Tanaka’s semiconductor integrated circuit The dispute is over the requirements of the last wherein clause of claim 1, and the issue arising is whether Tanaka describes a semiconductor device having gate sidewalls of the structure required by that last wherein clause, which reads “wherein a sidewall of each of the fourth gates is formed before one or more sidewalls of the second gates.” Claim 1 (emphasis added). First, Appellants contend that the Examiner failed to give full patentable weight to the last wherein clause, particularly, the “formed before” requirement. Appeal Br. 5; Reply Br. 3. Second, Appellants contend that Tanaka does not disclose the claim feature of the wherein clause. Appeal Br. 6–7; Reply Br. 3–4. We agree with the Examiner that the temporal aspect of the last wherein clause requiring each sidewall of each fourth gate be “formed Appeal 2016-006192 Application 14/340,054 4 before” one or more sidewalls of the second gates fails to structurally distinguish the semiconductor of claim 1 from the semiconductor described by Tanaka. Ans. 2–3. The relative timing of the formation of the sidewalls does not limit the location of the sidewalls. But more importantly, as pointed out by the Examiner, Tanaka, in fact, forms the sidewalls of the fourth gates before the sidewalls of the second gates. Ans. 3. This can be seen by a comparison of Figure 52, which shows the formation of the fourth gates MG1 and MG2 with their attendant sidewalls, with Figure 55, which shows that the step of forming the second gates LVGn and LVGp occurs later in the process. Tanaka ¶¶ 177, 180, 183. Given that Tanaka teaches the timing of the formation of the sidewalls required by claim 1, Tanaka’s structure must necessarily have the structure required by the claim. CONCLUSION We sustain the Examiner’s rejection. DECISION The Examiner’s decision is affirmed. TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1). AFFIRMED