Ex Parte Essey et al

Patent Trial and Appeal Board

May 25, 2017

12816165 (P.T.A.B. May. 25, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/816,165 06/15/2010 Edward G. Essey 13768.1758 2758
47973 7590 05/30/2017
WORKMAN NYDEGGER/MICROSOFT
60 EAST SOUTH TEMPLE
SUITE 1000
SALT LAKE CITY, UT 84111
EXAMINER
ONAT, UMUT
ART UNIT PAPER NUMBER
2194
NOTIFICATION DATE DELIVERY MODE
05/30/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
Docketing @ wnlaw. com
u sdocket @ micro soft .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte EDWARD G. ESSEY, IGOR OSTROVSKY,
POOJA NAGPAL, HUSEYIN S. YILDIZ,
HAZIM SHAFI, and WILLIAM T. COLBURN
Appeal 2016-006308
Application 12/816,1651
Technology Center 2100
Before KRISTEN L. DROESCH, JUSTIN BUSCH, and JOYCE CRAIG,
Administrative Patent Judges.
CRAIG, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—20. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm-in-part and enter a NEW GROUND OF REJECTION
under 37 C.F.R. §41.50(b).
1 According to Appellants, the real party in interest is Microsoft Corporation.
App. Br. 2.
Appeal 2016-006308
Application 12/816,165
INVENTION
Appellants’ application relates to indicating parallel operations with
user-visible events. Spec. 1 8. Claim 1 is illustrative of the appealed subject
matter and reads as follows:
1. At a computer system including a plurality of processor
elements and system memory, the computer system configured
to utilize the plurality of processor elements for parallel
execution of programs across a plurality of threads, a method for
presenting program execution details resulting from parallel
execution of a program at the computer system, the method
comprising:
an act of executing a program at the computer system, the
program configured for parallel execution on the plurality of
processor elements across the plurality of threads and the
program comprising outer layer programming abstractions
which abstract, and therefore hide, from a developer of the
program, internal specific implementation details of the parallel
execution which correspond to the outer layer programming
abstractions;
an act of inserting event markers in the runtime system that
correspond to events that are of interest to a user in order to
understand performance of the program, wherein the event
markers comprise markers which identify the outer layer
programming abstractions and markers which identify the
internal specific implementation details of the parallel execution
which have been abstracted from the developer;
an act of merging an event log with one or more of:
processor utilization information and thread activity information
into graphical data representing one or more of how the plurality
of processing elements and plurality of threads were utilized
during execution of instructions that generated the events of
interest, the processor utilization information indicative of the
utilization of each of the plurality of processing elements during
execution of the instructions, the thread activity indicating thread
state of the plurality of threads during execution of the
instructions;
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an act of supplementing the graphical data with further
graphical data representing visualizations of the event markers
generated by the instructions; and
an act of visually presenting the graphical data and the
further graphical data so as to visually indicate one or more of
processor utilization and thread activity at least during execution
of the instructions along with the visualizations of the event
markers indicating the events of interest.
REFERENCES AND REJECTIONS
Claims 1—9 and 12—19 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over the combination of Luke (US 5,168,554; issued Dec. 1,
1992) and Bruckhaus (US 6,052,515; issued Apr. 18, 2000).
Claims 10 and 11 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over the combination of Luke, Bruckhaus, and Toub et al. (US
2009/0320005 Al; published Dec. 24, 2009) (“Toub”).
Claim 20 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over the combination of Luke, Bruckhaus, and Tan et al., Automated Black
Box Testing Tool for a Parallel Programming Library, 2009 Int’l Conf. on
Software Testing Verification and Validation, publ. April 17, 2009
(available at http://ieeexplore.ieee.org/xpls/abs_all.jsp?amumber=4815364
&tag=l, last accessed July 17, 2012) (“Tan”).
ANALYSIS
Rejection of Claims 19 and 12—19 over Luke and Bruckhaus
In rejecting claim 1, the Examiner found that Luke teaches or suggests
all of the recited limitations, including event markers indicating an outer
layer of execution and markers indicating internal specifics of parallel
execution. Final Act. 3—6. The Examiner found that Luke does not
explicitly disclose the recited outer layer of execution and internal specifics
being abstracted from a developer, for which the Examiner relied on
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Bruckhaus. Final Act. 6—8 (citing Bruckhaus Figs. 1 and 2, col. 1:41—43,
col. 5:33-34).
Appellants contend the cited portions of Bruckhaus do not teach the
limitation “outer layer programming abstractions which abstract, and
therefore hide, from a developer of the program internal specific
implementation details of the parallel execution which correspond to the
outer layer programming abstractions,” recited in claim 1, because “nowhere
in Bruckhaus is parallel execution disclosed.” App. Br. 26.
Appellants’ arguments do not persuade us of Examiner error.
Appellants attack Bruckhaus individually even though the Examiner relied
on the combination of Luke and Bruckhaus as teaching or suggesting the
disputed features. Final Act. 6—8; Ans. 9—10; In re Mouttet, 686 F.3d 1322,
1332 (Fed. Cir. 2012) (citing In re Keller, 642 F.2d 413, 425 (CCPA 1981))
(“The test for obviousness is what the combined teachings of the references
would have suggested to those having ordinary skill in the art.”). The
Examiner found that Luke discloses event markers associated with events
that occur during a parallel execution. Final Act. 5—6 (citing Luke Fig. 4);
Ans. 9 (citing Luke col. 3:65—68). The Examiner further found that
Bruckhaus discloses event markers that show/hide abstracted
implementation details during an execution. Final Act. 6—7; Ans. 9. The
Examiner concluded “it would have been obvious to one of ordinary skill in
the art to modify Luke with the teachings of Bruckhaus to implement event
markers that show/hide abstracted implementation detail during parallel
execution.” Ans. 10. Appellants’argument that Bruckhaus does not teach
parallel execution (Reply Br. 3) is insufficient to rebut the Examiner’s
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factual findings or conclusion of obviousness, which are based on the
combined teachings of Luke and Bruckhaus.
Appellants next contend the Examiner erred because the recited
“visualizations of the event markers” identified in Bruckhaus (visual actions
40 and 42) “have nothing to do with parallel execution” and, thus, “are not
visualizations of the right kind of event markers.” App. Br. 27. For the
reasons discussed above, because Appellants have not presented persuasive
argument or objective evidence to rebut the Examiner’s findings based on
the combination of Luke and Bruckhaus, Appellants’ argument is not
persuasive of Examiner error. See Mouttet, 686 F.3d at 1332.
Appellants also argue that Bruckhaus’s visual actions 40 and 42 are
inserted in the source code before runtime and are not inserted “in the
runtime system,” as claim 1 requires. App. Br. 27. Appellants further argue
that the Examiner does not explain how the “event markers” in Luke would
be modified to accommodate the “event markers” in Bruckhaus. Id. at 28.
Those arguments are also unpersuasive. The Examiner found that
Luke teaches the limitation “an act of inserting event markers in the runtime
system,” recited in claim 1. Ans. 12. The Examiner further found that Luke
teaches event markers that are associated with events that occur during
parallel execution (Ans. 9) and Bruckhaus teaches event markers associated
with the “abstraction” feature missing in Luke (id. at 8). Appellants attack
Bruckhaus individually, even though the Examiner relied on the combined
teachings of Luke and Bruckhaus. Nonobviousness cannot be established by
attacking the references individually when the rejection is predicated upon a
combination of prior art disclosures. In re Merck & Co., 800 F.2d 1091,
1097 (Fed. Cir. 1986). Moreover, “[t]he test for obviousness is not whether
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Application 12/816,165
the features of a secondary reference may be bodily incorporated into the
structure of the primary reference. . . . Rather, the test is what the combined
teachings of those references would have suggested to those of ordinary skill
in the art.” Keller, 642 F.2d at 425.
For these reasons, we are not persuaded that the Examiner erred in
finding that the combination of Luke and Bruckhaus teaches or suggests the
limitations of claim 1.
Accordingly, we sustain the 35 U.S.C. § 103(a) rejection of
independent claim 1, as well as the 35 U.S.C. § 103(a) rejection of
independent claim 15, which Appellants argue is patentable for similar
reasons. App. Br. 28. We also sustain the Examiner’s rejection of
dependent claims 2—9, 12—14, and 16—19, for which Appellants make no
separate arguments for patentability. Id.
Rejection of Claims 10 and 11 over Luke, Bruckhaus, and Toub
Dependent claim 11 depends from claim l.2 App. Br. 36. Appellants
contend the Examiner erred in rejecting claim 11 because Toub does not
teach or suggest “inserting a plurality of event markers into the event log
during execution of the Parallel Language Integrated Query (PLINQ) query
to provide data on how PLINQ and Task Parallel Library (TPL) interact
together.” Id. at 28. In particular, Appellants argue that paragraph 32 of
Toub, cited by the Examiner, does not teach using event markers “to provide
2 Appellants incorrectly state that claim 11 depends from claim 10. App. Br.
28. We note that the limitation “the Parallel Language Integrated Query
(PLINQ) query,” recited in claim 11, lacks antecedent basis. We leave it to
the Examiner to evaluate claim 11 for compliance with 35 U.S.C. § 112,
second paragraph.
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Application 12/816,165
data on how PLINQ and Task Parallel Library (TPL) interact together,” as
claim 11 requires. Id. at 28—29.
We agree with Appellants that the Examiner has not identified
specific teachings in the references to show how the disputed limitation is
taught or suggested by the prior art. Toub teaches that some operating
environments are expected to include Parallel Extensions (PFX) to the .NET
Framework for covering data parallel components such as Parallel LINQ
(PLINQ) or Task Parallel Library (TPL). Toub 132. That, without more, is
insufficient to teach or suggest using event markers “to provide data on how
PLINQ and Task Parallel Library (TPL) interact together,” as recited in
claim 11.
Therefore, on the record before us, because the Examiner has not
shown how claim 11 as a whole is taught or suggested by the prior art, we do
not sustain the rejection of claim 11. We sustain the rejection of claim 10,
which does not recite the disputed limitation of claim 11 and for which
Appellants made no separate arguments for patentability.
Rejection of Claim 20 over Luke, Bruckhaus, and Tan
In rejecting claim 20, the Examiner found that Luke teaches all of the
recited limitations, except the outer layer of execution and internal specifics
being abstracted from a developer, for which the Examiner relied on
Bruckhaus (Final Act. 21), and “a Parallel Language Integrated Query
(PLINQ) query,” for which the Examiner relied on Tan (id. at 22).
Appellants contend the Examiner erred because the cited portions of
the prior art do no teach the limitation “an outer layer programming
abstraction which abstracts, and therefore hides, from a developer, internal
specific implementation details of parallel execution which correspond to the
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Application 12/816,165
outer layer programming abstraction,” recited in claim 20. App. Br. 29.
Appellants present arguments similar to those presented for claim 1—that
visual actions 40 and 42 of Bruckhaus “have nothing to do with parallel
execution” (id. at 30), that the “high level markers” in Bruckhaus are not
inserted “during execution” (id. at 31), and that the Examiner does not
explain how the “high level event markers” in Luke would be modified to
accommodate the “high level event markers” in Bruckhaus (id.).
Appellants’ arguments are unpersuasive for at least the reasons
discussed above in the context of claim 1. Accordingly, we sustain the
35 U.S.C. § 103(a) rejection of claim 20.
NEW GROUND OF REJECTION
Pursuant to our authority under 37 C.F.R. § 41.50(b), we enter a new
ground of rejection under 35 U.S.C. § 101 for claims 15—19 as directed to
patent-ineligible subject matter.
The preamble of claim 15 recites:
A computer program product for use at a computer
system including a plurality of processor elements and system
memory, the computer system configured to utilize the plurality
of processor elements for parallel execution of programs across
a plurality of threads, the computer program product for
implementing a method for presenting program execution
details resulting from parallel execution of a program at the
computer system, the computer program product comprising
one or more computer storage media having stored thereon
computer executable instructions that, when executed, cause the
computer system to perform the method, including the
following....
App. Br. 37 (emphasis added). The nominal recitation of a computer system
in the preamble adds nothing beyond indicating that the claimed instructions
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are executable by a processor, and does not significantly differentiate claim
15 from a set of instructions stored in a computer readable medium.
Moreover, the term “computer storage media,” when given its
broadest reasonable interpretation, may encompass a transitory signal (see
Ex parte Mewherter, 107 USPQ2d 1857, 1862 (PTAB 2013) (precedential)
(“The broadest reasonable interpretation of a claim drawn to a computer
readable medium (also called machine readable medium and other such
variations) typically covers forms of nontransitory tangible media and
transitory propagating signals per se in view of the ordinary and customary
meaning of computer readable media, particularly when the specification is
silent.”)). We find Appellants’ Specification does not limit the recited
“computer storage media” to nontransitory forms (see Spec. 24—25), and
thus we deem the scope of the recited “computer storage media” to
encompass transitory media such as signals or carrier waves. Therefore,
independent claim 15, as well as claims 16—19 which depend from claim 15,
are patent-ineligible under 35 U.S.C. § 101.
DECISION
We affirm the decision of the Examiner rejecting claims 1—10 and 12—
20.
We reverse the decision of the Examiner rejecting claim 11.
Pursuant to our authority under 37 C.F.R. § 41.50(b), we reject claims
15—19 under 35 U.S.C. § 101 as directed to nonstatutory subject matter.
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TIME PERIOD FOR RESPONSE
This decision contains a new ground of rejection pursuant to 37
C.F.R. § 41.50(b). 37 C.F.R. § 41.50(b) provides “[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review.”
Section 41.50(b) also provides:
When the Board enters such a non-final decision, the
appellant, within two months from the date of the decision,
must exercise one of the following two options with respect to
the new ground of rejection to avoid termination of the appeal
as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new Evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the prosecution
will be remanded to the examiner. The new ground of rejection
is binding upon the examiner unless an amendment or new
Evidence not previously of Record is made which, in the
opinion of the examiner, overcomes the new ground of rejection
designated in the decision. Should the examiner reject the
claims, appellant may again appeal to the Board pursuant to this
subpart.
(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same Record. The
request for rehearing must address any new ground of rejection
and state with particularity the points believed to have been
misapprehended or overlooked in entering the new ground of
rejection and also state all other grounds upon which rehearing
is sought.
Further guidance on responding to new grounds of rejection can be
found in MPEP § 1214.01 (9th ed., rev. 07.2015, Nov. 2015).
No time period for taking any subsequent action in connection with
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this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l)(iv).
AFFIRMED-IN-PART; 37 C.F.R, $ 41.50(b)
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