Ex Parte Ellerbrock et al

Patent Trial and Appeal Board

Jun 28, 2017

13835191 (P.T.A.B. Jun. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/835,191 03/15/2013 Philip J. Ellerbrock 5013899.061US1 5921
128836 7590 06/30/2017
Wnmhle Parlvle SanHriHae Rr Rioe T T P
EXAMINER
Attn: IP Docketing
P.O. Box 7037
YEW, CHIE W
Atlanta, GA 30357-0037 ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
06/30/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipdocketing @ wcsr. com
patentadmin @ B oeing. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte THE BOEING COMPANY1
Appeal 2017-002236
Application 13/835,191
Technology Center 2100
Before CARL W. WHITEHEAD JR., JASON V. MORGAN, and
IRVIN E. BRANCH, Administrative Patent Judges.
MORGAN, Administrative Patent Judge.
DECISION ON APPEAL
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1—7 and 9—15. Claims 8 and 16 are canceled. App. Br. 1.
We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART and enter NEW GROUNDS OF
REJECTION.
1 The inventors are Philip J. Ellerbrock, Robert N. Zettwoch, and
Joseph P. Winkelmann.
Appeal 2017-002236
Application 13/835,191
Invention
The disclosed invention is directed to an apparatus that includes a
non-volatile memory coupled to a device interface including a volatile
“shadow memory configured to store an image of the plurality of locations
of the non-volatile memory in a corresponding plurality of locations of the
volatile shadow memory.” Spec., Abstract.
Exemplary Claim
1. An apparatus comprising:
a non-volatile memory configured to store data in a plurality of
locations, the non-volatile memory including a base memory
and an expanded memory; and
a device interface coupled to the non-volatile memory and
including a volatile shadow memory configured to store an
image of the plurality of locations of the non-volatile memory
in a corresponding plurality of locations of the volatile shadow
memory, the volatile shadow memory including a base shadow
memory configured to store an image of the base memory, and
an expanded shadow memory configured to store an image of a
only selectable subset of the expanded memory,
wherein the device interface is couplable to a bus controller via
a digital network bus, and configured to receive a command
across the digital network bus from the bus controller, and in
response thereto, the device interface is configured to write data
from the digital network bus to a location in the non-volatile
memory,
wherein the device interface being configured to write data to
the location in the nonvolatile memory includes the device
interface being configured to write the data to the
corresponding location in the volatile shadow memory, and
thereafter write the data from the corresponding location in the
volatile shadow memory to the location in the non-volatile
memory, and
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wherein in a first instance, the location in the non-volatile
memory is a location in the base memory and the corresponding
location in the volatile memory is a location in the base shadow
memory, and in a second instance, the location in the non­
volatile memory is a location in the expanded memory and the
corresponding location in the volatile memory is a location in
the expanded shadow memory.
Rejections
The Examiner rejects claims 1—7 and 9-15 under 35U.S.C. § 112,
first paragraph, as failing to comply with the written description
requirement. Final Act. 4—6.
The Examiner rejects claims 1 and 9 under 35 U.S.C. § 103(a) as
being unpatentable over Russell (US 5,623,604, issued. Apr. 22, 1997) and
Mantey (US 2003/0020512 Al, published Jan. 30, 2003). Final Act. 6—16.
The Examiner rejects claims 2 and 10 under 35 U.S.C. § 103(a) as
being unpatentable over Russell, Mantey, Aral (US 2012/0005452 Al,
published Jan. 5, 2012), and Chen (US 2010/0306448 Al, published Dec. 2,
2010). Final Act. 16-21.
The Examiner rejects claims 3 and 11 under 35 U.S.C. § 103(a) as
being unpatentable over Russell, Mantey, Aral, and Alexander (US
5,363,334, issued Nov. 8, 1994). Final Act. 22—27.
The Examiner rejects claims 4, 5, 12, and 13 under 35 U.S.C. § 103(a)
as being unpatentable over Russell, Mantey, Aral, Alexander, Nakagawa
(US 2008/0082744 Al, published Apr. 3, 2008), and Lin (US 2004/0019754
Al, published. Jan. 29, 2004). Final Act. 27—35.
The Examiner rejects claims 6, 7, 14, and 15 under 35 U.S.C. § 103(a)
as being unpatentable over Russell, Mantey, Aral, and Nakagawa. Final
Act. 36-43.
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ANALYSIS
35 U.S.C. § 112, first paragraph—Claims 1—7 and 9—15
The Examiner rejects claims 1—7 and 9—15 under 35 U.S.C. § 112,
first paragraph, because the Examiner finds the Specification does not
“disclose the details of writing data specifically from the base shadow
memory of volatile memory to the base memory of nonvolatile memory” or
“details of writing data specifically from the expanded shadow memory of
volatile memory to the expanded memory of the non-volatile memory.”
Final Act. 5. Thus, the Examiner finds the Specification provides
insufficient written description support for “‘writing from shadow memory
to non-volatile memory’ [that] results in writing base shadow memory into
base memory of non-volatile memory and writing expanded shadow
memory into expanded memory of non-volatile memory.” Id.
The Examiner also objects to the Specification as failing to provide
proper antecedent basis for the claimed subject matter. Id. at 3 (citing 37
C.F.R. § 1.75(d)(1) and MPEP § 608.01(o)). Because both this objection
and the Examiner’s 35 U.S.C. § 112, first paragraph, rejection turn on the
same issue of whether the claimed subject matter finds adequate support in
the original disclosure, our decision is dispositive to both the objection and
the rejection. Cf. MPEP §§ 2163.06(11); 608.04(c).
Appellant contends the Examiner erred because the Specification
discloses that “the base shadow memory and expanded shadow memory of
the volatile shadow memory shadow respectively the base memory and
expanded memory of the non-volatile memory.” App. Br. 5 (citing Spec. 14,
1. 7—15,1. 5). Appellant notes the Specification discloses that “[a] device­
memory write command may point to a memory location, and may be used
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Application 13/835,191
to update data in the shadow memory, after which a write cycle back to the
non-volatile memory may start.” App. Br. 6 (citing Spec. 24—25).
Appellant’s arguments accord with the Specification, which discloses
that “shadow memory 504 may include a base shadow memory 504a where
the base memory 502a of the non-volatile device storage memory 502 may
be fully shadowed” (Spec. 14,11. 21—23) and that similarly “a selectable
portion of the expanded memory, such as a subset (e.g., one) of the
expanded memory segments, may be shadowed in the expanded shadow
memory at any given time” {id. at 14,1. 30—15,1. 1). The Specification
further details that “device-memory write command may be used to update
data in the shadow memory 504 (both base 504a and expanded 504b), which
after a write start timeout time may start a write cycle back to the non­
volatile device storage memory 502.” Id. at 25,11. 15—17.
The Examiner responds by noting “[t]he mere fact that the shadow
memory stores corresponding images of the non-volatile memory does not
imply that [a] write to base shadow memory results in [a] subsequent write
back to base memory.” Ans. 44. The Examiner cites to Parley (US 2010/
0174847 Al, published July 8, 2010) as secondary evidence that memory
writes from an address in base shadow memory need not necessarily result
in a write back to the same address in base memory. See Ans. 44-45 (citing,
e.g., Parley, Figs. 22A—B). That is, the Examiner relies on Parley to show
that the Specification “does not appear to explicitly disclose ‘write from an
address (for example address OOOh) in base shadow memory to the same
address (for example address OOOh) in base memory during write back.’”
Ans. 44.
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The Examiner’s findings are insufficient because the feature at
issue—the feature the Examiner finds is not actually or inherently disclosed
by the Specification’s written description—is not claimed. Claim 1 recites a
location in non-volatile memory and a corresponding location in volatile
shadow memory without reciting that the location and the corresponding
location have the same address. Claim 1 has similar recitations directed to a
location in non-volatile memory being either a location in base memory or a
location in expanded memory and a location in volatile memory being a
location in base shadow memory or a location in expanded shadow memory.
Thus, the locations and corresponding locations, as recited, must merely
correspond—rather than having identical addresses. Moreover, the
Specification discloses the shadowing of base memory 502a in base shadow
memory 504a, and the shadowing of expanded memory 502b in expanded
shadow memory 504b, in a manner consistent with the disputed recitations.
See Spec. 14,11. 21—30, 25,11. 15—17, and Fig. 5. Thus, we agree with
Appellant that the Specification conveys with reasonable clarity to those
skilled in the art that the inventors were in possession of the claimed
invention. Vas-Cath, Inc. v. Mahurkar, 935 F.2d 1555, 1563—64 (Fed. Cir.
2002).
Accordingly, we do not sustain the Examiner’s 35U.S.C. § 112, first
paragraph, rejection of claim 1, and claims 2—7 and 9-15, which are
similarly rejected.
35 U.S.C. § 103(a)—Claims 1—7
In rejecting claim 1 under 35 U.S.C. § 103(a), the Examiner finds that
Russell’s Ethernet network controller 206 and DRAM 220 disclose a device
interface (Ethernet network controller) coupled to the non-volatile memory
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and including a volatile shadow memory (DRAM). Final Act. 8 (citing
Russell, Figs. 3, 4).
Russell’s Figure 4 is reproduced below.
216
PRINTER
EXPANSION
PORT
Russell’s Figure 4 illustrates Ethernet Network Controller 206
coupled to multiple other components, including DRAM 220.
Appellant contends the Examiner erred because “[t]he network
controller is coupled to DRAM. By contrast, the device interface of the
claimed invention includes volatile shadow memory.” App. Br. 9; see also
Reply Br. 5—6. The Examiner does not present findings that show Russell
teaches or suggests having Ethernet Network Controller 206 include DRAM
220. Rather, the Examiner interprets the disputed recitation to include
“wherein ‘the coupling includes a volatile shadow memory.’” Ans. 48
(emphasis added). However, the Examiner’s interpretation of the claimed
invention is unreasonably broad.
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The Examiner interprets the recitation of “including a volatile shadow
memory” as modifying a coupling even though claim 1 recites “a device
interface coupled to the non-volatile memory and including a volatile
shadow memory” (emphasis added). That is, the claim describes a feature of
the device interface (i.e., that it is “coupled to” a non-volatile memory)
without explicitly reciting a noun such as a “coupling” that implements the
claimed feature. The Examiner’s interpretation of “including” as modifying
the non-existent “coupling” recitation is grammatically untenable. Thus, we
agree with Appellants that the broadest reasonable interpretation of the
claimed invention requires that the device interface, not a coupling, includes
the volatile shadow memory.
Because the Examiner’s findings do not show that Russell, even in
combination with the other references, teaches or suggests the claimed
device interface including a volatile shadow memory, we do not sustain the
Examiner’s 35 U.S.C. § 103(a) rejection of claim 1, and claims 2—7, which
contain the same recitation.
35 U.S.C. § 103(a)—Claims 9—15
Method claim 9 does not recite a device interface including a volatile
shadow memory in the manner of claim 1. Therefore, our reasoning for
reversing the Examiner’s 35 U.S.C. § 103(a) rejection of claim 1 is
inapplicable to claim 9.
Russell teaches that “[a] ROM firmware image is . . . downloaded to
the DRAM .... [Subsequently,] the EPROM [electronically erasable read­
only-memory] is flashed with the new ROM image.” Russell col. 22,11. 57—
63. In rejecting claim 9 under 35 U.S.C. § 103(a), the Examiner finds that
this flashing of a ROM image from DRAM to an EPROM teaches or
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suggests a volatile shadow memory configured to store an image of the
plurality of locations of the non-volatile memory in a corresponding
plurality of locations of the volatile shadow memory. Final Act. 12 (citing,
e.g., Russell, Fig. 4, col. 22,11. 57—63). Russell further teaches that “it is
possible to select the specific modules that are retrieved from EPROM 222
for execution out of DRAM 220.” Russell col. 23,11. 63—65. The Examiner
finds that this capability of selecting modules in the EPROM to be stored in
the DRAM teaches or suggests the non-volatile memory including an
expanded shadow memory configured to store an image of “a onlf [sic]
selectable subset of the expanded memory. Final Act. 12—13 (citing, e.g.,
Russel col. 23,11. 58—66). Mantey teaches programming field
programmable gate array (FPGA) code into an EEPROM associated with
FPGAs. Mantey 12. In particular, Mantey teaches updating FPGA codes to
an EEPROM by first transferring appropriate FPGA configuration code to a
memory system (e.g., RAM) and thereupon transferring the FPGA
configuration code into EEPROM devices. Id. 127. The Examiner finds
this transfer teaches or suggests the claimed locations features in a first
instance, while Russell’s ROM image flashing teaches or suggests the
claimed locations features in a second instance. Final Act. 14—15 (citing,
e.g., Mantey ^fl[ 2, 27, and Fig. 2).
Appellant contends the Examiner erred because “Russell does not
disclose that the EEPROM stores the ROM firmware in locations, and that
the DRAM stores the ROM firmware image in corresponding locations, as
is required by the claim.” App. Br. 10; see also id. at 11—12; Reply Br. 6—7.
However, we agree with the Examiner that RusselFs ROM image comprises
data at multiple locations. See Ans. 49. Moreover, as discussed above with
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respect to the Examiner’s 35 U.S.C. § 112, first paragraph, rejection, the
claimed location and corresponding location need not have identical
addresses in both memories for the locations to correspond. Thus, we agree
with the Examiner that the locations in Russell’s DRAM where data in a
ROM image is stored correspond to the locations in Russell’s EPROM to
which the data from the ROM image is flashed. See Russell col. 22,11. 57—
63.
Appellant further contends the Examiner erred because the Examiner
relies on another feature of Russell—selection of firmware modules from the
EPROM for loading into and execution from DRAM—that “has nothing to
do with the ROM firmware image or its being flashed from the DRAM to
EEPROM, cited by the Examiner for storage of the image of only a subset of
expanded memory.” App. Br. 11 (citing, e.g., Russell col. 23,11. 58—66); see
also Reply Br. 7—8. However, Appellant’s argument is not commensurate
with the scope of the claimed invention.
In particular, the claimed invention recites both “a volatile shadow
memory configured to store an image of the plurality of locations of the non­
volatile memory in a corresponding plurality of locations of the volatile
shadow memory” and “an expanded shadow memory [included in the
volatile shadow memory] configured to store an image of a only [sic]
selectable subset of the expanded memory.” A volatile shadow memory,
and an expanded shadow memory included in the volatile shadow memory,
can be configured to or capable of storing images from different sources for
different purposes.
The Examiner’s findings are consistent with evidence that Russell
both discloses: (1) the storing of an image in the DRAM (i.e., the volatile
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shadow memory as a whole) for purposes of flashing the image to the
EPROM (i.e., the non-volatile memory) and (2) the storing of an image in a
portion of the DRAM (i.e., an expanded shadow memory) for purposes of
reading a selected module from the EPROM (i.e., from an expanded non­
volatile memory) for execution. See Final Act. 12—13. These teachings and
suggestions fall within a reasonably broad interpretation of the disputed
recitations for the reasons discussed above.
Appellant also argues that the Examiner erred in relying on Mantey
because Mantey merely “discloses that an FPGA code is transferred to RAM
(base shadow memory), and then from the RAM to an EEPROM (base
memory).” App. Br. 12; see also Reply Br. 9-10. In particular, Appellant
argues “Mantey does not disclose data written to a location in the EEPROM
is written to a corresponding location in the RAM, and then from the
corresponding location in the RAM to the location in the EEPROM.”
App. Br. 12. However, for the same reasons discussed above with respect to
Russell’s teachings of flashing an image to an EPROM, Appellant’s
argument does not distinguish the claimed writing of data in a first instance
from the teachings and suggestions of Mantey.
Appellant further argues that the Examiner erred in combining the
teachings and suggestions of Russell and Mantey because “Russell’s system
does not include an FPGA [and] therefore has no need for . . . Mantey’s
method of programming FPGA code.” Id. at 13; see also Reply Br. 10-11.
However, the Examiner’s findings show that “programming FPGA code into
[an] EEPROM associated with FPGAs, or into an EEPROM of FPGAs,
through a central point” was known in the art. Final Act. 16 (citing Mantey
12). The Examiner’s findings also show that an artisan of ordinary skill
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would have recognized that Mantey’s teachings and suggestions relate to
Russell’s configuration code teachings. Ans. 54. Appellant’s conclusory
contention that “Russell’s system [would not] yield any benefit from[]
Mantey’s method of programming FGPA code” (App. Br. 13) is
unpersuasive because the Examiner’s findings show that modifying Russell
using the teachings and suggestions of Mantey would have represented the
combination of familiar elements using known methods to yield predictable
results.
For these reasons, we sustain the Examiner’s 35 U.S.C. § 103(a)
rejection of claim 9, and claims 10-15, which Appellants do not argue
separately with persuasive specificity. App. Br. 13—15.
NEW GROUNDS OF REJECTION
We newly reject claims 1—7 and 9-15 under 35 U.S.C. § 112, second
paragraph. Both independent claims 1 and 9 recite:
wherein in a first instance, the location in the non-volatile
memory is a location in the base memory and the corresponding
location in the volatile memory is a location in the base shadow
memory, and in a second instance, the location in the non­
volatile memory is a location in the expanded memory and the
corresponding location in the volatile memory is a location in
the expanded shadow memory.
This “wherein” clause, being directed to first and second instances, is
directed to method steps (i.e., operations at different instances). This renders
apparatus claim 1 indefinite because it is unclear whether infringement
occurs when the apparatus is created or when the apparatus is used in the
first and second instances. See In re Katz Interactive Call Processing Patent
Litigation, 639 F.3d 1303, 1318 (Fed. Cir. 2015).
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Method claim 9 does not share this exact defect. However, this
“wherein” clause renders both claim 1 and claim 9 indefinite by creating
ambiguity in the meaning of “location” and “corresponding location” in the
recitations that precede the “wherein” clause. For example, both claims
have recitations directed to writing “data to the location in the non-volatile
memory” (emphasis added). Such writing includes writing “the data to the
corresponding location in the volatile shadow memory” (emphasis added).
It is only “thereafter” that “the data from the corresponding location in the
volatile shadow memory to the location in the non-volatile memory” is
written (emphases added).
This data writing, to a corresponding location in the volatile shadow
memory and thereafter a location in the non-volatile memory, encompasses
the two writes occurring at different instances (as evidenced by the second
write taking place after the first write). The “wherein” clause recites the
location and the corresponding location being different in first and second
instances (i.e., a location in base memory and a corresponding location in
base shadow memory in a first instance and a location in expanded memory
and a corresponding location in expanded shadow memory in a second
instance). Due to the “wherein” clause referring to the first and second
instances, the meaning of location and corresponding location are explicitly
not fixed between instances. Thus, the claims encompass scenarios such as
writing, in a first instance, data to a corresponding location in base shadow
memory and, thereafter (i.e., in a second instance), writing the data to
expanded memory. Therefore, the claims are ambiguous as to: (1) whether
the claimed write to a location in non-volatile memory and write to a
corresponding location on volatile shadow memory is limited to situations
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where the types of memories (i.e., base vs. expanded) written to match or (2)
whether the claimed writes encompass situations where the types of
memories can differ given that the writes occur at different instances. As
such, the scope of claims 1 and 9 is amenable to two plausible
interpretations rendering claims 1 and 9 ambiguous and therefore indefinite.
Accordingly, we newly reject claims 1 and 9, and claims 2—7 and 10-
15, which contain the same recitations, under 35 U.S.C. § 112, second
paragraph, as being indefinite.
DECISION
We reverse the Examiner’s decision rejecting claims 1—7 and 9—15
under 35 U.S.C. § 112, first paragraph.
We reverse the Examiner’s decision rejecting claims 1—7 under 35
U.S.C. § 103(a).
We affirm the Examiner’s decision rejecting claims 9—15 under 35
U.S.C. § 103(a).
We newly reject claims 1—7 and 9—15 under 35 U.S.C. § 112, second
paragraph.
This Decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.50(b). Section 41.50(b) provides “[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review.” Section 41.50(b) also provides:
When the Board enters such a non-final decision, the appellant,
within two months from the date of the decision, must exercise
one of the following two options with respect to the new ground
of rejection to avoid termination of the appeal as to the rejected
claims:
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(1) Reopen prosecution. Submit an
appropriate amendment of the claims so rejected or
new Evidence relating to the claims so rejected, or
both, and have the matter reconsidered by the
examiner, in which event the prosecution will be
remanded to the examiner. The new ground of
rejection is binding upon the examiner unless an
amendment or new Evidence not previously of
Record is made which, in the opinion of the
examiner, overcomes the new ground of rejection
designated in the decision. Should the examiner
reject the claims, appellant may again appeal to the
Board pursuant to this subpart.
(2) Request rehearing. Request that the
proceeding be reheard under §41.52 by the Board
upon the same Record. The request for rehearing
must address any new ground of rejection and state
with particularity the points believed to have been
misapprehended or overlooked in entering the new
ground of rejection and also state all other grounds
upon which rehearing is sought.
Further guidance on responding to a new ground of rejection can be
found in the Manual of Patent Examining Procedure § 1214.01 (9th Ed.,
Rev. 07.2015, Nov. 2015).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).
AFFIRMED-IN-PART
37 C.F.R, § 41.50(b)
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