Ex Parte Devine

Patent Trial and Appeal BoardAug 22, 2013

10787376 (P.T.A.B. Aug. 22, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/787,376 02/26/2004 Daniel John Devine Devine 2-2 4422 47386 7590 08/22/2013 RYAN, MASON & LEWIS, LLP 1300 POST ROAD SUITE 205 FAIRFIELD, CT 06824 EXAMINER VIDWAN, JASJIT S ART UNIT PAPER NUMBER 2181 MAIL DATE DELIVERY MODE 08/22/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte DANIEL JOHN DEVINE ____________ Appeal 2011-002783 Application 10/787,376 Technology Center 2100 ____________ Before DENISE M. POTHIER, BRYAN F. MOORE, and MATTHEW CLEMENTS, Administrative Patent Judges. POTHIER, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 4, 5, 10, 11, 17, and 18.1 Claims 1-3, 6-9, 12-16, 19, and 20 have been canceled. App. Br. 2. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 Appellant makes conflicting statements, indicating both that claims 4, 5, 10, 11, 17, and 18 are on appeal (App. Br. 1) and also only claims 5, 11, and 18 are being appealed (App. Br. 2). In order to avoid piecemeal prosecution, we find that Appellant intends to appeal claims 4, 5, 10, 11, 17, and 18. Appeal 2011-002783 Application 10/787,376 2 Invention Appellant’s invention relates to high speed interfaces between host computers and peripheral devices. See generally Spec. 1:5-6. Illustrative independent claim 5 is reproduced below: 5. An integrated controller for use in a peripheral device for controlling high speed communications between a host computer and said peripheral device, comprising: a processor integrated with said controller for controlling communications on a bus using one or more communication functions, wherein said processor performs at least one function for said peripheral device in addition to said one or more communication functions, wherein said processor provides processing capacity for use by said peripheral device, and wherein said high speed communications conform to a USB standard. The Examiner relies on the following as evidence of unpatentability: Adams US 5,987,568 Nov. 16, 1999 Sartore US 6,493,770 B1 Dec. 10, 2002 The Rejections Claims 4, 5, 10, 11, 17, and 18 are rejected under 35 U.S.C. § 103(a) as unpatentable over Sartore and Adams. Ans. 3-4. THE CONTENTIONS Regarding independent claim 5, the Examiner finds that Sartore teaches many of its limitations, including a processor for controlling communications using a communication function (Ans. 3-4) and additionally cites to Adams to teach a processor that controls a function for the peripheral device (Ans. 4). Appeal 2011-002783 Application 10/787,376 3 Appellant argues Sartore does not teach a single processor that (1) performs at least one function for the peripheral device in addition to a communication function and (2) provides processing capacity for use by the peripheral device. App. Br. 4; Reply Br. 2-3, 5. Rather, Appellant asserts Sartore teaches the processor (e.g., 72) is only used to reconfigure the peripheral and “not used for the normal operation of the peripheral.” App. Br. 4; Reply Br. 5. Appellant further contends that Adams fails to teach a processor integrated with a controller for performing one function for a peripheral device in addition to one communication function or provide processing capacity for use by the peripheral. App. Br. 4; Reply Br. 5-6. ISSUE Under § 103, has the Examiner erred in rejecting claim 5 by finding that Sartore and Adams collectively would have taught or suggested a processor that (1) performs a function for the peripheral device in addition to a communication function and (2) provides processing capacity for use by the peripheral device? ANALYSIS Based on the record before us, we find no error in the Examiner’s rejection of independent claim 5. Regarding the specific recitation that the processor performs “one or more communication functions,” Appellant repeats the claim language and asserts that Sartore’s central processing unit (CPU) 72 does not teach this limitation. See App. Br. 4. Given that there is no underlying argument as to how Sartore’s CPU 72 fails to perform the communication functions (see id.), we agree with the Examiner (Ans. 5) that Appeal 2011-002783 Application 10/787,376 4 Appellant has not argued the merits of this limitation in the Appeal Brief, presenting a nominal argument at best. For the first time in the Reply Brief, Appellant asserts that CPU 72 does not perform any communication functions. Reply Br. 3. We consider this argument waived. See Ex parte Borden, 93 USPQ2d 1473, 1474 (BPAI 2010) (informative). Nonetheless, Appellant admits that Sartore’s processor 72 performs a reconfiguring function for the peripheral. See App. Br. 4. We find that Sartore’s reconfiguring function can reasonably be a communication function (see Ans. 3 (discussing Fig. 2)), given that the recited “communication function[]” is not defined in the disclosure (see generally Spec.). That is, Sartore teaches a bus connection between a host and the peripheral device for communications (see col. 4, ll. 65-67; Fig. 2), and an ordinarily skilled artisan would have recognized CPU 72’s reconfiguring (col. 5, ll. 11-16) at least suggests performing a communication function for the peripheral device (e.g., configuring circuitry for data communication over the bus). We therefore are not persuaded that Sartore fails to teach a processor that performs “one . . . communication function[].” The Appellant further contends that neither Sartore nor Adams teaches a single processor performing both a communication function and at least one function for the peripheral device in addition to the communication function. App. Br. 4-5; Reply Br. 2-4. Attacking these references individually does not show nonobviousness where rejections are based on combinations of references. See In re Merck & Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986). Notably, the Examiner proposes to combine the teachings of Sartore and Adams to yield a processor that performs both a Appeal 2011-002783 Application 10/787,376 5 communication function and at least one function for the peripheral device. See Ans. 3-4. While Appellant argues that Sartore’s processor “is not used for the normal operation of the peripheral,” the term “normal operation” is not in claim 5. The Examiner finds that the CPU of the peripheral device in Sartore would inherently perform a function for the peripheral device (see Ans. 3-4, 6), but nonetheless, additionally cites to Adams to teach a peripheral device uses a processor to perform and control signal processing functions. Ans. 4 (citing col. 4, ll. 31-45). Adams also suggests a processor that performs multiple functions (e.g., multiple signal processing functions) to reduce components, complexity, size, power, heat, and costs. See Ans. 4, 6 (citing col. 4, ll. 31-45). Thus, when combining Adams’ teaching of performing multiple functions with Sartore’s processor, the combination suggests a processor that performs multiple functions, including a communication function (e.g., reconfiguring) and at least one function for the peripheral device (e.g., signal processing function). Appellant alleges that the modifications based on the references’ teachings, as proposed by the Examiner, require an additional processor. Reply Br. 3-4. We disagree. Based on Adams teaching (col. 4, ll. 31-45), one skilled in the art employing creative inferences and one’s background knowledge would have recognized using a processor to perform multiple functions, such as a communication function and peripheral device function. See KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007). Furthermore, there is insufficient evidence that CPU 72 in Sartore cannot also perform the digital signal processing functions taught by Adams as the Examiner proposes or would be rendered inoperable by such an additional function. Appeal 2011-002783 Application 10/787,376 6 We therefore are not persuaded that Sartore fails to teach or suggest a processor that performs both a function for the peripheral device and a communication function as recited. Concerning the disputed limitation that the processor provides processing capacity for use by the peripheral device (App. Br. 4-5), the Examiner discusses Sartore–not Adams. Ans. 3, 5-6. Attacking Adams individually thus does not show nonobviousness. See Merck, 800 F.2d at 1097. Notably, Sartore teaches code executed by CPU 72 and applicable to the peripheral device. Col. 5, ll. 11-12, 50-51. However, we also find that Adams’ processor performing digital processing for the peripheral device (col. 4, ll. 31-45) teaches providing processing capacity for use by the peripheral device as broadly as recited. See Ans. 6. For the foregoing reasons, Appellant has not persuaded us of error in the rejection of (1) independent claim 5; (2) claims 11 and 18, which recite commensurate limitations; and (3) claims 4, 10, and 17 not separately argued with particularity. CONCLUSION The Examiner did not err in rejecting claims 4, 5, 10, 11, 17, and 18 under § 103. DECISION The Examiner’s decision rejecting claims 4, 5, 10, 11, 17, and 18 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). Appeal 2011-002783 Application 10/787,376 7 AFFIRMED gvw