Ex Parte Creamer et al

Patent Trial and Appeal BoardMay 23, 2017

11382315 (P.T.A.B. May. 23, 2017)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/382,315 05/09/2006 Thomas E. Creamer BOC920060021US1 (075) 5879 46322 7590 CRGO LAW STEVEN M. GREENBERG 7900 Glades Road SUITE 520 BOCA RATON, EL 33487 05/25/2017 EXAMINER STORK, KYLE R ART UNIT PAPER NUMBER 2144 NOTIFICATION DATE DELIVERY MODE 05/25/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing@crgolaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte THOMAS E. CREAMER and CURTIS E. HRISCHUK1 Appeal 2015-007383 Application 11/382,315 Technology Center 2100 Before ERIC B. GRIMES, MELANIE L. McCOLLUM, and ULRIKE W. JENKS, Administrative Patent Judges. McCOLLUM, Administrative Patent Judge. DECISION ON APPEAL This is an appeal under 35U.S.C. § 134 involving claims to an XML processing method, system, and computer program product. The Examiner has rejected the claims as obvious. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. STATEMENT OF THE CASE Claims 1—13 are on appeal (App. Br. 1). Claim 1 is illustrative and reads as follows: 1 Appellants identify the real party in interest as International Business Machines Corporation (App. Br. 2). Appeal 2015-007383 Application 11/3 82,315 1. An optimized extensible markup language (XML) schema validation and XML document parsing method comprising: placing an XML document in shared memory disposed between multiple different central processing units (CPUs) of a symmetric multiprocessing (SMP) architecture and a multi-core CPU having multiple CPU cores, and signaling a local XML processing element in one of the multiple CPU cores to process the XML document; receiving a notification to retrieve results provided by the XML processing element in processing the XML document; and, retrieving the results from the shared memory. Claims 6 and 9 are also independent. Claim 6 is directed to an XML processing system comprising, among other things, “shared memory disposed between multiple different CPUs of a symmetric multiprocessing (SMP) architecture and a multi-core CPU having multiple CPU cores” (App. Br. 12—13). Claim 9 is directed to a computer program product comprising, among other things, “computer usable program code for placing an XML document in shared memory disposed between multiple different CPUs of a symmetric multiprocessing (SMP) architecture and a multi-core CPU having multiple CPU cores” (id. at 14). Claims 1, 3, 5, 9, and 11 stand rejected under 35 U.S.C. § 103(a) as obvious over Letz2 in view of Scales3 (Final Act. 2). Claims 2, 4, 6, 7, 10, 12, and 13 stand rejected under 35 U.S.C. § 103(a) as obvious over Letz in view of Scales and Letz24 (id. at 6). 2 Stefan Letz, Cell Processor-Based Workstation for XML Offload — System Architecture and Design, Diploma Thesis, University of Leipzig (May 2005). 3 Scales et al., US 5,950,228, Sept. 7, 1999. 4 Letz2 refers to chapter 3 of Letz (Final Act. 6). 2 Appeal 2015-007383 Application 11/3 82,315 Claim 8 stands rejected under 35 U.S.C. § 103(a) as obvious over Letz in view of Scales, Letz2, and Kleinsorge5 {id. at 11). I In rejecting claims 1 and 9, the Examiner relies on Letz for disclosing many of the features of these claims (Final Act. 2—5). However, the Examiner finds that “Letz fails to specifically disclose shared memory disposed between multiple different CPUs of a symmetric multiprocessing architecture” {id. at 3). The Examiner relies on Scales for disclosing “shared memory disposed between multiple different CPUs of a symmetric multiprocessing architecture and additional CPUs” {id.). The Examiner concludes that it would have been obvious “to have combined Scales with Letz, as it would have allowed a user to efficiently implement parallel processing of data with a good price/performance ratio . . . , while maintaining the ability to offload certain processes to the multi-core processor for efficient processing” {id.). Analysis Appellants argue: [Njeither Letz nor Scales teaches the disposal of shared memory between multiple different CPUs on the one hand, and a multi core processor on the other hand. Rather, Examiner only draws the conclusory statement that so much would be obvious to “solve different computing problems” and for “efficient processing”. Examiner’s conclusory statement, however, is completely devoid of any evidence and merely represents Examiner’s subjective justification for maintaining a[n obviousness] rejection. (App. Br. 6.) 5 Kleinsorge et al., US 6,247,109 Bl, June 12, 2001. 3 Appeal 2015-007383 Application 11/3 82,315 In response, the Examiner argues: The SMP architecture provides efficient implementation of parallel processing of data with a good price/performance ratio (Scales: column 1, lines 36-42). A multi-core processor provides efficient processing of computationally intensive processes by exploiting the underlying hardware architecture (Letz: page 1). One of ordinary skill in the art at the time of the applicant’s invention would have recognized that disposing memory between these two types of processors would have allowed a user to process contents in the memory in order to reap the benefits afforded by each type of processor. A skilled artisan would have recognized that combining Scales with Letz would have allowed a user to implement parallel processing with a good price/performance ratio, offered by a SMP architecture, for less computationally intensive processes (Scales: column 1, lines 36- 42) while maintaining the ability to leverage the multi-core processor to process computationally intensive processes (Letz: page 1). (Ans. 4—5.) We conclude that Appellants have the better position. Scales discloses shared memory disposed between multiple CPUs of an SMP architecture (Scales, col. 1,11. 3 5—42). In addition, Letz discloses offloading XML parsing to a multi-core CPU (Letz, Abstract & § 2.2). However, we agree with Appellants that the Examiner does not adequately explain why it would have been obvious for the shared memory that is disposed between the multiple CPUs of the SMP architecture to also be shared by the multi-core CPU. The Examiner states that it would have been obvious “to have combined Scales with Letz, as it would have allowed a user to efficiently implement parallel processing of data with a good price/performance ratio . . . , while maintaining the ability to offload certain processes to the multi core processor for efficient processing” (Ans. 3). However, this reasoning 4 Appeal 2015-007383 Application 11/3 82,315 does not explain why one of ordinary skill in the art would have shared memory between the SMP and the multi-core CPU, rather than offloading the XML data to the multi-core CPU, as described in Letz. Conclusion The Examiner has not set forth a prima facie case that Letz and Scales suggest shared memory disposed between multiple different CPUs of an SMP architecture and a multi-core CPU having multiple CPU cores. We therefore reverse the obviousness rejection of claims 1 and 9 and of claims 3, 5, and 11, which depend from claims 1 or 9. II In rejecting claims 2, 4, 6—8, 10, 12, and 13, the Examiner additionally relies on Letz2 and/or Kleinsorge (Final Act. 6—11). However, the Examiner does not explain how Letz2 or Kleinsorge overcomes the deficiency noted above (id.). Thus, we also reverse the obviousness rejections of claims 2, 4, 6—8, 10, 12, and 13, which recite or depend from a claim that recites shared memory disposed between multiple different CPUs of an SMP architecture and a multi-core CPU having multiple CPU cores. REVERSED 5