Ex Parte Corisis et al

Patent Trial and Appeal Board

Feb 25, 2019

14258875 (P.T.A.B. Feb. 25, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/258,875 04/22/2014 David J. Corisis
52142 7590 02/27/2019
FLETCHER YODER (MICRON TECHNOLOGY, INC.)
P.O. BOX 692289
HOUSTON, TX 77269-2289
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
06-0847.01 (MICS:0169-1) 1837
EXAMINER
GRAYBILL, DAVIDE
ART UNIT PAPER NUMBER
2894
NOTIFICATION DATE DELIVERY MODE
02/27/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket@fyiplaw.com
manware@fyiplaw.com
s trickland @fyiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAVID J. CORISIS and MATT SCHWAB
Appeal2018-000155
Application 14/258,875
Technology Center 2800
Before MICHAEL P. COLAIANNI, GEORGIANNA W. BRADEN, and
SHELDON M. McGEE, Administrative Patent Judges.
COLAIANNI, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2018-000155
Application 14/258,875
Appellants 1 appeal under 35 U.S.C. § 134 the final rejection of
claims 1-5, 8-13, 15, 16, and 18-20. Claims 6, 7, and 17 are withdrawn
from consideration by the Examiner. Claims 14 and 21-26 has been
canceled. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b ).
We REVERSE.
The invention is directed to microelectronic packaging including a
multi-chip or system-in-package modules with semiconductor devices in a
stacked arrangement. (Claim 1; Spec. ,r 2). Claim 1 is illustrative and
reproduced below:
1. A semiconductor device, comprising:
a first preassembled subassembly individually fabricated,
assembled, and tested to ensure functionality comprising:
a substrate; and
at least one semiconductor die attached to the substrate,
wherein the at least one semiconductor die comprises a second
memory die mounted on a first memory die; and
a second preassembled subassembly individually
fabricated, assembled, and tested to ensure functionality,
wherein the second preassembled subassembly is coupled to the
first preassembled subassembly and comprising:
an interposer; and
a controller mounted on the interposer.
Appellants appeal the following rejections:
1. Claims 1-5, 8-13, 15, 16, and 18-20 are rejected under 35 U.S.C.
§ 112, second paragraph, as being indefinite for failing to particularly
1 In the Appeal Brief, the real party in interest is listed as "Micron
Technology Inc." (App. Br. 2).
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Application 14/258,875
point out and distinctly claim the subject matter which the applicant
regards as the invention.
2. Claims 1--4, 8-13, 15, 16, and 18-20 are rejected under 35 U.S.C.
§ I03(a) as unpatentable over the combination of Kuroda
(US 2007/0170573 Al; July 26, 2007) in view of Zohni
(US 2007/017 6297 A 1; Aug. 2, 2007).
3. Claim 5 is rejected under 35 U.S.C. § I03(a) as unpatentable over
Kuroda in view of Zohni and Lee (US 2004/0041393 Al;
Mar. 4, 2004).
FINDINGS OF FACT & ANALYSIS
35 U.S.C. § 112, ,r 2 Rejection
The Examiner's findings of fact and rejection are located on pages 6
to 8 of the Final Rejection. Specifically, the Examiner finds that the claim
language is indefinite because the plain meaning of claim 1 requires "a first
preassembled subassembly comprising: a second preassembled subassembly,
wherein the second preassembled subassembly is coupled to the first
preassembled subassembly comprising: a second preassembled subassembly,
wherein the second preassembled subassembly is coupled to the first
preassembled subassembly comprising: ... ad infinitum" (Final Act. 7).
The Examiner also finds that claim 1 requires that the first preassembled
subassembly comprises a second preassembled subassembly that is coupled
to the first preassembled subassembly, which the Examiner finds
incompatible with the later-recited claim 1 recitation of a second
preassembled subassembly individually constructed and tested (Final Act.
7). The Examiner further finds the claim language indefinite because it is
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Application 14/258,875
unclear how the second preassembled subassembly can be individually
fabricated but also part of the first preassembled subassembly (Final Act. 7).
Appellants argue that the Examiner's claim construction is
unreasonable (App. Br. 5; Reply Br. 3--4). Appellants contend that claim 1
as read in light of the Specification makes clear that the semiconductor
device is comprised of a first and second preassembled subassembly wherein
the second preassembled subassembly is coupled to the first preassembled
subassembly (Reply Br. 4 ). Appellants contend that one of ordinary skill in
the art, having read the Specification, would not interpret the claim as
requiring the first preassembled subassembly comprises the second
subassembly (Reply Br. 4 ).
Whether a claim is invalid for indefiniteness under 35 U.S.C. § 112
requires a determination of whether those skilled in the art would understand
what is claimed when the claim is read in light of the specification.
Orthokinetics Inc. v. Safety Travel Chairs, Inc., 806 F.2d 1565, 1576 (Fed.
Cir. 1986). In the present case, the Examiner has not shown that one of
ordinary skill in the art would not understand what is claimed when the
claim is read in light of the Specification. Rather, the Examiner's rejection
appears to be based upon a reading of the claim that does not account for
either the disclosure in the Specification, or the indentations, breaks and
punctuation of the claim. Claim 1 plainly recites a semiconductor device
comprising: a first preassembled subassembly ... comprising: a substrate;
and at least one semiconductor die ... ; and a second preassembled
subassembly ... wherein the second preassembled subassembly is coupled
to the first preassembled subassembly and comprising: an interposer; and a
controller mounted on the interposer. (Emphasis added). In other words,
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Application 14/258,875
claim 1 requires a semiconductor device that comprises: (1) a first
preassembled subassembly that comprises a substrate and at least one
semiconductor die, and (2) a second preassembled subassembly comprising
an interposer and a controller mounted on the interposer. The first and
second preassembled subassemblies are coupled together and compose the
semiconductor device. Our reading of the claim is supported by the
Specification that shows in Figures 2 to 4 the forming a first preassembled
subassembly 40 of memory dies 16 and 17 and forming a second
preassembled subassembly 46 of an interposer 12 and processor 18 (Spec. ,r,r
19 to 22). We do not read the claims as the Examiner proposes to include an
infinite coupling of a first and second preassembled subassemblies. We
determine that the claims are not indefinite and we reverse the Examiner's §
112, second paragraph, rejection.
35 U.S.C. § 103 Rejection
The Examiner's findings and conclusions regarding Kuroda and Zohni
are located on pages 9--18 of the Final Rejection. The Examiner relies on
Zohni to teach forming preassembled subassemblies that are tested before
assembling and mounting the subassemblies to form the final product (Final
Act. 17-18). The Examiner finds, in relevant part, that Kuroda teaches an
interposer 5 with microchip 6 attached to it (Final Act. 9). The Examiner
finds that Kuroda teaches that the memory chip 5 is an interposer because
"Kuroda discloses something [ memory chip] 5 placed between two or more
things 3, 6, or something [, memory chip] 5 placed in an intervening
(between 3 and 6) position." (Final Act. 14 ). The Examiner's finding is
based upon the definition of "interpose" from Merriam-Webster's dictionary
(Final Act. 14).
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Application 14/258,875
Appellants argue that neither Kuroda nor Zohni teaches forming a
second preassembled subassembly comprising an interposer and a controller
mounted on the interposer as recited in claim 1 (App. Br. 9--10). Appellants
contend that Kuroda's memory chip 5 is not an interposer as that term is
understood by the ordinarily skilled artisan (App. Br. 8). Appellants argue
that an interposer as understood by the ordinarily skilled artisan is an
electrical interface routing between one socket or connection to another, and
the purpose of an interposer is to spread a connection to a wider pitch or to
reroute a connection to a different connection (App. Br. 8).
We begin our analysis by construing the claim language interposer.
The Specification describes that interposer 12 allows microcontroller 18 and
capacitors 20 to be relocated and reoriented to preferred area on the stack 10
(Spec. ,r 17). The Specification describes that the interposer has bond pads
30 that allow microcontroller chip 18 to be coupled to memory chips 16 and
17 via bond wires 36 and 32 (Spec. ,r 22). The Specification does not
describe the interposer as having any functionality other than providing
electrical connections that permit the reorientation of the chips in a stack so
that various chips are connected electrically. This general description of an
interposer in the Specification comports with Kuroda's description of
interposer 7 (Kuroda ,r,r 23, 57 to 59). Specifically, Kuroda teaches that
interposer 7 has bonding pads 18 that are connected to corresponding
bonding pads 20 via wiring 22 formed in the front surface of the interposer
chip 7 (i-f 59). In other words, interposer 7 in Kuroda is formed to connect
electrically microcomputer chip 6 with wiring substrate 1 via bonding wires
W2 and W4 (Figs. 1, 2, and 4). Kuroda is intrinsic evidence as to the
ordinary meaning of interposer in the semiconductor arts. Therefore, we
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construe interposer within the meaning of claim 1 as a chip that includes
connections and conduits to connect electrically the controller and the
memory chips.
With this construction in mind, we find that the Examiner has not
shown how Kuroda's memory chip 5 constitutes an interposer. First, the
Examiner's definition of interposer is based on Merriam-Webster's
Dictionary definition of the verb "interpose" (Final Act. 14 ). Yet, that
definition fails to account for the meaning of interposer to the ordinarily
skilled artisan in the relevant art. See Phillips v. AWH Corp., 415 F.3d 1303,
1318 (Fed. Cir. 2005) ( explaining how some evidence may be "less reliable
than the patent ... in determining how to read claim terms" if it is "not
written by or for skilled artisans and therefore may not reflect the
understanding of a skilled artisan in the field of the patent.). Second,
Kuroda uses different terms to describe interposer 7 and memory chip 5, and
the Examiner has failed to show memory chip 5 functions in the same
manner as Kuroda's interposer 7. Lastly, because the Examiner has not
established that Kuroda's memory chip 5 constitutes an interposer, the
Examiner has not shown where the claim limitation that requires a controller
mounted on the interposer is taught by Kuroda and Zohni. Rather, Kuroda
teaches that microcontroller chip 6 is positioned adjacent to interposer 7 to
provide for ease of bonding (Kuroda ,r,r 50, 57, and 70). Thus, the Examiner
has not satisfied the initial requirement to establish a prima facie case of
obviousness. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992).
On this record, we reverse the Examiner's§ 103 rejection over
Kuroda and Zohni. Appellant relies on the same arguments with regard to
the § 103 rejection of dependent claim 5 over Kuroda in view of Zohni and
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Lee as were made with regard to claim 1 (App. Br. 12). The Examiner does
not rely on Lee to cure the deficiency noted above with the combination of
Kuroda and Zohni. Therefore, we reverse the Examiner's§ 103 rejection of
claim 5 over Kuroda in view of Zohni and Lee.
DECISION
The Examiner's decision is reversed.
REVERSED
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