Ex Parte Cooney et al

Patent Trial and Appeal Board

May 31, 2017

13778263 (P.T.A.B. May. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/778,263 02/27/2013 Edward C. Cooney III BUR920110044US2 9853
134359 7590
Gibb & Riley, LLC
844 West Street
Suite 200
Annapolis, MD 21401
06/02/2017 EXAMINER
ESKRIDGE, CORY W
ART UNIT PAPER NUMBER
2898
NOTIFICATION DATE DELIVERY MODE
06/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
support @ gibbiplaw .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte EDWARD C. COONEY III, JEFFREY P. GAMBINO,
ZHONG-XIANG HE, XIAO-HU LIU, THOMAS L. MCDEVITT,
GARY L. MILO, and WILLIAM J. MURPHY
Appeal 2016-003994
Application 13/778,263
Technology Center 2800
Before GEORGE C. BEST, WESLEY B. DERRICK, and
MICHAEL G. McMANUS, Administrative Patent Judges.
McMANUS, Administrative Patent Judge.
DECISION ON APPEAL
The Examiner finally rejected claims 1, 3—6, 8—11, and 13—18 of
Application 13/778,263 under 35 U.S.C. § 102(b) as anticipated. Final Act.
(March 3, 2015) 2—9. Appellants1 seek reversal of these rejections pursuant
to 35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C. § 6.
For the reasons set forth below, we AFFIRM.
1 International Business Machines Corporation is identified as the real party
in interest. Appeal Br. 3.
Appeal 2016-003994
Application 13/778,263
BACKGROUND
The present application generally relates to a method of fabricating
semiconductor devices. The application describes forming semiconductor
devices having first and second vertically stacked conductor layers separated
by an air gap. Spec. Abst.
Claim 1 is representative of the pending claims and is reproduced
below:
1. A method of fabricating a semiconductor device, said
method comprising:
forming an insulator;
forming a vertical stack of layers on said insulator, each layer of
said stack of layers being formed in a process that includes
embedding a first metal conductor and a second metal
conductor in a layer of insulation, said vertical stack of layers
comprising a plurality of first vertically stacked metal layers
and a plurality of second vertically stacked metal layers
proximate said first vertically stacked metal layers; and
etching at least one air gap in inter-stack material of said
vertical stack of layers, said at least one air gap being etched
through a vertical stack of more than one layer of said vertical
stack of layers and between said first vertically stacked metal
layers and said second vertically stacked metal layers,
said at least one air gap being positioned such that less than
10 pm of inter-stack material remains between a first side edge
of said first vertically stacked metal layers and a first side edge
of said at least one air gap and less than 10 pm of inter-stack
material remains between a second side edge of said second
vertically stacked metal layers and a second side edge of said at
least one air gap.
Appeal Br. 13 (Claims App.).
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Application 13/778,263
REJECTION
On appeal, the Examiner maintains the following rejection:
Claims 1, 3—6, 8—11, and 13—18 are rejected under 35 U.S.C. § 102(b)
as anticipated by US 7,138,329 B2, iss. Nov. 21, 2006 (hereinafter “Lur”).
Final Act. 2—9.
DISCUSSION
The Examiner rejected each of the pending claims as anticipated by
Lur. Appellants assert that such rejection is in error on several bases.
First, Appellants argue that claim 1 (and claims 6 and 11) requires
“etching at least one air gap,” while Lur teaches to form a trench by etching
that is then partially filled by a deposition process to form an air gap.
Appeal Br. 8—10. Thus, Appellants concede that Lur teaches an etching
process to remove dielectric but maintain that this does not amount to
formation of an air gap. Appeal Br. 10112. The gravamen of Appellants’
argument seems to be that an air gap is not formed until it is enclosed on all
sides.
During examination, claim terms must be given their broadest
reasonable construction consistent with the Specification. In re ICON
Health and Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007). The
Specification uses the term “air gap” several times. The Specification states,
for example, “the air gap 302 is formed by removing material down to the
lowest metal wire layer El.” Spec. 124. Thus, the Specification teaches
that the air gap is formed when etched, not when covered. According the
term its broadest reasonable construction, we construe “air gap” to include
gaps formed by etching prior to the addition of subsequent layers above the
etched portion. To the extent that Appellants argue that the claims require
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Application 13/778,263
etching of multiple levels in a single step, we do not adopt such construction.
Accordingly, Appellants have failed to show error in the Examiner’s finding
that Lur teaches to etch an air gap.
Second, Appellants argue that Lur does not teach that the air gap is
positioned less than 10pm from each of the stacked metal layers as required
by the last claim limitation of claim 1. Appeal Br. 9—10. The Examiner
determines that, upon formation of the air gap by etching, “there is
essentially no dielectric remaining between the sidewall of the trench, or ‘air
gap,’ and the metal portions, (i.e. FIG. 11) thereby meeting the claimed
limitation of less than 10 microns.” Answer 2. In the alternative, the
Examiner finds that the dielectric that enters the air gap upon deposition of a
dielectric layer (for example, by conventional plasma enhanced chemical
vapor deposition (“PECVD”)), will have the same thickness as the dielectric
layer: 0.2 to 1 microns. Final Act. 3. This finding is bolstered by the
teaching in the Specification to apply the same dielectric layer (SiCE) by the
same process (PECVD) as taught by Lur. Compare Lur 7:65—8:3 with Spec.
125 (“air-gap 302a may be ‘pinched-off by deposition of a non-conformal
dielectric, such as SiCE deposited by plasma-enhanced chemical vapor
deposition (PECVD).”).
Accordingly, Appellants have failed to show error in the Examiner’s
finding that Lur teaches an air gap positioned within 10 pm of the metal
stack layer.
Third, Appellants argue that Lur does not teach to etch the air gap
through “more than one layer of said vertical stack of layers.” Appeal Br.
10, 13 (Claims App.). In this regard, Lur teaches as follows:
In other instances a single air gap can be extended in height so
that it serves to reduce capacitance for more than one
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Application 13/778,263
interconnect layer. For example, the air gap 42 shown in the
middle of FIG. 13 serves as an air gap for two separate metal
interconnect levels; this same principle could be extended as
needed for additional levels. Thus, by appropriate “stacking”
and arrangement of interconnect layers, a single air gap can be
formed between adjacently located conductive lines in more than
one layer of metal.
Lur 9:32—41.
In view of the foregoing, Appellants have failed to show error in the
Examiner’s finding that Lur teaches an air gap that extends through a
plurality of layers.
Appellants additionally submit arguments in support of the
patentability of dependent claims 3 and 8,2 each of which require a second
air gap, and claims 16—18, each of which require a second air gap that is in
“vertical alignment” with the first air gap. Appellants argue that Lur does
not teach “a portion of said inter-stack material between said at least one air
gap and said second air gap” as required by claims 3 and 8. This argument
fails in view of Lur’s Figure 34 which depicts air gap 88 above air gap 68
and the related teaching that air gap 68 is “shown embedded in dielectric
layer 14.” Lur 12:33.
With regard to claims 16—18, Appellants argue that “[sjince Lur does
not etch the air gaps, it is impossible for Lur to create multiple air gaps
aligned vertically, as claimed.” Appeal Br. 11. For the reasons set forth
above in regard to claim 1, we have determined that Appellants have failed
to show error in the Examiner’s finding that Lur teaches to etch air gaps.
2 Appellants argue that claim 11 also requires a second air gap. Appeal Br.
10. Claim 11, however, requires only “at least one air gap.” Id. at 16—17
(Claims App.).
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Application 13/778,263
Accordingly, Appellants have failed to show error in the Examiner’s
determination regarding claims 16—18 for the same reasons.
Any argument not addressed herein fails to meet the requirements of
37 CFR § 41.37(c)(l)(iv) and is therefore refused consideration.
CONCLUSION
The rejection of claims 1, 3—6, 8—11, and 13—18 as anticipated is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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