Ex Parte Colglazier

Patent Trial and Appeal Board

Mar 27, 2017

13672896 (P.T.A.B. Mar. 27, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/672,896 11/09/2012 Daniel J. Colglazier RPS920120073US1 (157) 8397
50594 7590
CRGO LAW
STEVEN M. GREENBERG
7900 Glades Road
SUITE 520
BOCA RATON, EL 33487
03/29/2017 EXAMINER
AHMED, ZUBAIR
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
03/29/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@crgolaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte INTERNATIONAL BUSINESS MACHINES CORP.1
Appeal 2017-001149
Application 13/672,896
Technology Center 2100
Before BRADLEY W. BAUMEISTER, JOHN F. HORVATH, and
MICHAEL J. ENGLE, Administrative Patent Judges.
BAUMEISTER, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejections of claims 6—15. App. Br. 5—17.2 We have jurisdiction under
35 U.S.C. § 6(b). We affirm.
1 Daniel J. Colglazier is named as Inventor.
2 Rather than repeat the Examiner’s positions and Appellant’s arguments in
their entirety, we refer to the following documents for their respective
details: the Non-Final Office Action mailed November 12, 2015 (“Non-
Final Act.”); the Appeal Brief filed April 11, 2016 (“App. Br.”); the
Examiner’s Answer mailed August 16, 2016 (“Ans.”); and the Reply Brief
filed October 17, 2016 (“Reply Br.”).
Appeal 2017-001149
Application 13/672,896
STATEMENT OF THE CASE
Appellant describes the present invention as follows:
Embodiments of the present invention provide a method,
system and computer program product for enhanced cache
coordination in a multi-level cache. In an embodiment of the
invention, a method for enhanced cache coordination in a multi­
level cache is provided. The method includes receiving a
processor memory request to access data in a multi-level cache
and servicing the processor memory request with data in either
an LI cache or an L2 cache of the multi-level cache. The method
additionally includes marking a cache line in the LI cache and
also a corresponding cache line in the L2 cache as most recently
used responsive to determining that the processor memory
request is serviced from the cache line in the LI cache and that
the cache line in the LI cache is not currently marked most
recently used.
Abstract.
Claims 6 and 11 stand rejected under 35 U.S.C. § 103(a) as obvious
over Jaleel (US 2012/0159073 Al; published June 21, 2012) in view of
Azevedo (US 2003/0221072 Al; published Nov. 27, 2003). Non-Final Act.
10.
Claims 7, 9, 12, and 14 stand rejected under 35 U.S.C. § 103(a) as
obvious over Jaleel in view of Azevedo, Balakrishnan
(US 2010/0191916 Al; published July 29, 2010), Sendag (US 7,721,048 Bl;
issued May 18, 2010), and Walker (US 2013/0311724 Al; published
Nov. 21, 2013). Non-Final Act. 13.
Claims 8 and 13 stand rejected under 35 U.S.C. § 103(a) as obvious
over Jaleel in view of Azevedo and Pong (US 2007/0239938 Al; published
Oct. 11,2007) Non-Final Act. 17.
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Application 13/672,896
Claims 10 and 15 stand rejected under 35 U.S.C. § 103(a) as obvious
over Jaleel in view of Azevedo, Balakrishnan, Sendag, Walker, and Pong.
Non-Final Act. 19.
We review the appealed rejections for error based upon the issues
identified by Appellant, and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential).
CLAIMS 6, 8, 11, AND 13
The Rejected Claims
Independent claim 6, reproduced below, is illustrative of appealed
claims 6 and 11:
6. A data processing system configured for enhanced cache
coordination in a multi-level cache, the system comprising:
a processor coupled to main memory over a bus;
a multi-level cache accessible to the processor and
comprising an LI cache and an L2 cache;
a cache controller managing access to the multi-level
cache; and,
an enhanced cache coordination module coupled to the
cache controller and comprising program code enabled to mark
a cache line in the LI cache and also a corresponding cache line
in the L2 cache as most recently used responsive to determining
that the processor memory request is serviced by the cache
controller from the cache line in the LI cache and that the cache
line in the LI cache is not currently marked most recently used.
Findings and Contentions
The Examiner finds that Jaleel discloses every limitation of
independent claim 1 other than program code enabled to mark a cache line
and an enhanced cache coordination module coupled to the cache controller.
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Application 13/672,896
Non-Final Act. 12. The Examiner further finds, though, that Azevedo
teaches these missing limitations and that motivation existed to modify
Jaleel so as to incorporate these features. Id.
Of relevance, the Examiner finds that Jaleel’s Temporal-Locality-
Hints (TLH) caching protocol teaches to
[m]ark a cache line in the LI cache and also a corresponding
cache line in the L2 cache as most recently used responsive to
determining that the processor memory request is serviced by the
cache controller from the cache line in the LI cache and that the
cache line in the LI cache is not currently marked most recently
used.
Id. at 11 (citing Jaleel 143; FIG. 3); Ans. 2—6 (citing Jaleel Tflf 34, 43;
FIG. 3).
The Examiner explains that while Jaleel does not expressly state that
the cache marking step is responsive to determining that the cache line in the
LI cache is not currently marked most recently used, as claimed, Jaleel
inherently makes this determination. Non-Final Act. 11. The Examiner
explains
a decision to promote the cache line to the MRU [Most Recently
Used] position is only viable when the cache line is NOT marked
as MRU. Otherwise, if the cache line is already marked as MRU
then no action is taken in Jaleel as well as in the instant invention.
Accordingly, there is a determination that the cache line is not
marked MRU and only then promote the cache line to the MRU
position if the processor request is serviced by the LI cache.
Ans. 4—5.
Appellant does not dispute that Jaleel marks a cache line in both the
LI and L2 caches as MRU in response to determining that the request is
serviced from the cache line in the LI cache. App. Br. 5—13. Appellant only
argues that Jaleel does not disclose performing the marking in response to
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Application 13/672,896
determining that the cache line in the LI cache is not currently marked MRU
{id.) and such a determination is not inherent to Jaleel’s disclosure (id. at 12—
13).
Appellant further draws attention to the well-settled legal principle
that “[t]he mere fact that a certain thing may result from a given set of
circumstances is not sufficient” to prove inherency (App. Br. 10) (emphasis
omitted) (citation omitted), and that the inherency doctrine requires an
inherent characteristic necessarily flow from the teachings (id. at 10—11).
Appellant contends that the “Examiner presents only a single, conclusory
sentence which is mere conjecture or argumentation absent factual support.”
Id. at 13. Appellant urges that “a review of Figure 3, column b of Jaleel
reveals an absence of any suggestion of any determination as to whether or
not the memory request is serviced from a line in LI and that the line in LI
is NOT currently marked MRU.” Id.
Analysis
We disagree with Appellant’s contention that the Examiner’s
conclusion regarding Jaleel inherently teaching marking a cache line as
MRU upon determining the cache line is not currently marked as MRU is
only conclusory or constitutes mere conjecture absent factual support.
Contrary to Appellant’s argument that the “Examiner has elected not to
provide any evidence” (Reply Br. 5; App. Br. 10—13), the Examiner supports
the conclusion of inherency by first discussing what Jaleel expressly teaches
(Ans. 3^4 (citing Jaleel Fig. 3, 34, 43)) and then explaining the following
factual reasoning based on those teachings:
a decision to promote the cache line to the MRU [Most Recently
Used] position is only viable when the cache line is NOT marked
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Application 13/672,896
as MRU. Otherwise, if the cache line is already marked as MRU
then no action is taken in Jaleel as well as in the instant invention.
Ans. 4; see also id. at 5—6.
Jaleel expressly supports this finding. Jaleel states that “the LI cache
can issue TLHs for non-MRU lines.” Jaleel 144. Restated, TLH protocol
entails updating the L2 cache only in those circumstances when the
requested LI line is not marked as most recently used.
Accordingly, Appellant has not persuaded us of error in the
Examiner’s obviousness rejection of independent claim 6. We, therefore,
sustain the Examiner’s rejection of that claim, as well as claim 11, which is
not separately argued. See App. Br. 5—13.
With respect to the rejection of dependent claims 8 and 13, Appellant
provides no patentability arguments directed to the additionally cited
reference, Pongo. App. Br. 16—17. Rather, Appellant argues for the
patentability of claims 8 and 13 based upon their dependency from claim 1.
Id. For the reasons discussed above, then, we likewise sustain the rejection
of these claims.
CLAIMS 7, 9, 10, 12, 14, AND 15
The Rejected Claims
Claim 7, reproduced below, is illustrative of appealed claims 7, 9, 10,
12, 14, andl5:3
7. The system of claim 6, wherein the program code is further
enabled to determine that the cache controller has serviced the
request with a cache line from the L2 cache, to replace an existing
3 The body of the Non-Final Action focuses on claim 7 (Non-Final Act. 13—
17), whereas Appellant’s briefs focus on claim 9 (App. Br. 13—16; Reply
Br. 6—7), but the claims are commensurate in scope.
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cache line in the LI cache with the cache line from the L2 cache,
to send an address of the replaced cache line to the L2 cache and
to mark a corresponding cache line in the L2 cache as least
recently used responsive to determining that the processor
memory request is serviced from a cache line in the L2 cache
rather than the LI cache and that the replaced cache line in the
LI cache does not exist in any other LI cache of the multi-level
cache.[4]
Findings and Contentions
The Examiner relies on the combination of Jaleel and Azevedo for
teaching the limitations of claim 6. Non-Final Act. 13. The Examiner finds
that Balakrishnan teaches a method for enhanced cache coordination in a
multi-level cache that comprises receiving a processor memory request to
access data in a multi-level cache, servicing the processor memory request
with data in a cache line of an L2 cache of the multi-level cache, and
replacing an existing cache line in an LI cache of the multi-level cache with
the cache line from the L2 cache, as recited in claim 7. Id. at 13—14. The
Examiner finds that “Sendag teaches ‘to send an address of the replaced
cache line to the L2 cache and to mark a corresponding cache line in the L2
cache as least recently used,’” as recited in claim 7. Id. at 15. The Examiner
finds that “Walker teaches ‘responsive to determining that the replaced
cache line in the LI cache does not exist in any other LI cache of the multi­
level cache[s],’ . . . L2 cache replaces the cache line with a new cache line.”
Id. at 16 (citing Walker 127). The Examiner further finds that sufficient
4 In the event of further prosecution, the Examiner may wish to consider
whether the Specification reasonably explains how to make and use the
invention in a manner that entails “sending an address of the replaced cache
line to the L2 cache,” as claimed, as opposed to sending the cache line,
itself. Emphasis added; see also App. Br. 3 (citing only Spec. 117 as
written description support).
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motivation existed to combine the teachings of Jaleel, Azevedo,
Balakrishnan, Sendag, and Walker. Id. at 12—16.
Appellant contends that Walker fails to “determin[e] that the replaced
cache line in the LI cache does not exist in any other LI cache of the multi­
level cache,” as recited in the last limitation of claim 7. App. Br. 15—16. In
Appellant’s view, “Walker provides for the replacement of a cache line with
a new cache line in response to a determination of whether or not a cache
line is present in only one of the higher level caches.” App. Br. 16
(emphasis added).
Analysis
Walker’s abstract reads as follows:
A cache system includes plurality of first caches at a first level
of a cache hierarchy and a second cache at a second level of the
cache hierarchy which is lower than the first level of cache
hierarchy coupled to each of the plurality of first caches. The
second cache enforces a cache line replacement policy in which
the second cache selects a cache line for replacement based in
part on whether the cache line is present in any of the plurality
of first caches and in part on another factor.
Abstract (emphasis added).
Walker also states in relation to the disputed step 306, “if the cache
line is present in any of the higher level, LI, caches then method 300
proceeds to 308, else method 300 proceeds to 310 and the L2 cache replaces
the cache line with a new cache line.” Walker 127 (emphasis added).
These passages support the Examiner’s finding that Walker
determines if the requested cache line is present in any of the higher level
caches of the multi-level cache and replaces the cache line only when the
cache line is not present in any of the LI caches.
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Accordingly, Appellant has not persuaded us of error in the
Examiner’s obviousness rejection of independent claim 7. We, therefore,
sustain the Examiner’s rejection of that claim, as well as claims 9, 12, and
14, which are not argued separately. See 37 C.F.R. § 41.37(c)(l)(iv).
With respect to the remaining rejection of claims 10 and 15, Appellant
provides no patentability arguments directed to the additional reference
Pongo. Rather, Appellant argues the patentability of these claims based
upon their dependency from claims 9 and 14. App. Br. 17. For the reasons
discussed above, then, we likewise sustain the rejections of these claims.
DECISION
The Examiner’s decision rejecting claims 6—15 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 1.136(a)(l)(iv).
AFFIRMED
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