Ex Parte Clauberg

Patent Trial and Appeal BoardOct 31, 2012

10123797 (P.T.A.B. Oct. 31, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/123,797 04/12/2002 Rolf Clauberg CH919990029US1 9070 7590 10/31/2012 IBM CORPORATION Intellectual Property Law T.J. WATSON RES. CENTER P.O. BOX 218 YORKTOWN HGTS, NY 10598 EXAMINER LEVITAN, DMITRY ART UNIT PAPER NUMBER 2461 MAIL DATE DELIVERY MODE 10/31/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte ROLF CLAUBERG ____________ Appeal 2010-000296 Application 10/123,797 Technology Center 2400 ____________ Before CARL W. WHITEHEAD, JR., ERIC S. FRAHM and ANDREW J. DILLON, Administrative Patent Judges. WHITEHEAD, JR., Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-000296 Application 10/123,797 2 STATEMENT OF THE CASE Appellant is appealing claims 1-5, 7-18, and 21-23. Appeal Brief 2. We have jurisdiction under 35 U.S.C. § 6(b) (2002). We affirm. Introduction The invention is directed to “a method and device for creating an aligned outgoing data stream of a predetermined width and clock rate from an unaligned data stream.” Appeal Brief 3. Illustrative Claims 1. A device for creating an aligned outgoing data stream of a predetermined width and an output clock rate from an unaligned incoming data stream having a width comprising a lower number of bits an input clock rate, the device comprising: a composing unit for converting the incoming data stream into a data stream of a higher width in number of bits than the incoming data stream and lower clock rate than the input clock rate and for providing the data stream of higher width for storage at a storage unit; a storage unit comprising a single shift register for storing a number of bits comprising at least two times the number of bits in the width of the outgoing data stream, wherein the storage unit further comprises an align position detection unit for monitoring the bits in the single shift register for locating a particular bit position indicative of an align position and for generating a bit location signal indicating the location of the particular bit position, an output port for outputting the outgoing data stream at the lower clock rate, and an extracting unit for receiving the bit location signal and for extracting from said single shift register to said output port the same number of bits as the number of bits in the width of the outgoing data stream starting from the located align position. Appeal 2010-000296 Application 10/123,797 3 3. The device according to claim 1, wherein the unaligned incoming data stream has a width of 16-bits, said composing unit converts the incoming stream to an outgoing data stream of 64-bit width and said shift register provides storage space for 196 bits of data comprising three times the number of bits in the width of the outgoing data stream. Rejections on Appeal Claims 3 and 14 stand rejected under 35 U.S.C. § 112, first paragraph, as being indefinite for failing to comply with the written description requirement. Answer 3. Claims 1-5, 7-18, and 21-22 stand rejected under 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which Appellant regards as the invention. Answer 4. Claims 1-5, 7, 8, 11-18, and 21-23 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Stephenson (U.S. Patent Number 5,081,654; issued January 14, 1992). Answer 4-9. Claims 9 and 10 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Stephenson and Appellant’s Admitted Prior Art. Answer 9-10. Issue on Appeal Does Stevenson disclose an apparatus and method that “allows greater processing capability with far fewer circuits” as demarcated within the claims? Appeal 2010-000296 Application 10/123,797 4 ANALYSIS 35 U.S.C. § 112, first paragraph rejection Appellant argues that the Amendment After Final would have corrected the typographical errors within claim 3 and 14 if the Examiner would have entered the amendment instead of concluding that the amendments “are not deemed to place the application in better form by materially reducing or simplifying the issues for appeal” and thus refusing to enter the amendment. Appeal Brief 9-10. Appellant requests that the Board enter the amendments to claims 3 and 14 to overcome the 35 U.S.C. § 112. Id. at 10. Inasmuch as Appellant’s request that the amendments to the claims be entered, this is not an issue before us because the request relates to a petitionable issue and not an appealable issue. See In re Schneider, 481 F.2d 1350, 1356-57, (CCPA 1973) and In re Mindick, 371 F.2d 892, 894, (CCPA 1967). See also Manual of Patent Examining Procedure (MPEP) (8th Ed., August 2001) § 1002.02(c), item 3(g) and § 1201. Thus, the relief sought by Appellant would have been properly presented by a petition to the Director under 37 C.F.R. § 1.181 instead of by appeal to this Board. Accordingly, we sustain the Examiner’s rejection of claims 3 and 14 under 35 U.S.C. § 112, first paragraph. 35 U.S.C. § 112, second paragraph rejection Appellant argues that the Amendment After Final would have corrected the inadvertent omission from the claims, which is clearly supported by the Specification if only the Examiner would have entered the Appeal 2010-000296 Application 10/123,797 5 amendment. Appeal Brief 10-11. Appellant requests that the Board enter the amendment to claim 1 to overcome the 35 U.S.C. § 112. Id. at 11. As we stated above, Appellant’s request that the amendments to the claims be entered, this is not an issue before us because the request relates to a petitionable issue and not an appealable issue. See In re Schneider, 481 F.2d 1350, 1356-57, (CCPA 1973) and In re Mindick, 371 F.2d 892, 894, (CCPA 1967). See also Manual of Patent Examining Procedure (MPEP) (8th Ed., August 2001) § 1002.02(c), item 3(g) and § 1201. Thus, the relief sought by Appellant would have been properly presented by a petition to the Director under 37 C.F.R. § 1.181 instead of by appeal to this Board. Accordingly, we sustain the Examiner’s rejection of claims 1-5 and 7-11 under 35 U.S.C. § 112, second paragraph. Appellant argues that claim 12 is not “unclear as written” as the Examiner finds. Appeal Brief 12. Appellant contends that claim 12 was amended by the amendment submitted on September 21, 2007 and the amended language is supported by the Specification on page 9, lines 23-26. Id. However, we do not find support for the amendment on page 9 of the Specification because there appear to be only 7 lines on the page. In lieu of Examiner’s comments and Appellant’s lack of support, we agree with the Examiner and find that claim 12 is unclear because of the unambiguity between the terminology “a number of bits” and “a different lower number of bits.” Accordingly we sustain the Examiner’s rejection of claims 12-18, 21 and 22 under 35 U.S.C. § 112, second paragraph. Appeal 2010-000296 Application 10/123,797 6 35 U.S.C. § 103 rejection We have reviewed the Examiner’s rejections in light of Appellant’s arguments that the Examiner has erred. We disagree with Appellant’s conclusions. We concur with the findings and reasons set forth by the Examiner in the action from which this appeal is taken and the reasons set forth by the Examiner in the Answer in response to Appellant’s Appeal Brief. However, we highlight and address specific findings and arguments for emphasis as follows. Appellant argues that because Stephenson requires that the serial-to- parallel converter uses an input clock rate and parallel data be provided to multiple shift registers in conjunction with multiple detectors employed; Stephenson cannot obviate the claimed invention because the claimed invention allows greater processing capability with far fewer circuits. Appeal Brief 14. Appellant further argues that the claimed invention provides “an inventive circuitry that allows a single shift register and a single align position detection unit to output an aligned outgoing data stream of a predetermined width and clock rate form an unaligned incoming data stream.” Id. at 14-15. Appellant concludes: Stephenson does not teach or suggest using a single shift register. Rather, Stephenson uses a series of latches, none of which can store two or more times the number of bits in the bit stream. Further, Stephenson does not teach a single align position detection unit associated with a single shift register. Rather, Stephenson teaches a plurality of detectors associated with different latches. Further, Appeal 2010-000296 Application 10/123,797 7 Stephenson does not teach that a detector generates a bit location signal for an extracting unit to extract the output stream from the single shift register starting with the detected alignment bit. Appeal Brief 15. However, the Examiner finds: The system of Stephenson performs the same operation as the claimed invention with minor difference, as explained in the claims rejection above, and provides more in-depth disclosure, including detailed schematic, in comparison with the Application. Therefore, lack of description of in- depth operation of the application should not be interpreted as a "single" or better solution, as the disclosure of the application is simply limited to a block diagram. In addition, Stephenson teaching of multiple latches does not contradict (teaches away) claims limitations directed to a single register, as a single register comprises multiple latches, as shown above. A single register can comprise multiple parallel registers, as in cited portion of Stephenson teaching, directed to parallel shift registers 6:19-21. Latches 28 on Fig. 3 and 4 are examples of parallel devices connected in a single shift register. Answer 12. We do not find Appellant’s arguments to be persuasive. Appellant does not point to specific portions of their Specification that would lead one of ordinary skill in the art to conclude that the invention as claimed is novel. Appellant’s argument pertaining to the fabrication of semiconductor devices to save or conserve “real estate” on a semiconductor chip is not persuasive because the invention allegedly reduces the number of circuits and therefore has nothing to do with a novel approach to semiconductor Appeal 2010-000296 Application 10/123,797 8 fabrication but merely points out that with fewer circuits to fabricate, less chip real estate needed. See Appeal Brief 15. The novelty of the invention appears to be the “creat[ion] an aligned outgoing data stream of a predetermined width and clock rate from an unaligned outgoing data stream.” Specification 4. Appellant’s arguments that the novelty of the claims is the reduction of circuitry are contradicted by what is actually disclosed within the Specification. Id. at 6. Further, from what we can gleam from the claims; we find that Stephenson performs the same operation as the claimed invention and that the noted differences are merely obvious variations that are not considered to patentably distinguish the claimed invention over the cited art. See Answer 6, 8. Also, the merely integration of separate parts are not considered to be a novel endeavor. See In re Larson, 340 F.2d 965, 968 (CCPA 1965). Therefore we do not find Appellant’s arguments to be persuasive and we sustain the Examiner’s rejection of independent claim 1, as well as, independent claims 12 and 23 not separately argued. We also sustain the Examiner’s rejection of dependent claims 2-5, 7-11, 13-18, 21, and 22 not separately argued. DECISION The rejection of claims 1-5, 7-18, and 21-23 is affirmed. Appeal 2010-000296 Application 10/123,797 9 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R. § 41.50(f). AFFIRMED pgc