Ex Parte Clancy et al

Patent Trial and Appeal Board

May 23, 2018

13451010 (P.T.A.B. May. 23, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/451,010 04/19/2012
12371 7590 05/25/2018
Muncy, Geissler, Olds & Lowe, P.C./QUALCOMM
4000 Legato Road, Suite 310
Fairfax, VA 22033
Robert D. Clancy
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
QC113024 8578
EXAMINER
PARK,ILWOO
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
05/25/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
meo.docket@mg-ip.com
meo@mg-ip.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ROBERT D. CLANCY, THOMAS PHILIP SPEIER,
and JAMES NORRIS DIEFFENDERFER
Appeal2017-008690
Application 13/451,010 1
Technology Center 2100
Before JASON V. MORGAN, BARBARA A. BENOIT, and
MICHAEL J. ENGLE, Administrative Patent Judges.
ENGLE, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 2-7 and 9-27, which are all of the claims pending in the application.
We have jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE.
Technology
The application relates to "power management of a microprocessor"
by "preventing the displacement of high temporal locality of reference data
fill buffers." Spec. i-f 2.
1 Appellants state the real party in interest is QUALCOMM Inc. App. Br. 3.
Appeal2017-008690
Application 13/451,010
Illustrative Claims
Claim 9 (a processor) and claim 2 (a method) are illustrative and
reproduced below with certain limitations at issue emphasized:
9. A processor, comprising:
a memory structure comprising a data buffer and a cache,
wherein the processor is configured to:
store memory content in the data buffer, the data
buffer coupled to the cache so that data may be written
from the data buff er to the cache and from the cache to the
data buff er;
initialize a counter associated with the memory
content in the data buffer;
increment the counter when the memory content in
the data buffer is accessed within a predetermined number
of clock cycles;
decrement the counter when the memory content in
the data buff er is not accessed within the predetermined
number of clock cycles;
determine that the memory content of the data
buffer has a high temporal locality of reference when the
counter is above a threshold; and
access the data buffer, instead of the cache, for each
operation targeting the memory content when the counter
is above the threshold.
2. A method of accessing memory content with a high temporal
locality of reference, comprising:
storing the memory content in a data buffer of a processor,
the data buffer coupled to a cache of the processor so that data
may be written from the data buffer to the cache and from the
cache to the data buffer;
initializing a counter associated with the data buffer;
incrementing the counter when the memory content in the
data buffer is accessed within a predetermined number of clock
cycles;
2
Appeal2017-008690
Application 13/451,010
decrementing the counter when the memory content in the
data buffer is not accessed within the predetermined number of
clock cycles;
determining that the memory content of the data buffer has
the high temporal locality of reference when the counter is above
a threshold; and
accessing the data buffer, instead of the cache, for each
operation targeting the memory content when the counter is
above the threshold.
Rejections
Claims 2, 3, 9, 10, 15-17, and 23-25 stand rejected under 35 U.S.C.
§ 103(a) as obvious over the combination of Worthington et al.
(US 2011/02710170 Al; Nov. 3, 2011), Banerjee et al. (US 8,386,717 Bl;
Feb. 26, 2013), and Wallner et al. (US 2007 /0247929 Al; Oct. 25, 2007).
Final Act. 3-8.
Claims 4--7, 11-14, and 18-22 stand rejected under 35 U.S.C.
§ 103(a) as obvious over the combination of Worthington and Dan et al.,
Use of Secondary Address Stack and Multiple Insertion Points for Database
Buffer Management under Least Recently Used Policy, IBM Technical
Disclosure Bulletin, Vol. 36, No. 07, Pages 431-32 (July 1993). Final Act.
8-13.
Claims 26 and 27 stand rejected under 35 U.S.C. § 103(a) as obvious
over the combination of Worthington, Banerjee, Wallner, and Wu et al.
(US 2016/0116965 Al; Apr. 28, 2016). Final Act. 13-15.
ISSUE
Did the Examiner err in finding Worthington teaches or suggests a
"processor, comprising ... a cache" (in claims 9, 11, 15, and 22) or "a cache
of the processor" (in claims 2, 4, 16, and 18)?
3
Appeal2017-008690
Application 13/451,010
ANALYSIS
Independent claims 9, 11, 15, and 22 recite "[a] processor, comprising
... a cache." Independent claims 2, 4, 16, and 18 similarly recite "a cache
of the processor."
The Examiner finds "Worthington teaches the cache of the processor
[e.g., 'memory regions with infrequently used memory pages consolidated'
in paragraph 0047]." Ans. 17 (brackets in original). According to the
Examiner, Worthington's "'memory regions with infrequently used memory
pages' ... is used by the ... PROCESSOR 108 .... Thus, Worthington
teaches a cache of a processor." Id. at 16-17 (emphasis added).
We agree with Appellants, however, that "[t]he mere fact that
Worthington's processor 108 may write data to ... memory regions 110-116
of FIG. 1 does not necessarily mean that memory regions 110-116 are in fact
a 'cache of a processor', and interpreting them as such would be
unreasonably broad." Reply Br. 5---6. As Appellants correctly point out,
Figure 1 of Worthington depicts memory groups 110-116 as separate
hardware components from processor 108. App. Br. 11.
The Examiner does not show how Worthington teaches or suggests a
"processor, comprises ... a cache" (for claim 9, 11, 15, and 22), rather than
a processor that uses an external cache. Similarly, for claims 2, 4, 16, and
18, Worthington may teach a cache of device 102 (which includes both
processor 108 and memory groups 110-116), but not a cache of processor
108. We agree with Appellants that the claimed "cache of a processor" is a
"component[] of the processor, itself," Reply Br. 5, such as the instruction
cache 26 or data cache 30 inside processor 10 in Figure 2 of the
Specification. Spec. i-fi-1 21, 23; see also id. i1 29, Fig. 3 (depicting L 1 cache).
4
Appeal2017-008690
Application 13/451,010
Accordingly, we do not sustain the Examiner's rejection of
independent claims 2, 4, 9, 11, 15, 16, 18, and 22, and their dependent
claims 3, 5-7, 10, 12-14, 17, 19-21, and 23-27.
DECISION
For the reasons above, we reverse the Examiner's decision rejecting
claims 2-7 and 9-27.
REVERSED
5