Ex Parte Chinnakonda

Patent Trial and Appeal Board

Nov 15, 2012

11214501 (P.T.A.B. Nov. 15, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte MURALIDHARAN S. CHINNAKONDA
____________________

Appeal 2010-005612
Application 11/214,501
Technology Center 2100
____________________

Before JEAN R. HOMERE, ST. JOHN COURTENAY III, and
GREGORY J. GONSALVES, Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134 from a rejection of claims
1-5, 7, 8, 10-13, and 15-22. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.

The claims are directed to store buffer forwarding in a pipelined
computer processing system. Claim 1, reproduced below, is illustrative of
the claimed subject matter:
1. A system, comprising:

a processor coupled to an address bus;

a cache memory that couples to the address bus and
comprises cache data, the cache memory divided into a plurality
of ways; and

a store buffer that couples to the address bus, and
comprises store buffer data, a store buffer way and a store
buffer index,

wherein,

the processor selects the store buffer data for use by a
data load operation if both (i) a selected way of the plurality of
ways matches the store buffer way and (ii) at least part of a
virtual address on the address bus matches the store buffer
index; otherwise, when the selected way matches the store
buffer way, the processor selects the cache data corresponding
to the selected way, and

when the selected way does not match the store buffer
way, the processor ends a store buffer access;

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a hashed address generator that couples to the address
bus and converts the virtual address present on the address bus
into a current hashed address; and

a hash memory that couples to the address bus and
comprises a saved hashed address associated with the cache
data;

wherein the current hashed address is compared to the saved
hashed address; and

wherein the result of the comparison of the hashed addresses is
a current way value indicative of the selected way.

(disputed limitations emphasized).

REFERENCES
The prior art relied upon by the Examiner as evidence in rejecting the
claims on appeal is:
Gruner US 4,048,623 Sept. 13, 1977
Razdan US 6,253,285 B1 Jun. 26, 2001
Hughes US 6,662,280 B1 Dec. 09, 2003

REJECTION

Claims 1-5, 7, 8, 10-13, and 15-22 stand rejected under 35 U.S.C.
§103(a) as being unpatentable over the combination of Razdan, Hughes, and
Gruner.
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GROUPING OF CLAIMS
In light of Appellant’s arguments, we will decide the appeal of the
obviousness rejection of claims 1-5, 7, 8, 10-13, 15, 21, and 22 on the basis
of claim 1. See 37 C.F.R. § 41.37(c)(1)(iv). We will similarly decide the
appeal of the obviousness rejection of independent claim 16 and associated
dependent claims 17-20 on the basis of claim 16. (Id.).
Contentions
Appellant contends:
Independent claim 1 recites, in part, “the processor
selects the store buffer data for use by a data load operation if
both (i) a selected way of the plurality of ways matches the
store buffer way ... wherein the result of the comparison of the
hashed addresses is a current way value indicative of the
selected way.” Independent claim 10 recites similar limitations.
However, Examiner erred in rejecting the claims because the
cited references fail to teach or suggest the quoted limitations.
On page 7 of the Final Office Action, Examiner cites Hughes at
col.2 l.36-44 as allegedly teaching the quoted limitation. At the
cited location, Hughes states “[i]n set associative embodiments,
the way in which the load hits is compared to the way in which
the store hits to further verify the correctness of the
forwarding.” However, an independent way determination fails
to teach or suggest the result of hashed address comparison
being the way value.
(App. Br. 12-13).

The Examiner disagrees. In particular, the Examiner responds that
“Applicant has not argued against Razdan in view of Hughes, instead
preferring to attack Hughes singly.” (Ans. 9). The Examiner further
responds:
The Appellant’s statement to the effect of “[h]owever, an
independent way determination fails to teach or suggest the
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result of hashed address comparison being the way value” (pg
13) does not appear reflective of positively recited claim
requirements. The claimed phrasing “wherein the result of the
comparison of the hashed addresses is a current way value
indicative of the selected way” does not positively require that
the comparison generate the way; it merely requires that the
comparison generate a value that is indicative of the way, which
can be interpreted as being fulfilled by Hughes disclosure of
recalling the forwarding if the way determination misses, in that
the recall signal is a value indicative of the way being incorrect.
(Ans. 9-10, underline added).

Issue
Under § 103, did the Examiner err in finding that the cited references,
either alone or in combination, would have taught or suggested “the
processor selects the store buffer data for use by a data load operation if both
(i) a selected way of the plurality of ways matches the store buffer way . . .
wherein the result of the comparison of the hashed addresses is a current
way value indicative of the selected way,” within the meaning of claim 1 and
the commensurate language of claim 10? (emphasis added).

ANALYSIS

Regarding the disputed hashed address limitation, we agree with the
Examiner (Ans. 9) that Appellant is attacking the Hughes reference in
isolation, while ignoring the teachings and suggestions of Razdan, as relied
on by the Examiner in combination with Hughes (and Gruner), as follows:1
Razdan discloses using a hash of a portion of the load address
and an un-hashed portion of the address to determine if a load

1 One cannot show nonobviousness by attacking references individually
where the rejections are based on combinations of references. In re Merck
& Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
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hits in the cache (figure 6), while Hughes accepts the address
and way of a load address in determining whether a load hits in
the store queue (figure 1). At the time of the invention, it would
have been obvious to a person having ordinary skill in the art to
modify Razdan to buffer the store operations, as taught by
Hughes, and to operate the store queue given the hashed
address and un-hashed address already calculated by Razdan.
The motivation for doing so would have been that it allows the
processor to store writes that are still speculative and to flush
those writes when they turn out to be non-coherent (Hughes,
column 1 lines 14-42). Therefore, it would have been obvious
to modify Razdan to use Hughes store buffer for the benefit of
flushing speculative writes that turn out to be non-coherent.
(Ans. 4-5).

We also observe that Appellant does not further rebut the Examiner’s
responsive arguments (Ans. 9-10) and broader claim construction (id.) by
filing a Reply Brief. Therefore, on this record we are not persuaded of
Examiner error regarding the rejection of representative claim 1.
Accordingly, we affirm the Examiner’s rejection of claim 1 and of claims 2-
5, 7, 8, 10-13, 15, 21, and 22 (not argued separately) which fall therewith.
See 37 C.F.R. § 41.37(c)(1)(iv).

Claims 16-20
Appellant contends that claims 16-20 are allowable for the same
reasons discussed above regarding claim 1 which we did not find to be
persuasive. (App. Br. 13-14). However, Appellant additionally contends
that the Examiner has erred regarding claims 16-20 in view of the claimed
virtual address:
Additionally, independent claim 16 recites, in part, “a
virtual address.” However, Examiner erred in rejecting the
claims because the cited references fail to teach or suggest the
quoted limitation. On page 9 of the Final Office Action,
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Examiner cites Gruner at col.5 l.25-21 as allegedly teaching the
quoted limitation. At the cited location, Gruner teaches an
interleaved memory system in which words that are normally
expected to be used sequentially are stored in different memory
modules. However, storing words in different memory modules
fails to teach or suggest a virtual address. For at least these
reasons, Examiner erred in rejecting independent claim 16,
along with dependent claims 17-20, because the claims are
allowable over Razdan in view of Hughes in even further view
of Gruner.
(App. Br. 14).

The Examiner disagrees:

Applicant has failed to provide any reasoned rationale as to why
storing words in different memory modules fails to teach or
suggest a virtual address. Gruner’s storing of words in different
memory modules means that the inputted addresses are mapped
to different modules, that there is a conversion between the
inputted address and the address the actual memory modules
see. The Examiner asserts that this can clearly be seen as
disclosing a virtual address.
(Ans. 11-12).

We reproduce the pertinent portions of Gruner below:

Further, the memory system may be arranged to be used
in an interleaving process. In non-interleaved memory systems,
groups of memory words (e.g., instruction words) which are
normally used in sequence are often stored in the same memory
module. Accordingly, such sequentially used words cannot be
made available simultaneously since access to only one module
at a time can be achieved. The process of interleaving memory
words reduces the chance that sequentially used memory words
will reside in the same memory module and increases the
chance that sequential words can be accessed simultaneously.
In accordance with such an interleaving memory word
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arrangement, words which are normally expected to be used
sequentially are stored in different memory modules.
(Gruner, col. 5, ll. 25-39)

Normally, without interleaving, the most significant bit
or bits (MSB) of an address identify the memory module which
is addressed and the remaining bits of the address identify the
particular word within a memory module. Thus, in a 64K
memory system using eight 8K memory modules, a 16-bit
address is required, the first three most significant bits
identifying the module which is addressed and the remaining 13
bits identifying one word of the 8K words within such selected
module.
If the memory words are interleaved in a 8-way
interleaving arrangement, it can be shown that the three least
significant bits (LSB) identify the module which is addressed,
while the remaining 13 bits identify one word of the 8K words
within such module.
(Gruner, col. 6, ll. 13-26).

We begin by broadly but reasonably construing a “virtual address” in
accordance with its plain meaning as requiring a mapping between a defined
virtual address space and a physical address space. The Examiner finds
that, because “Gruner’s storing of words in different memory modules
means that the inputted addresses are mapped to different modules, . . . there
is a conversion between the inputted address and the address the actual
memory modules see.” (Ans. 11-12, emphasis added).
We agree with the Examiner that Gruner teaches a conversion
between the inputted address which is 16 bits (as required to address a 64K
memory physical memory space containing 2^16 memory locations) and the
13-bit address that the respective eight physical memory modules “see” (i.e.,
13-bits are required to address the 8K (2^13) memory locations within a
particular 8K memory module).
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However, we find this conversion is merely the result of decoding a
physical 16-bit address as required to address eight 8K physical memory
modules. Thus, the 16-bit address in Gruner is an absolute machine address
that specifies a physical location in memory, and is not a virtual or logical
address which is typically used to address a virtual memory space that may
exceed the available physical memory of the machine, and where memory
pages may be swapped between physical memory and the hard disk using
page frames and page faults.
In particular, the Examiner has not shown where any virtual address
space is defined in Gruner that is mapped to a physical address space. In
Gruner’s interleaved method of addressing eight memory modules of 8K
each, the physical address space is 64K (i.e., the sum total of the memory
locations contained in eight 8K memory modules).
In accordance with Gruner’s disclosed interleaving method, the least
significant three bits of the 16-bit address are decoded to enable and select
one of the eight 8K memory modules. (Gruner, col. 6, ll. 22-25). The most
significant 13 bits of the 16 bit address are used to address the respective
memory locations contained within a selected 8K memory module. (Gruner,
col. 6, ll. 25-26).
In summary, we find Gruner’s “conversion” at best merely teaches a
conventional method of decoding a physical 16-bit absolute machine address
to address the sum total of 64K physical memory locations as contained
within eight 8K physical memory modules. Thus, in our view, the Examiner
has confused conventional physical address decoding with virtual address to
physical address mapping.
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Because we find the weight of the evidence supports Appellant’s
position as articulated in the Brief, we reverse the Examiner’s rejection of
independent claim 16 and also associated dependent claims 17-20, which
stand therewith.

DECISION
We affirm the Examiner’s rejection of claims 1-5, 7, 8, 10-13, 15, 21,
and 22.
We reverse the Examiner’s rejection of claims 16-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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