Ex Parte Chen et al

Patent Trial and Appeal BoardFeb 15, 2019

14846411 (P.T.A.B. Feb. 15, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/846,411 09/04/2015 73462 7590 02/20/2019 Hall Estill Attorneys at Law (Seagate Technology LLC) 100 North Broadway, Suite 2900 Oklahoma City, OK 73102-8820 FIRST NAMED INVENTOR Yiran Chen UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. STL14871.l 1192 EXAMINER DUDEK JR, EDWARD J ART UNIT PAPER NUMBER 2136 NOTIFICATION DATE DELIVERY MODE 02/20/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): danderson@hallestill.com okcipdocketing@hallestill.com USPTO@dockettrak.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte YIRAN CHEN, HAI LI, WENZHONG ZHU, XIAOBIN WANG, YUAN YAN, and HARRY HONGYUE LIU Appeal2018-005540 Application 14/846,411 1 Technology Center 2100 Before JAMES R. HUGHES, ERIC S. FRAHM, and JOYCE CRAIG, Administrative Patent Judges. FRAHM, Administrative Patent Judge. DECISION ON APPEAL 1 According to Appellants, Seagate Technology, LLC is the real party in interest (Br. 1 ). Appeal2018-005540 Application 14/846,411 STATEMENT OF THE CASE Introduction Appellants appeal under 35 U.S.C. Â§ I34(a) from a final rejection of claims 1-20. We have jurisdiction under 35 U.S.C. Â§ 6(b ). We affirm. Disclosed Invention and Exemplary Claim Appellants' disclosed invention relates to a data storage device made of semiconductor arrays of solid-state memory cells, and having first and second non-volatile (e.g., RRAM, STRAM, flash etc.) memory arrays of different types (Spec. 1:7-13; 2:14--15, 3:7-22; Title; Abs., Fig. 1; claim 1). Appellants' disclosed and claimed invention also relates to methods for updating data in such a data storage device ( claims 11 and 16). Representative independent claim 1, with emphasis on the disputed portion of the claim, reads as follows: 1. An apparatus comprising a data storage device having first and second non-volatile memory arrays, the first non-volatile memory array comprising a first type of memory that cannot be updated in-place, the second non-volatile memory array comprising a second type of memory that can be updated in- place, the first non-volatile memory storing at least one out-of- date version of data and the second non-volatile memory storing a current version of the data. Examiner's Rejections (1) The Examiner rejected claims 1-9 and 11-20 as being unpatentable under 35 U.S.C. Â§ I03(a) over Cheon (US 2011/0219180 Al; published Sept. 8, 2011 and effectively filed Feb. 6, 2007), Hitachi, Ltd., Prototype 2 Mbit Non-Volatile RAM Chip Employing Spin-Transfer Torque Writing Method, pp. 2--4 (2007) (hereinafter, "Hitachi"), Peter Clarke, 2 Appeal2018-005540 Application 14/846,411 Resistive RAM sets chip companies racing, pp. 2-3 (2006) (hereinafter, "Clarke"), Gonzalez (US 2004/0083335 Al; published April 29, 2004), and Matsuura (US 2007/0214309 Al; published Sept. 13, 2007). Final Act. 3- 11; Ans. 2-11. (2) The Examiner rejected claim 10 under 35 U.S.C. Â§ I03(a) as being unpatentable over the combination of Cheon, Hitachi, Clarke, Gonzalez, and Cheng (US 2009/0106513 Al; published April 23, 2009 and filed Oct. 22, 2007). Final Act. 11-12; Ans. 11. Appellants ' Contentions in the Appeal Brief Appellants present arguments as to claims 1-20 (see Br. 5-8), "using independent claim 1 as a representative claim" (Br. 5). Independent claims 1 (apparatus), 11 (method), and 16 (method) each claim similar limitations regarding a first non-volatile memory array of a first type "that cannot be updated in-place," and a second non-volatile memory array of a second type "that can be updated in-place" ( claim 1 ). Appellants do not separately address claim 10 (rejected over Cheon, Hitachi, Clarke, and Gonzalez taken with Cheng instead of Matsuura). We select independent claim 1 as representative of the group of claims rejected underÂ§ I03(a) over Cheon, Hitachi, Clarke, Gonzalez, and Matsuura (claims 1-9 and 11-20), pursuant to our authority under 37 C.F.R. Â§ 4I.37(c)(l)(iv). Accordingly, our analysis herein will only address representative claim 1. We will decide the outcome of claim 10 rejected over the combination of Cheon, Hitachi, Clarke, Gonzalez, and Cheng based on the outcome for claim 1 from which claim 10 directly depends. Appellants contend that the Examiner erred in rejecting claim 1 under 35 U.S.C. Â§ I03(a) as being unpatentable over Cheon, Hitachi, Clarke, 3 Appeal2018-005540 Application 14/846,411 Gonzalez, and Matsuura for numerous reasons, including: ( 1) "Cheon, Hitachi, Clarke, Gonzalez, and [Matsuura] individually and collectively fail to teach or suggest the rewritable in- place memory used with non-rewritable in-place memory to store current and out-of-date versions of data" (Br. 5) ( emphasis omitted); (2) Because "each cited reference exclusively teaches using only one type of memory, either rewritable in-place or non-rewritable in-place," each cited reference teaches away from the present claims (Br. 6); (3) "the cells of Cheon are exclusively flash memory that cannot be rewritten in-place and Cheon does not suggest any substitution of a single or multi-level flash cell with a rewritable in- place memory, as claimed" (Br. 7); and ( 4) the Examiner's rationale for combining Cheon is conclusory because Cheon does not prohibit changing Cheon by replacing the flash memory with either Hitachi's STRAM or Clarke's RRAM (Br. 7). Examiner's Response in the Answer The Examiner responds to Appellants' arguments in the Brief with articulated reasoning and findings, including (i) finding that "Cheon discloses a memory system that utilizes two types of flash memory, SLC and MLC" (Ans. 12); (ii) "Hitachi and Clark[ e] provide details about STRAM and RRAM" (Ans. 12); and (iii) "[n]one of the references criticize, discredit, or otherwise discourage using the memories described alongside each other" (Ans. 12). Simply put, the Examiner determines (Ans. 12-13) that the combination of Cheon, Hitachi, and Clarke teaches or suggests using a 4 Appeal2018-005540 Application 14/846,411 rewriteable in-place memory (Hitachi and/or Clarke) in the hybrid memory data storage device of Cheon (see, e.g., Cheon ,r 35; Ans. 13). The Examiner's reasoning for the combination is restated in the Answer: Cheon discloses the use of two types of memory, SLC flash and MLC flash (see [0035]). The SLC array is used as a buffer for write data categorized as having a random-writing pattern (see [0039]). At a future time, the data that was stored in the SLC blocks are copied over to MLC blocks (see [0043] and [0051]). One would understand that the SLC blocks are only used for temporary data storage. The SLC blocks provide a buffer that enhances the data write speed (see [0041]). Hitachi and Clarke disclose alternative types of non-volatile memory, STRAM and RRAM. These memories are non-volatile, can be updated in-place, and provide higher performance than SLC flash. Substituting the STRAM or RRAM for the SLC flash would provide a performance improvement and eliminate the overhead associated with erase cycles in flash memory. The resulting combination results in an improved system without breaking the base reference (Cheon). Replacing the SLC memory buffer with S TRAM/RRAM results in improved peiformance due to the higher performing STRAM/RRAM and reduction of overhead associated with garbage collection while still retaining the non-volatile characteristics. One of ordinary skill in the art would possess the knowledge necessary to assemble a system that uses a combination of STRAM/RRAM and flash memory. The majority, if not all, of the computer systems in the world contain a combination of different types of memory, so it is a common chore to build such a system. Ans. 13-14 (emphases added). Principal Issue on Appeal Based on Appellants' arguments (App. Br. 4--8), the following principal issue is presented: Did the Examiner err in rejecting claims 1-20 as being obvious because the base combination of Cheon, Hitachi, Clarke, and Gonzalez is 5 Appeal2018-005540 Application 14/846,411 not properly combinable to teach or suggest a data storage device having two types of non-volatile memory arrays, as set forth in representative claim 1? ANALYSIS We have reviewed the Examiner's rejections (Final Act. 3-12; Ans. 2-11) in light of Appellants' contentions in the Appeal Brief (Br. 5-7) that the Examiner has erred, as well as the Examiner's response to Appellants' arguments in the Appeal Brief (Ans. 12-14). We disagree with Appellants' contentions. With regard to representative claim 1, we adopt as our own ( 1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken (Final Act. 3--4; Ans. 2--4); (2) the additional findings and reasoning set forth in the Advisory Action mailed May 16, 2017 (p. 2); and (3) the reasons set forth by the Examiner in the Examiner's Answer in response to Appellants' Appeal Brief (see Ans. 12-14). Appellants' contention (Br. 6) that "each cited reference exclusively teaches using only one type of memory" is not persuasive inasmuch as Cheon specifically discloses a hybrid memory having two types of memory arrays, SLC and MLC (see Cheon ,r 35). Appellants do not dispute the Examiner's findings that the applied references collectively teach or suggest the two types of non-volatile memory arrays recited (a first type that can, and a second type that cannot, be updated in-place), or that Cheon teaches combining two types of memory arrays into a hybrid array to provide the benefits of both types of memories. With regard to claim 1, we agree with the Examiner's findings with regard to Cheon, Hitachi, and Clarke (Final Act. 3--4; Ans. 2--4), as well as the Examiner's well-articulated reasoning for 6 Appeal2018-005540 Application 14/846,411 making the combination (see Ans. 12-14). Appellants have not filed a Reply Brief, or otherwise rebutted the Examiner's findings and reasoning with persuasive evidence or argument. In view of the foregoing, we sustain the Examiner's obviousness rejection of independent claim 1, as well as claims 2-9 and 11-20 grouped therewith. For similar reasons, and because (i) claim 10 depends directly from independent claim 1 and therefore contains all of the salient limitations, and (ii) Appellants argue claim 10 is patentable for the same reasons as claim 1 (see App. Br. 8), we also sustain the Examiner's obviousness rejections of dependent claim 10. CONCLUSIONS Cheon, Hitachi, Clarke, Gonzalez, and Matsuura are properly combinable, and the combination teaches or suggests a computer program product for performing a method of preventing login attempts on an electronic device based on a stored itinerary of destinations and a monitored location of the device, as set forth in representative claim 1. Appellants have not sufficiently shown that the Examiner erred in rejecting claims 1-20 under 35 U.S.C. Â§ 103(a). Thus, we sustain the rejections before us. 7 Appeal2018-005540 Application 14/846,411 DECISION The Examiner's rejections of claims 1-20 under 35 U.S.C. Â§ 103(a) are affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 3 7 C.F .R. Â§ 1.13 6( a )(1 )(iv). AFFIRMED 8