Ex Parte Chen et alDownload PDFPatent Trial and Appeal BoardApr 23, 201311381790 (P.T.A.B. Apr. 23, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte WEN-TZER THOMAS CHEN, JIMMIE EARL JR. DEWITT, FRANK ELIOT LEVINE, and ENIO MANUEL PINEDA ____________________ Appeal 2010-010527 Application 11/381,790 Technology Center 2100 ____________________ Before: KALYAN K. DESHPANDE, JOHNNY A. KUMAR, and MICHAEL J. STRAUSS, Administrative Patent Judges. STRAUSS, Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-010527 Application 11/381,790 2 STATEMENT OF CASE Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. The claims are directed to a method and apparatus for hardware assisted profiling of code. Abstract. Claims 1 and 8, reproduced below, are illustrative of the claimed subject matter: 1. A computer implemented method for executing instructions by a computer, the computer implemented method comprising: responsive to a processor executing a plurality of instructions, determining whether the processor is in an instrumentation mode; and responsive to the processor being in the instrumentation mode, executing instrumentation instructions associated with the plurality of instructions, wherein the instrumentation instructions are unexecuted in response to an absence of the processor being in the instrumentation mode; wherein the instrumentation mode determination determines which of a plurality of processor resources of the computer will be used by the processor to execute certain ones of the plurality of instrumentation instructions in response to fetching at least one of the plurality of instructions based upon whether the processor is in the instrumentation mode, wherein the instrumentation instructions are a set of trace instructions used to obtain trace data about operations and events that occur during execution by the processor of at least some of the plurality of instructions. 8. A data processing system apparatus comprising: a bus; a communications unit connected to the bus; Appeal 2010-010527 Application 11/381,790 3 a storage device connected to the bus, wherein the storage device includes computer usable program code; and a processor unit connected to the bus, wherein the processor unit executes the computer usable program code to determine whether a processor is in an instrumentation mode in response to the processor executing a plurality of instructions; and execute instrumentation instructions associated with the plurality of instructions in response to the processor being in the instrumentation mode, wherein the instrumentation instructions are unexecuted in response to an absence of the processor being in the instrumentation mode; and wherein the instrumentation mode determination determines which of a plurality of processor resources of the data processing system will be used by the processor to execute certain ones of the plurality of instructions in response to fetching at least one of the plurality of instructions based upon whether the processor is in the instrumentation mode, wherein the instrumentation instructions are a set of trace instructions used to obtain trace data about operations and events that occur during execution by the processor of at least some of the plurality of instructions. REFERENCES The prior art relied upon by the Examiner in rejecting the claims on appeal is: Jaggar Huck US 6,343,358 B1 US 6,654,877 B1 Jan. 29, 2002 Nov. 25, 2003 Oplinger et al., Enhancing Software Reliability with Speculative Threads, pp. 184-196, Computer Systems Laboratory: Stanford University (October 2002). REJECTIONS The Examiner made the following rejections: Claims 8-14 stand rejected under 35 U.S.C. § 101 as being directed to non-statutory subject matter. Ans. 4. Appeal 2010-010527 Application 11/381,790 4 Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Huck, Jaggar, and Oplinger. Ans. 5. ISSUES ON APPEAL Based on Appellants’ arguments in the Appeal Brief (App. Br. 10-20) and Reply Brief (Reply Br. 2-5) the issues presented on appeal are (i) whether claims 8-14 are directed to statutory subject matter, (ii) whether the Examiner erred in combining the disclosures of Huck, Jaggar and Oplinger, and (iii) whether the asserted combination of references teaches or suggests the invention as recited in the disputed claims. ANALYSIS We have reviewed the Examiner’s rejections in light of Appellants’ arguments that the Examiner has erred. We consider Appellants’ arguments seriatim as they are presented in the principal Brief pages 10-20. Rejection under 35 U.S.C. § 101 Appellants contend that “apparatus claims 8-14 explicitly recite hardware elements including a bus, a communication unit, a storage device and a processor unit, and yet the Examiner ignores these specifically claimed hardware elements and instead points to a comment in the Specification that the invention can be implemented solely in software as the basis for the non- statutory rejection.” App. Br. 10. The Examiner responds that: While it is true that one of ordinary skill in the art might interpret “a bus, a communication unit, a storage device and a Appeal 2010-010527 Application 11/381,790 5 processor unit” as hardware elements, page 56, paragraph 00172 of the appellant’s original specification reads as follows: [00172] The invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in hardware, but controlled by software, which includes but is not limited to firmware, resident software, microcode, etc. Ans. 15. The Examiner concludes that “an interpretation of these elements of the claimed invention as being hardware elements is inconsistent with the specification, which explicitly states that ‘the invention can take the form of ... an entirely software embodiment.’” Id. We disagree because the cited paragraph discloses that an embodiment of the invention can be entirely software, while another embodiment can be entirely hardware, and still another could be a combination of software and hardware. However, that does not mean that each element of every claim must also be realizable so that each and every claim encompasses all disclosed embodiments, i.e., that the claimed bus, communications unit, storage device and processor unit of claim 8 must be capable of being realized as software alone or hardware alone. That is, there is no indication that claim 8 covers an entirely software embodiment of the invention even though the Specification discloses the potential for such an embodiment, the latter presumably definable by a claim not including the recitation of hardware. Therefore we find, consistent with the Specification, that claim 8 together with claims 9-14 dependent therefrom require hardware elements in the form of a bus and a storage device such that the claimed apparatus includes physical articles or objects. Appeal 2010-010527 Application 11/381,790 6 Accordingly, we find that claims 8-14 are directed to statutory subject matter and we do not sustain the rejection of those claims under 35 U.S.C. § 101. Rejections under 35 U.S.C. § 103(a) In connection with the rejections of claims 1-20 under 35 U.S.C. § 103(a), we disagree with Appellants’ contentions as to all those rejections. In connection with those rejections, we adopt as our own (1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken and (2) the reasons set forth by the Examiner in the Examiner’s Answer in response to Appellants’ Appeal Brief and we concur with the conclusions reached by the Examiner. We highlight the following arguments for emphasis. Claims 1, 3, 8, 10 and 15-19 In connection with claims 1, 3, 8, 10 and 15-19 Appellants contend that, unlike the prior art that discloses two processors (a generalized main processor and a specialized debug coprocessor), claim 1 recites a single processor that “(1) executes instructions, (2) can be in a special instrumentation mode, (3) processor resources are determined based upon whether such processor is in the special instrumentation mode, and (4) has operations and events traced that occur during its (per Claim 1: ‘processor’) execution of instructions.” App. Br. 12-13. In particular Appellants argue that Jaggar’s debug processor “(1) does not have a special mode (‘instrumentation mode’) for which resource utilization determination is based upon . . . and instruction execution of such debug co-processor thereof is not - and cannot be - traced, as is provided by the claimed ‘processor’ in combination with the trace instructions.” App. Br. 13. Appeal 2010-010527 Application 11/381,790 7 The Examiner responds that claim 1 does not require executing the regular instructions and instrumentation instructions in the same processor. Ans. 16. The Examiner explains: For instance, the claim recites “responsive to the processor being in the instrumentation mode, executing instrumentation instructions associated with the plurality of instructions”, and “wherein the instrumentation mode determination determines which of a plurality of processor resources of the computer will be used by the processor to execute certain ones of the plurality of instrumentation instructions in response to fetching at least one of the plurality of instructions ... ”, neither of which requires that the instrumentation instructions be executed by the first processor. Id. We agree with the Examiner because Appellants’ Specification contemplates that each of the processors may comprise two or more processors (Spec. [0033]) and that a processing unit may include one or more processors or CPUs (Spec. [0038]). While Appellants argue that “the separate processor of Figure 4 is an alternative embodiment that is claimed in related application serial # 11/381,798 - and it is not unusual or extraordinary to provide varying different embodiments in a common Specification” (Reply Br. 3), this does not provide a definition of processor that is commensurate with Appellants’ arguments or otherwise limit the scope of the disputed claims to exclude multiple processors1. We disagree 1 Any special meaning assigned to a term “must be sufficiently clear in the specification that any departure from common usage would be so understood by a person of experience in the field of the invention.” Multiform Desiccants Inc. v. Medzam Ltd., 133 F.3d 1473, 1477 (Fed. Cir. 1998); see also Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F.3d 1379, 1381 (Fed. Cir. 2008) (“A patentee may act as its own lexicographer and assign to Appeal 2010-010527 Application 11/381,790 8 with Appellants that “per Claim 1, a single processor [must be] used to self- trace its actions.” Id. (emphasis added). Claim 1 does not recite a “single” processor, and thus Appellants’ arguments are not commensurate in scope with claim 1. Accordingly, Appellants’ contention is unpersuasive of Examiner error. Appellants further argue that there is no showing “regarding the ‘processor’ that is explicitly recited in the trace instruction aspect of Claim 1” (App. Br. 13), i.e., the prior art fails to teach or suggest “wherein the instrumentation instructions are a set of trace instructions used to obtain trace data about operations and events that occur during execution by the processor of at least some of the plurality of instructions.” The Examiner responds “Oplinger teaches the explicit tracing of events in a processor, while Huck and Jagger both teach testing/debugging functions that monitor a main processor executing instructions, which is a way of obtaining ‘trace data about operations and events that occur during execution by the processor of at least some of the plurality of instructions.’” Ans. 18. Since we find supra that claim 1 is not limited to a single processor, the trace instructions used to obtain trace data about operations and events that occur during execution may be executed by a different processor. Therefore, Appellants’ arguments are not commensurate in scope with claim 1. Accordingly, these arguments are also unpersuasive of Examiner error. Appellants also argue that the references are not properly combinable. App. Br. 13-15. In particular Appellants contend that the asserted combination is improper because: a term a unique definition that is different from its ordinary and customary meaning; however, a patentee must clearly express that intent in the written description.” (citation omitted)). Appeal 2010-010527 Application 11/381,790 9 (a) There is no motivation to combine the disparate architectures of Jaggar, “a hardware-based technique for performing debug operations”, and Oplinger, “a software-based technique for speculatively executing code in parallel by a thread.” App. Br. 13-14. (b) “[Jaggar’s] main processor actually drains instructions out of its pipeline - meaning the processor’s operations and events cannot be traced while the debug processor is executing instructions.” Id. (emphasis omitted). (c) “A person of ordinary skill in the art would . . . not be motivated to modify Huck’s parallel multi-pipelined system to determine processor resource utilization based on processor mode, as alleged taught by Jaggar, as such a change would adversely effect the system performance that Huck is so keen on providing (Huck col. 1, lines 62-67; col. 7, lines 11-25).” App. Br. 15. (d) “[A] person of ordinary skill in the art would not have been motivated to somehow combine the functionality provided by the separate specialized debug processor circuitry into the main processor, and eliminate the separate specialized debug processor, as the resulting advantages of combining these two cited references would no longer exist due to the elimination of this separate specialized debug processor.” Id. (emphasis omitted). Addressing contention (a), the Examiner finds that the motivation for modifying Huck according to Jaggar would have been that it is known to provide data processing systems with debug mechanisms for assisting the processor in the debugging of hardware and software (column 1, lines 12- 18) where providing separate debug logic increases the operational speed of the debug mode since the instructions can Appeal 2010-010527 Application 11/381,790 10 be handled by the separate logic and need only be transferred once (abstract). Ans. 7-8 (emphasis and brackets in original omitted). The Examiner explains that [t]he motivation for [using the SMP profiling system of Oplinger (including trace instructions) for running instrumentation/debug mode instructions in the debug mode taught by Huck], as provided by Oplinger, would have been the monitoring function performing profiling allows for the user to gain a better understanding of bottlenecks in the system to improve the performance of programs (page 185, section 2.1, paragraph 1) and, furthermore, the use of computer architecture support makes this ‘monitor-and-recover’ style of programming both more efficient and easier to write (Oplinger, page 184, section 1, second paragraph). Ans. 8 (emphasis and brackets in original omitted). We find that the Examiner has provided sufficient articulated reasoning with rational underpinning to support the legal conclusion of obviousness. While Appellants argue that Jaggar and Oplinger use different techniques, (App. Br. 13-14) Appellants fail to provide sufficient evidence supporting, or argument explaining, why the Examiner’s reasoning is flawed and “a person of ordinary skill in the art would not have been motivated to combine these disparate teachings from two totally different and incompatible debug techniques” (id.) We note all of the features of the secondary reference need not be bodily incorporated into the primary reference, but consideration should be given to what the combined teachings, knowledge of one of ordinary skill in the art, and the nature of the problem to be solved as a whole would have suggested to those of ordinary skill in the art (see In re Keller, 642 F.2d 413, 425 (CCPA 1981)). The Appeal 2010-010527 Application 11/381,790 11 artisan is not compelled to blindly follow the teaching of one prior art reference over the other without the exercise of independent judgment (see Lear Siegler, Inc. v. Aeroquip Corp., 733 F.2d 881, 889 (Fed. Cir. 1984)). Accordingly, one skilled in the art would not be dissuaded from combining the teachings of Jaggar and Oplinger merely because they use different techniques, one hardware-based and the other software-based. Appellants further argue that “Oplinger requires that the error recovery code always be executed in parallel such that recovery can occur in the event of any error [so that the] system would not need to make any type of instrumentation mode determination to determine which resources will be used by the processor to execute instrumentation instructions, as per the claimed instrumentation mode determination features expressly recited in Claim 1.” App. Br. 14 (emphasis and citation omitted). Appellants still further argue that because “(Jaggar) seeks to selectively invoke debugging and . . . (Oplinger) requires continuous debugging in order to provide an error recovery mechanism that includes a fail-over capability upon error detection” (id.), that there is no motivation to combine “such [dissimilar] teachings” (id.) We disagree that selective and continuous debugging are so fundamentally different as to negate the reasons for combining the teachings of the references articulated by the Examiner. As explained supra and by the Examiner, “the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in anyone or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of Appeal 2010-010527 Application 11/381,790 12 ordinary skill in the art.” Ans. 19 (citing to In re Keller, 642 F.2d 413). Accordingly contention (a) is unpersuasive of Examiner error. In connection with contention (b) Appellants further assert that Jaggar and Oplinger are not properly combinable because Jaggar teaches draining instructions out of its pipeline so that tracing cannot be performed while the debug process is executing instructions. App. Br. 14. The Examiner responds: Regarding Jaggar’s draining of the instruction in the main processor pipeline (as alluded to by appellant and illustrated in Jaggar’s figure 4); this is due to the fact that Jaggar’s debugging/testing is being run by passing multiple values to the same instruction in the main processor core while the debug coprocessor executes debug instructions, to test outputs, (see, e.g., Jaggar, abstract and column 5) so that different instructions are not drawn in while that instruction is being tested on different data sets/values. However, the advantages provided by the debug coprocessor of Jaggar (as described above) would still be applicable to a system which continues to run separate instructions with different data, rather than a single instruction with different data, as in both cases the main processor core continues to execute and continues to be monitored while the debug coprocessor core runs the debug/testing code. Ans. 19-20. We find the Examiner’s explanation to be reasonable. Furthermore, Jaggar is applied for disclosing that the instrumentation mode determination determines which of a plurality of processor resources of the computer will be used by the processor to execute certain ones of the plurality of instrumentation instructions in response to fetching at least one of the plurality of instructions based upon whether the processor is in the instrumentation mode. Ans. 7. To the extent that “[Jaggar’s] main Appeal 2010-010527 Application 11/381,790 13 processor actually drains instructions out of its pipeline [so that] processor’s operations and events cannot be traced while the debug processor is executing instructions” (App. Br. 14), Appellants’ arguments are based on bodily incorporation and the blind following of Jaggar over Huck without the exercise of independent judgment. Appellants have presented no evidence that modifying Huck according to Jaggar was “uniquely challenging or difficult for one of ordinary skill in the art” or “represented an unobvious step over the prior art.” See Leapfrog Enters., Inc. v. Fisher- Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418-19 (2007)). Accordingly, contention (b) is not persuasive of Examiner error. In connection with contention (c), we agree with the Examiner that Appellants fail to provide sufficient evidence or argument in support of their contention that system performance would be adversely affected. Ans. 21. Attorney arguments and conclusory statements that are unsupported by factual evidence are entitled to little probative value. See In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); see also In re De Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984.) Accordingly, contention (c) is not persuasive of Examiner error. In connection with contention (d), Appellants’ arguments are again improperly premised on use of a single processor. As we find that the disputed claims are not limited to a single processor, such arguments are not commensurate in scope of the claims and are not persuasive of Examiner error. For the reasons discussed supra, we find that Appellants have failed to provide sufficient evidence or argument to persuade us that the combination Appeal 2010-010527 Application 11/381,790 14 of Huck, Jaggar, and Oplinger is improper or fails to teach or suggest the disputed claim limitations. Therefore, we sustain the rejection of claim 1 together with the rejections of claims 3, 8, 10, and 15-19 not separately argued. Claims 2, 4, 5, 9, 11 and 12 Appellants argue the prior art fails to teach or suggest “that the instrumentation mode determination is made by the instruction cache unit” as recited by claim 2. App. Br. 16. The Examiner responds that Huck discloses that the mode indicator is asserted at run time while Jaggar discloses the instruction cache as in input device such that the combination teaches or suggests the disputed limitation. Given Huck’s mode indicator and Jaggar’s cache storing the mode indicator, we agree with the Examiner that the combination teaches or suggests “determining, by an instruction cache unit of the computer, whether an indicator is set in a register in the processor, wherein the indicator indicates whether the processor is in the instrumentation mode.” Therefore, these arguments are unpersuasive of Examiner error. Appellants further argue the references are not properly combinable. App. Br. 16-17. In particular, Appellants argue that Huck requires a specialized control circuit and that: [A] person of ordinary skill in the art would not have been motivated to modify the Huck/Jaggar combination in accordance with the missing features recited in Claim 2 as such a change would adversely effect Huck’s dual-pipeline control architecture where a special control circuit is used to either execute a pipeline instruction, or not, based upon the mode indicator and the specialized pipeline control circuitry - further evidencing non-obviousness of Claim 2 and its erroneous obviousness rejection. Appeal 2010-010527 Application 11/381,790 15 App. Br. 17. The Examiner responds that the mode indicator is accessed by a unit of the processor with access to run time instruction data, which obviously includes the instruction cache, and using the cache as the means of checking the status would not change the operation of the invention, as in any case a unit of the processor with access to run time instruction data is setting and determining the status of the mode indicator. Ans. 22. Appellants have provided insufficient evidence or argument of the asserted adverse effect on Huck’s dual-pipeline control architecture or otherwise to persuade us that the Examiner’s reasoning and rationale to support the legal conclusion of obviousness is erroneous. Appellants’ arguments are again based on bodily incorporation of Jaggar’s instruction cache into the pipeline of Huck without the exercise of independent judgment. Appellants have presented no evidence that modifying Huck according to Jaggar was uniquely challenging or difficult for one of ordinary skill in the art or presented an unobvious step over the prior art. Accordingly, these arguments are also unpersuasive of Examiner error. For the reasons discussed supra, we find that Appellants have failed to provide sufficient evidence or argument to persuade us that the combination of Huck, Jaggar, and Oplinger is improper or fails to teach or suggest the disputed claim limitations. Therefore, we sustain the rejection of claim 2 together with the rejections of claims 4, 5, 9, 11 and 12 not separately argued. Appeal 2010-010527 Application 11/381,790 16 Claims 6, 13 and 20 Appellants argue “Huck[’s] description of setting a mode indicator . . . does not teach or suggest the setting of a indicator using a policy that includes a plurality of rules that specify under what conditions the instrumentation mode should be enabled, as claimed.” App. Br. 18-19. Appellants emphasize that claim 6 is directed to characteristics pertaining to the ‘policy’ aspect of setting the instrumentation mode indicator, where such policy includes a plurality of rules that specify under what conditions the instrumentation mode should be enabled. In contrast, Huck's configuration is modified based on raw data (“runtime data”, see Huck col. 5, lines 4-28), and not a plurality of rules, as claimed. App. Br. 18 (footnote omitted). The Examiner responds that Huck discloses a number of input data values at runtime thereby disclosing a plurality of rules. While Appellants quote the passages of Huck cited to and relied upon by the Examiner, asserting that the disputed claim language is not taught or suggested thereby, Appellants do not address the Examiner’s findings directly or indicate why “runtime data … indicative of whether or not the testing code . . . is to be enabled or disabled” (Huck col. 5, ll. 9-11) does not teach or suggest a plurality of rules that specify under what conditions the instrumentation mode should be enabled. Therefore, in the absence of sufficient evidence or argument that the disputed claim language is not taught or suggested by the asserted combination of references, Appellants’ arguments are unpersuasive of Examiner error. Accordingly, we sustain the rejection of claim 6 together with the rejections of claims 13 and 20 not separately argued. Appeal 2010-010527 Application 11/381,790 17 Claims 7 and 14 Appellants argue Jaggar does not teach or suggest “that the instrumentation instructions are identified using address range registers in the instruction cache unit” nor is such limitation “purely a matter of design choice.” App. Br. 19-20 (emphasis omitted). The Examiner responds that Jaggar’s bank of watchpoint and breakpoint registers disclose “address range registers” since “they are monitoring the instructions for a range of addresses.” Ans. 25. We find the Examiner’s finding to be reasonable. Appellants further argue that Jaggar’s watchpoint and breakpoint registers “are required to be contained within the co-processor itself.” App. Br. 20. Appellants conclude that [m]odifying the teachings of Jaggar to place these registers in the Jaggar instruction cache is therefore not ‘purely a matter of design choice’ as erroneously alleged by the Examiner, as Jaggar expressly teaches away from such a design due to its expressed desire to maintain these registers within the specialized co-processor itself such that the co-processor itself is able to monitor busses and provide hit signals to the main processor when detecting a matching condition. Id. We disagree with Appellants. “A reference may be said to teach away when a person of ordinary skill, upon reading the reference, would be discouraged from following the path set out in the reference, or would be led in a direction divergent from the path that was taken by the applicant.” Ricoh Co., Ltd. v. Quanta Computer, Inc., 550 F.3d 1325, 1332 (Fed. Cir. 2008) (citations omitted). A reference does not teach away if it merely expresses a general preference for an alternative invention from amongst options available to the ordinarily skilled artisan, and the reference does not discredit Appeal 2010-010527 Application 11/381,790 18 or discourage investigation into the invention claimed. In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004). Here, we find that Appellants have not provided sufficient evidence that Jaggar discourages or discredits placing the registers in the cache structure particularly when used in other environments such as in the asserted combination with the instrumentation instructions of Huck. For the reasons supra and in the absence of sufficient evidence or argument to the contrary Appellants’ argument are not persuasive of Examiner error. Accordingly, we sustain the rejection of claim 7 together with the rejection of claim 14 not separately argued. For the reasons supra, we sustain the rejection of claims 1-20 under 35 U.S.C. § 103(a). CONCLUSION The Examiner erred in rejecting claims 8-14 under 35 U.S.C. § 101 as being directed to non-statutory subject matter. The Examiner did not err in rejecting claims 1-20 under 35 U.S.C. § 103(a) as being unpatentable over Huck, Jaggar, and Oplinger. DECISION The decision of the Examiner to reject claims 8-14 under 35 U.S.C. § 101 is reversed. The decision of the Examiner to reject claims 1-20 under 35 U.S.C. § 103(a) is affirmed. Appeal 2010-010527 Application 11/381,790 19 AFFIRMED msc Copy with citationCopy as parenthetical citation