Ex Parte Chang et al

Patent Trial and Appeal Board

Mar 27, 2017

12893484 (P.T.A.B. Mar. 27, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/893,484 09/29/2010 Kuk-Hui Chang 041501-5951 4212
9629 7590 03/29/2017
MORGAN LEWIS & BOCKIUS LLP (WA)
1111 PENNSYLVANIA AVENUE NW
WASHINGTON, DC 20004
EXAMINER
JANSEN II, MICHAEL J
ART UNIT PAPER NUMBER
2696
NOTIFICATION DATE DELIVERY MODE
03/29/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents @ morganlewis.com
karen.catalano @ morganlewis.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KUK-HUI CHANG and YOUNG-NAM LEE
Appeal 2017-000994
Application 12/893,484
Technology Center 2600
Before JOHNNY A. KUMAR, LINZY T. McCARTNEY, and
JAMES W. DEJMEK, Administrative Patent Judges.
McCARTNEY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a rejection of claims
1—4 and 6—9. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
Appeal 2017-000994
Application 12/893,484
STATEMENT OF THE CASE
The present patent application concerns “a driving circuit for a display
device and a method for driving the same.” Spec. 12. Claim 1 illustrates
the claimed subject matter (disputed limitations emphasized):
1. A driving circuit for a display device, comprising:
a plurality of data driving units configured to supply image
data to a display portion of a panel through data link lines formed
at a non-display portion of the panel; and
a driving controller configured to:
sequentially generate a plurality of source output
enable signals to determine output timing of the image
data from the data driving units; and
directly supply each of the source output enable
signals to a respective pair of the data driving units,
among the plurality of data driving units, to directly
control the output timing of each of the plurality of the
data driving units;
wherein the plurality of data driving units and the driving
controller are included in a driving integrated circuit of the
driving circuit,
wherein the driving controller comprises a control signal
generator configured to:
receive a plurality of control signals from an
external system; and
output various timing control signals, including the
source output enable signals,
wherein the control signal generator comprises a plurality
of signal generators each configured to:
generate a corresponding source output enable
signal, among the plurality of source output enable
signals, and
directly supply the corresponding source output
enable signal to a corresponding pair of the data driving
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Application 12/893,484
units, among the plurality of data driving units, through
two output lines at the same time, the corresponding pair
of the data driving units being arranged at both sides of the
driving controller,
wherein all of the plurality of source output enable signals
are generated in response to one of the plurality of control signals
from the external system,
wherein the plurality of source output enable signals are
sequentially generated by the plurality of signal generators, and
wherein a number of the plurality of signal generators is
half of a number of the plurality of the data driving units.
REJECTION
Claims 1—4 and 6—9 stand rejected under 35 U.S.C. § 103(a) as
unpatenable over Ha et al. (US 2009/0058788 Al; Mar. 5, 2009), Suh et al.
(US 2009/0045733 Al; Feb. 19, 2009), and Kim et al. (US 2008/0273002
Al; Nov. 6, 2008).
ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellants’
arguments, and we disagree with Appellants that the Examiner erred. To the
extent consistent with the analysis below, we adopt the Examiner’s
reasoning, findings, and conclusions set forth in the appealed action and the
Examiner’s Answer. We have limited our review to the arguments raised by
Appellants. Appellants have waived arguments Appellants failed to raise or
properly develop. See 37 C.F.R. §§ 41.37(c)(l)(iv), 41.41(b)(2).
Appellants contend Ha does not teach or suggest the emphasized
limitations in part because Ha discloses the same number of delay parts and
data integrated circuits (ICs). See App. Br. 7—8. Appellants argue the
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Application 12/893,484
Examiner erroneously concluded it would have been obvious to reduce the
number of delay parts to half the number of data ICs by combining the delay
parts into a single circuit. See App. Br. 8—11. Appellants contend this
conclusion rests on the erroneous finding that Ha teaches or suggests
outputting data at the same time because Ha discloses “symmetric” data
output timing. See id. at 9-10. According to Appellants, “[bjecause Ha . . .
discloses different optional timings and a markedly different physical
structure it would not be inherent that the same signal is output... at the
same time.” Id. at 9. Appellants also argue combining Ha’s delay parts
would “require significant structural changes” and “would not allow for
asymmetric application of SOE signals, thus modifying Ha ... so that it fails
to function as intended.” Id. at 10—11.
Contrary to Appellants’ arguments, the Examiner did not find that
Ha’s system inherently simultaneously outputs the same signal. Instead, the
Examiner found Ha teaches (1) supplying the same source output enable
(SOE) signal to first and second delay circuits that include the delay parts
discussed above and (2) driving the delay circuits “symmetrically” to
produce equivalent SOE signals. Ans. 4 (citing Ha Fig. 8, 63, 65). The
Examiner found that because Ha’s system supplies the same SOE signal to
the delay circuits and drives the delay circuit symmetrically, Ha’s delaying
parts transmit the same SOE signals to their respective data ICs. See id.', see
also Non-Final Act. 3 (finding the delay parts “produc[e] a pair of the same
respective signals directly to each of the data drivers [i.e., data ICs]”
(emphasis omitted)). The Examiner concluded that, in light of the
“symmetrical configuration” of the delay circuits, it would have been
obvious to combine them into a single circuit because “it has been held that
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Application 12/893,484
forming in one piece an article which has formerly been formed into two
pieces and put together involves only routine skill in the art.” Id.
Appellants’ contention that this conclusion rests on the Examiner’s
erroneous finding that Ha teaches or suggests outputting data at the same
time has not persuaded us the Examiner erred. As found by the Examiner,
Ha discloses “[t]he data output timing of the data ICs . . . included in the
first data drive . . . may be symmetric to the data output timing of the data
ICs . . . included in the second data driver.” Ha 1 65 (emphases added).
Because the delay circuits control the output timing of the ICs, see id. Fig. 8,
62—65, this disclosure would have suggested to (if not taught) one of
ordinary skill in the art that Ha’s delay circuits output data at the same time.
As for Appellants’ argument that the Examiner’s proposed
modification would “require significant structural changes,” Appellants have
not provided persuasive evidence or reasoning to support this argument.
Appellants simply assert the “control timings and power requirements would
be much greater than simply ‘putting together’ two pieces” and “[tjhere are
marked differences between the physical structures of [Appellants’ and
Ha’s] devices.” App. Br. 10; see also Reply Br. 2 (asserting, without
supporting evidence, that the Examiner’s modification “would require more
than simply providing double-sized capacitors and resistors”). But
“[ajrgument in the brief does not take the place of evidence in the record.”
In re Schulze, 346 F.2d 600, 602 (CCPA 1965). The Examiner found that
proposed modification would not require significant changes, see Ans. 7—8,
and Appellants’ conclusory arguments have not persuaded us the Examiner
erred. Moreover, although Appellants contend the Examiner’s modifications
would require significant changes, Appellants do not argue the changes are
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Application 12/893,484
“uniquely challenging or difficult for one of ordinary skill in the art.”
Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir.
2007).
Regarding Appellants’ argument that the Examiner’s combination
“would not allow for asymmetric application of SOE signals, thus modifying
Ha ... so that it fails to function as intended,” as found by the Examiner, Ha
teaches that asymmetric SOE signal application is an alternative function of
Ha’s system. See Ans. 8; see also Ha 1 63 (disclosing time constants in the
first and second delay circuits “may be symmetric or asymmetric” to each
other), | 65 (disclosing the data output timing of the data ICs “may be
symmetric” or “may be asymmetric”). In addition, Ha discloses each
delaying parts has its own time constant, which Ha’s system can set with
different values in order to adjust each data IC’s data output timing. See Ha
Fig. 8,62—65. Thus, even if both the SOE signal lines and the delay
circuits were combined, Ha’s system could still perform both symmetric and
asymmetric SOE signal application by altering the relevant time constants
for the delaying parts. For example, Ha’s system could set the time
constants such the data output times for certain data ICs (e.g., D-IC1 and D-
IC2) shown in Figure 8 each differ from each other.
Finally, Appellants contend the Examiner erred because Ha’s timing
controller is not directly connected to the data driving units. App. Br. 11.
According to Appellants, Ha depicts “the delaying parts . . . disposed
between the timing controller and the data ICs” Id. at 12. Appellants argue
“there is no single item in Ha . . . that has multiple copies each of which
outputs a pair of simultaneous signals, all from a single control signal, as
claimed.” App. Br. 11 (emphases modified).
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Application 12/893,484
We find Appellants’ arguments unpersuasive. The Examiner found
Ha discloses multiple delaying parts that each (1) receive the same SOE
signal, (2) connect to an IC directly, and (3) adjust, either symmetrically or
asymmetrically, the data output timing of its respective data IC. See Ans. 5—
6, 8—9; see also Ha. Fig. 8 (illustrating Ha’s data driving apparatus), Tflf 60-
65 (describing the data driving apparatus depicted in Figure 8). Appellants’
arguments concerning Ha’s timing controller do not address these findings
and are therefore unpersuasive.
For the above reasons, we sustain the Examiner’s rejection of claim 1.
Because Appellants have not presented separate, persuasive argument for
claims 2-4 and 6—9, we also sustain the Examiner’s rejection of these
claims.
DECISION
We affirm the Examiner’s rejection of claims 1—4 and 6—9.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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