Ex Parte Chang et al

Patent Trials and Appeals Board

Apr 24, 2019

13494761 - (D) (P.T.A.B. Apr. 24, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/494,761 06/12/2012 Jichuan Chang
56436 7590 04/26/2019
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
82901999 3489
EXAMINER
BUl,THA-OH
ART UNIT PAPER NUMBER
2825
NOTIFICATION DATE DELIVERY MODE
04/26/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
hpe.ip.mail@hpe.com
chris.mania@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JICHUAN CHANG, DOE HYUN YOON, and
PARTHASARATHY RANGANATHAN
Appeal2017-007223
Application 13/494,761
Technology Center 2800
Before ROMULO H. DELMENDO, CHRISTOPHER L. OGDEN, and
JEFFREY R. SNAY, Administrative Patent Judges.
DELMENDO, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2017-007223
Application 13/494,761
The Applicants ("Appellants") 1 appeal under 35 U.S.C. § 134(a) from
the Primary Examiner's final decision to reject claims 1-19. 2 We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.
I. BACKGROUND
The subject matter on appeal relates generally to hybrid memory
modules and to associated systems and methods (Spec. ,r,r 8-10, 17-24;
Drawings filed June 12, 2012, Figs. 1 and 2). Specifically, Figure 1 is
illustrative of the invention and is reproduced as follows:
1 The Appellants state that Hewlett Packard Enterprise Development LP
("HPED"), which is a wholly-owned affiliate of Hewlett Packard Enterprise,
is the real party in interest (Appeal Brief filed September 15, 2016 ("Appeal
Br."), 1-2). According to the Appellants, Enterprise DC Holdings LLC is
the general or managing partner of HPED (id. at 2). Furthermore, the
Appellants state that the "invention has been made with [U.S.] Government
support under Contract No. DE- SC0005026, awarded by The Department
of Energy" and that "[t]he Government has certain rights in the invention"
(Specification filed June 12, 2012 ("Spec."), ,r 1).
2 Appeal Br. 4--14; Reply Brief filed April 7, 2017 ("Reply Br."), 2-3; Final
Office Action entered February 1, 2016 ("Final Act."), 2-10; Examiner's
Answer entered February 10, 2017 ("Ans."), 2-9.
2
Appeal2017-007223
Application 13/494,761
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Figure 1 above shows a hybrid memory module including, inter alia, a
DRAM ( dynamic random-access-memory) bank 102 that communicates
with a memory buffer 106 through bus 180 and an NVM (non-volatile
memory) bank 104 that communicates with the memory buffer 106 through
a bus 182 (Spec. ,r,r 2, 3, 14). As shown in Figure 2 (not reproduced here), a
memory controller is in communication with the memory buffer through a
bus to migrate data between various memory devices in the memory module
(Spec. ,r 17).
Representative claim 1 is reproduced from the Claims Appendix to the
Appeal Brief, as follows:
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Appeal2017-007223
Application 13/494,761
1. A hybrid memory module comprising:
at least two heterogeneous memory devices; and
a memory buffer in communication with a memory
controller of a computer system through a memory channel, the
memory buff er being further in communication with the memory
devices to carry out migration of data, the migration of data
including reading data from any one of the memory devices and
writing the data to any other of the memory devices, wherein the
migration of data is carried out entirely by the memory buffer
without consuming any bandwidth of the memory channel.
(Appeal Br. 14 (emphasis added).)
II. REJECTIONS ON APPEAL
On appeal, the Examiner maintains two rejections under pre-AIA 35
U.S.C. § I03(a), as follows:
A. Claims 1-14 as unpatentable over Best3 in view of Donlin; 4 and
B. Claims 15-19 as unpatentable over Best in view ofNation. 5
(Ans. 2-9; Final Act. 2-10.)
III. DISCUSSION
Rejection A. As the Examiner observes (Ans. 2), the Appellants
argue claims 1-14 together-i.e., they focus their arguments on independent
claims 1 and 8 without providing any additional argument in support of the
separate patentability of any particular claim (Appeal Br. 4--11 ). Therefore,
pursuant to 37 C.F.R. § 4I.37(c)(l)(iv), we confine our discussion to claim
1, which we select as representative, and that discussion controls the
outcome for all claims rejected on this ground.
3 US 2010/0110748 Al, published May 6, 2010.
4 US 7,380,035 Bl, published May 27, 2008.
5 US 2009/0313416 Al, published December 17, 2009.
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Appeal2017-007223
Application 13/494,761
The Examiner finds that Best describes a hybrid memory module
having every limitation recited in claim 1 except the reference "is silent with
regard to operat[ing] without consuming any bandwidth [ of the memory
channel]" (Final Act. 3). The Examiner finds, however, that Donlin, which
is a reference in the same field of endeavor, discloses operating without
consuming any bandwidth of a memory channel (id.). Based on these
findings, the Examiner concludes that a person having ordinary skill in the
art would have combined Best and Donlin in the manner claimed by the
Appellants (id. at 3--4).
The Appellants' main argument focuses on Best's Figure 3, which is
reproduced as follows:
FIG. 3
f '''''':::--::::~'''''''''''1
I .Array Die
I ill
140
NV Memory
Array me
:1PJ
Best's Figure 3 above depicts a data control/steering circuit 150 that is
interconnected with a hybrid, composite memory device having a volatile
DRAM memory array die 101 and a non-volatile NV flash memory array die
103 (Best ,r,r 6, 7, 17, and 21).
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Appeal2017-007223
Application 13/494,761
Specifically, the Appellants contend that Best does not teach or
suggest "migration of data is carried out entirely by the memory buffer," as
recited in claim 1, because "[t]he only buffers disclosed in Best are the
interface buffers 159 and 161 illustrated in Figure 3" and these interface
buffers function under the control of the data control circuit 151 (Appeal Br.
8-9 (bolding added)). Regarding Donlin, the Appellants argue that Donlin
does not relate to a memory device and, therefore, fails to provide any
teaching or suggestion that would have led a person having ordinary skill in
the art to modify Best's hybrid memory module in the manner as recited in
claim 1 (id. at 9-11 ).
In response to the Appellants' arguments, the Examiner explains that
although Best is "silent" as to the disputed claim limitations, Best anticipates
claim 1 because it teaches data transfer between the volatile and non-volatile
memory dies through path 171 without using what would correspond to the
Appellants' specified "memory channel" (Ans. 7-9 (relying on Best Figure 3
and ,r 21) ). The Examiner states that, because Best anticipates, reliance on
Donlin is unnecessary (Ans. 8-9).
The Appellants counter that "any transfer of data between the DRAM
and NV memories in Best requires use of the memory controller 151, as well
as bandwidth of the channel between the interface buffers 159, 161" (Reply
Br. 2-3 (bolding added)). The Appellants urge that, therefore, "Best fails to
teach or suggest 'wherein the migration of data is carried out entirely by the
memory buffer without consuming any bandwidth of the memory channel,'
as recited in [claim 1]" (id. at 3).
The Appellants' arguments fail to identify any reversible error in the
Examiner's rejection. In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011).
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Appeal2017-007223
Application 13/494,761
"A patent applicant is free to recite features of an apparatus either
structurally or functionally ... Yet, choosing to define an element
functionally, i.e., by what it does, carries with it a risk." In re Schreiber, 128
F.3d 1473, 1478 (Fed. Cir. 1997). The risk in functional claiming is that it
may be insufficient to give patentable weight to the claim when the
structures are otherwise indistinguishable. Id.
Applying this principle, we discern no error in the Examiner's
findings. Best teaches that the data control/steering circuit 150 includes a
data control circuit 151, a multiplexer 153, primary volatile and non-volatile
data paths 142 and 144, secondary volatile and non-volatile data paths 155
and 157, a volatile-storage-die interface buffer 159, a non-volatile-storage
die interface buffer 161, and an inter-die data path 171 (Best ,r 21 ). 6 As one
embodiment, Best teaches that in a memory write operation, data received
via a shared internal data path 140 is passed via the multiplexer 153 to one
of the secondary data paths 155, 157 according to the memory access target
via data paths 142, 144 (id. ,r,r 21, 22). Conversely, in a data read operation,
the data control circuit 151 asserts a synchronizing signal to the DRAM
control circuit 129 or non-volatile-die control circuit 137 to initiate assertion
of row address strobe (RAS) and column-address-strobe (CAS) signals 146
or read-enable signal (REN) to enable data to be read out of the DRAM or
non-volatile-storage die via data path 142 or 144, to the DRAM interface
buffer 159 or non-volatile-die interface buffer 161, and thereafter, the data is
read out of the DRAM interface buffer 159 or non-volatile-die interface
6 Referring to Best's Figure IA, the Examiner finds that data bus (bi-
directional data interface) 104 corresponds to the Appellants' "memory
channel," which is not specifically identified in their Drawings and
Specification (Ans. 4). The Appellants do not contest that finding.
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Appeal2017-007223
Application 13/494,761
buffer 161 onto the secondary data path 155 or 157, and then passed through
multiplexer 153 onto shared data path 140 (id.).
But as the Examiner correctly finds (Ans. 7), Best teaches that
"[a]lternatively, the data read out of the volatile storage die may be
transferred from the volatile-die interface buffer 159 to the non-volatile-die
interface buffer 161 via the inter-die data path 171" (id. ,r 21 ). In addition,
Best teaches "[ d]ata may similarly be transferred in the opposite direction
from the non-volatile die 101 to the volatile storage die 103 via inter-die data
path 171 (i.e., transferring the data from buffer 161 to buffer 159)" (id.). As
the Examiner finds (Ans. 8), this alternative mode of data transfer does not
involve the use of elements that would be considered as defining the
"memory channel" recited in claim 1. Indeed, the Appellants do not
specifically dispute these findings (Reply Br. 2-3). Instead, they argue that
"any transfer of data between the DRAM and NV memories in Best requires
use of the memory controller 151, as well as bandwidth of the channel
between the interface buffers 159, 161" (id. at 3).
Best's alternative embodiment, however, is patentably
indistinguishable from the Appellants' "structures" described for the hybrid
memory modules shown in their Figure 2, which the Appellants
acknowledge is encompassed by claim 1 (Appeal Br. 2). In this regard, the
Appellants specifically cite to paragraph 20, which relates to Figure 2, as
supporting the limitation "wherein the migration of data is carried out
entirely by the memory buffer without consuming any bandwidth of the
memory channel" (id. at 3). In the Appellants' Figure 2, a memory
controller 202 issues a "migrate data" command to instruct one of the
memory buffers (e.g., buffer 214) to migrate data between the memory
devices (DRAM 210 and NVM 212) within a module, and then data
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Application 13/494,761
migration is carried out entirely by the memory buffer, which avoids
consuming memory channel bandwidth (Spec. ,r 20). 7 The box labeled
"Buffer" in the Appellants' Figure 2 ( as well as "Memory Buffer" in Figure
1) is generic to any buffering structures and, therefore, claim 1 's "memory
buffer" reads on Best's DRAM and NV interface buffers as shown in Best's
Figure 3. Accordingly, we do not find the Appellants' arguments in the
Reply Brief at pages 2-3 to be persuasive in identifying any reversible error.
For these reasons and those given by the Examiner, we uphold the
Examiner's rejection as maintained against claim 1.
Rejection B. The Appellants rely on the same arguments in support
of claim 1, adding only that "Nation fails to provide any teaching or
suggestion to cure" the alleged deficiencies in the Examiner's reliance on
Best (Appeal Br. 12-13). Because we do not find the Appellants' arguments
against Best persuasive, we uphold Rejection B for the same reasons
discussed above for Rejection A.
IV. SUMMARY
Rejections A and Bare sustained. Therefore, the Examiner's final
decision to reject claims 1-19 is affirmed.
7 Significantly, the Specification also informs one skilled in the relevant art
that "the memory controller [in Figure 2] uses timing information of the data
migration to optimally use memory channel bandwidth" (Spec. ,r 20
( emphasis added)), which indicates that the disputed claim limitation ("the
migration of data is carried out entirely by the memory buffer without
consuming any bandwidth of the memory channel") does not completely
eliminate using memory channel bandwidth. Cf Oatey Co. v. JPS Corp.,
514 F.3d 1271, 1276-77 (Fed. Cir. 2008) (claims are not normally
interpreted to exclude embodiments disclosed in the specification absent a
clear disclaimer).
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Application 13/494,761
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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