Ex Parte Burr et alDownload PDFPatent Trial and Appeal BoardMar 23, 201713103952 (P.T.A.B. Mar. 23, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. TRAN-P126C1 1242 EXAMINER RAHMAN, FAHMIDA ART UNIT PAPER NUMBER 2116 MAIL DATE DELIVERY MODE 13/103,952 05/09/2011 45590 7590 03/24/2017 Patent Prosecution Dept. MURABITO, HAO & BARNES LLP TWO NORTH MARKET STREET THIRD FLOOR SAN JOSE, CA 95113 James B. Burr 03/24/2017 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JAMES B. BURR, ANDREW READ, and TOM STEWART Appeal 2016-004115 Application 13/103,952 Technology Center 2100 Before BRUCE R. WINSOR, KEVIN C. TROCK, and AARON W. MOORE, Administrative Patent Judges. MOORE, Administrative Patent Judge. DECISION ON APPEAL Appeal 2016-004115 Application 13/103,952 STATEMENT OF THE CASE Appellants1 appeal under 35 U.S.C. § 134(a) from a Non-Final Rejection of claims 1—21, which are all of the pending claims. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. THE INVENTION The application is directed to “[a] method and system of adaptive power control” in which “[cjharacteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit.” (Abstract.) Claim 1, reproduced below, is representative of the subject matter on appeal: 1. A method comprising: accessing a measurement of a frequency-voltage character istic of an integrated circuit, wherein the frequency-voltage char acteristic is stored external to a substrate of the integrated circuit; and operating the integrated circuit at a voltage and frequency specified by the frequency-voltage characteristic. THE REFERENCES The prior art relied upon by the Examiner in rejecting the claims on appeal is: Soerensen et al. US 2003/0071657 A1 Apr. 17, 2003 Lawrence US 2004/0025061 Al Feb. 5,2004 Casto et al. US 6,791,157 B1 Sept. 14, 2004 1 Appellants identify Intellectual Venture Funding LLC as the real party in interest. (See App. Br. 1.) 2 Appeal 2016-004115 Application 13/103,952 Ando US 6,792,379 B2 Sept. 14,2004 Tobias et al. US 7,188,261 B1 Mar. 6, 2007 THE REJECTIONS 1. Claims 1—21 were provisionally rejected on the ground of nonstatutory obviousness-type double patenting as unpatentable over claims 1—20 of US Serial No. 13/118,762. (See Non-Final Act. 4—5.) 2. Claims 1—21 stand rejected on the ground of nonstatutory obviousness-type double patenting as unpatentable over claims 1—42 of US 7,953,990. (See Non-Final Act. 5-6.) 3. Claims 1—21 stand rejected on the ground of nonstatutory obviousness-type double patenting as unpatentable over claims 1—36 of US 7,941,675. (See Non-Final Act. 7-8.) 4. Claims 1—6, 8—14, 17, and 19-21 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Ando and Tobias. (See Non-Final Act. 8-14.) 5. Claim 7 stands rejected under 35 U.S.C. § 103(a) as unpatentable over Ando, Tobias, and Casto. (See Non-Final Act. 14.) 6. Claim 15 stands rejected under 35 U.S.C. § 103(a) as unpatentable over Ando, Tobias, and Soerensen. (See Non-Final Act. 14— 15.) 7. Claim 18 stands rejected under 35 U.S.C. § 103(a) as unpatentable over Ando, Tobias, and Fawrence. (See Non-Final Act. 15- lb.) 3 Appeal 2016-004115 Application 13/103,952 ANALYSIS Double Patenting As Appellants present no arguments regarding the double patenting rejections (see App. Br. 4), we summarily sustain the rejections of claims 1— 21 for obviousness-type double patenting over claims 1—42 of US 7,953,990 and claims 1—36 of US 7,941,675. The provisional double patenting rejection is moot, as US Serial No. 13/118,762 has been abandoned. Prior Art Arguments Appellants offer a series of arguments for the patentability of various claims, which we will refer to by their associated headings in the Appeal Brief, A—X, and address grouped by the nature of the contention.2 Teaching Away Appellants contend the obviousness rejections of various claims are improper because the prior art “teaches away” from the combinations made by the Examiner. These contentions are summarized in the following table: Argument Claim Contention A 1 “Ando teaches awav from the claimed limitations of a ‘frequencv-voltage characteristic is stored external to a substrate of the integrated circuit.’” (Ann. Br. 12.) D 1 “Tobias states a preference for sample data, in contrast to individual data.” (Id. at 20.) 2 Arguments G, I, M, and O-Q are non-substantive, asserting only that the claims are patentable by virtue of their dependence on other claims, and will not be further discussed herein. 4 Appeal 2016-004115 Application 13/103,952 H 4 “Ando’s preference for testing prior to packaging, would [have led one] to perform testing prior to packaging, as preferentially taught by Ando, and led away” from testing after packaging. (Id. at 30.) J 8 “Tobias states a preference for sample data, in contrast to specific characteristics.” (Id. at 33.) K 8 A person of ordinary skill “would be led to determine an operating frequency dependent on operating voltage, as taught by Tobias, and away from . . . ‘determining, independent of operating voltage, a desirable operating frequency for a processor.’” (Id. at 36.) N 13 “As Tobias teaches ‘plural’ data sets . . . Tobias fails to teach or suggest ‘only one set of the characteristics’” and ‘Ta]ccordinglv, Tobias teaches away from these instant claimed embodiments.” (Id. at 41.) R 7 “[T]he plain language of Casto teaches that fuses 207 do not contain data that relates to both frequency and voltage parameters simultaneously” and ‘Talccordinglv, Casto teaches away from the claimed limitations of a ‘frequency-voltage characteristic is stored external to a substrate of the integrated circuit.’” (Id. at 46.) S 7 “Casto suggests storing a single frequency-voltage point of operation, and teaches away from the claimed limitations of a ‘frequency-voltage characteristic.’” (Id. at 48.) T 15 “Soerensen teaches away from the claimed limitations of ‘a frequency-voltage relationship that is . . . stored externally to the processor’” because “Soerensen teaches memory for storing voltage information on the same integrated circuit.” (Id. at 50.) 5 Appeal 2016-004115 Application 13/103,952 V 18 “Lawrence teaches awav from the claimed limitations of ‘a frequency-voltage relationship that is specific to the processor’” because “Lawrence teaches use of data that is obtained by testing many systems.” (Id. at 54.) In connection with each of these contentions, Appellants, quoting In re Haruna, 249 F.3d 1327, 1335 (Fed. Cir. 2001), assert that “[a] reference may be said to teach away when a person of ordinary skill, upon reading the reference . . . would be led in a direction divergent from the path that was taken by the applicant.” (E.g., App. Br. 13.) More recently, however, our reviewing Court has clarified that “[a] reference does not teach away ... if it merely expresses a general preference for an alternative invention but does not criticize, discredit, or otherwise discourage investigation into the invention claimed.” Galderma Labs., L.P. v. Tolmar, Inc., 737 F.3d 731, 738 (Fed. Cir. 2013) (quoting DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 567 F.3d 1314, 1327 (Fed. Cir. 2009)); see In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004). Thus, “mere disclosure of alternative designs does not teach away.” Id. We find Appellants’ arguments listed above unpersuasive because we conclude that, in each case, the prior art was simply teaching a different way, not teaching away. Change Principle of Operation, Render Unsatisfactory for Intended Purpose, and No Expectation of Success Regarding claim 1, Appellants argue the combination of Ando and Tobias changes the principle of Ando because Ando teaches storage of information on the die of the IC, while in the combination the information is stored external to the substrate of the IC. (App. Br. 16 (Argument B).) We do not agree that the combination would work an impermissible change in 6 Appeal 2016-004115 Application 13/103,952 Ando’s “principle of operation.” Ando is directed to a system (similar to that described in Appellants’ Specification) in which chips are tested, optimal frequency-voltage values are determined, and the values are stored and used “to reduce the power consumed by a chip, maximize its operating speed, reduce its operating voltage, or achieve a balance of high speed and low power consumption.” (See Ando 2:18—37.) Storing the information outside the chip would be a modification of one aspect of Ando, but Appellants have not explained how, nor do we see why, this would affect, much less impermissibly alter, Ando’s core principle of operation. Cf. In re Mouttet, 686 F.3d 1322, 1331—32 (Fed. Cir. 2012) (sustaining “the Board’s determination that the difference in the circuitry—electrical versus optical— does not affect the overall principle of operation of a programmable arithmetic processor”); In re Umbarger, 407 F.2d 425, 430-31 (CCPA 1969) (finding In re Ratti, 270 F.2d 810, 813 (1959), cited by Appellants, inapplicable where the modified apparatus will operate “on the same principles as before”). For similar reasons, we do not agree that storing the data outside the chip would “would render the prior art invention being modified unsatisfactory for its intended purpose.” (App. Br. 19 (Argument C).) As explained above, the “intended purpose” of Ando is to collect the data and store it so that it may be used to maximize or optimize performance. Appellants do not explain how locating the data outside the chip would render Ando’s system unsatisfactory for that purpose. We also are not persuaded of error by Appellants’ argument that “there is no expectation of success for the proposed modification of Ando in view of Tobias.” (App. Br. 22 (Argument E).) Appellants specifically 7 Appeal 2016-004115 Application 13/103,952 assert that the “modification raises the substantial engineering challenge of how to link one specific IC’s frequency-voltage characteristic with that specific IC.” (Id. at 23.) The Examiner explains, however, that Tobias describes how “the off-die storage location may be performed through a variety of well-known techniques”3 and we agree that because “techniques of providing off-die storage of a chip are well known, the prior art provides a sufficient basis for a reasonable expectation of success.” (Ans. 22.) We also observe that Appellants’ Specification does not detail “how to link one specific IC’s frequency-voltage characteristic with that of specific IC,” suggesting that, assuming Appellants complied with their obligations under Section 112, such information would have been known to one of skill in the art at the time the priority application was filed. Lack of Motivation to Combine Quoting In re Vaeck, 947 F.2d 488, 493 (Fed. Cir. 1991), Appellants assert that “a proper analysis under § 103 requires, inter alia, consideration of. . . whether the prior art would have suggested to those of ordinary skill in the art that they should make the claimed composition or device, or carry out the claimed process.” (E.g., App. Br. 25.) Appellants continue, without citation, that “[rjegardless of the type of disclosure, the prior art must provide some motivation or suggestion to one of ordinary skill in the art to make the claimed invention in order to support a conclusion of 3 See Tobias 6:10—18 (“Schmoo Plot 602 [a graph of voltage and frequency of the operational range of the processor] can be included on the silicon of a processor (CPU) 604, on the package of CPU 604 or externally coupled to CPU 604 through a variety of well known techniques such as laser cutting, fusible devices, non-volatile storage and the like.”). 8 Appeal 2016-004115 Application 13/103,952 obviousness.” (Id.) Appellants’ formulation of the law, at least to the extent it would require the motivation to be found in the prior art itself, is not consistent with current jurisprudence, in which “[i]t is well settled that, even where references do not explicitly convey a motivation to combine, ‘any need or problem known in the field of endeavor at the time of invention and addressed by the patent can provide a reason for combining the elements in the manner claimed.”’ ABTSys., LLC v. Emerson Elec. Co., 797 F.3d 1350, 1360 (Fed. Cir. 2015) (quoting KSRInt’l Co. v. Teleflex Inc., 550 U.S. 398, 420 (2007)). Appellants challenge the motivation to combine Ando and Tobias (Arguments F & L); Ando, Tobias, and Soerensen (Argument U); and Ando, Tobias, and Lawrence (Argument W). For the reasons detailed below, we find Appellants’ contentions unpersuasive. As to claim 1, the Examiner finds “Ando does not explicitly teach . . . wherein the frequency-voltage characteristic is stored external to a substrate of the integrated circuit” but Tobias does, and that it would have been obvious to combine because “external storage saves chip space (i.e., chip real estate) and provide[s] more flexibility as external storage is easier to maintain and easier to program.” (Non-Final Act. 9.) Appellants’ Argument F is that “[tjhere is no teaching of record that such ‘external storage’ saves chip space, and the rejection fails to cite to any support for such allegations.” (App. Br. 25.) This is not persuasive of error because (a) it only addresses saving chip space, failing to contest the second part of the motivation (flexibility), and (b) we agree that moving the data off the chip would 9 Appeal 2016-004115 Application 13/103,952 necessarily save space on the chip, a point amply supported by the additional art cited by the Examiner in the Answer. (See Ans. 23.4) Regarding claim 8, the Examiner finds “Ando does not explicitly mention . . . accessing indication of voltage from storage external to a substrate of the processor,” but Tobias teaches that “characteristics are stored external to a substrate of the processor,” and that it would have been obvious to combine “so that additional processing steps need not be performed on CPU die,” because the “processor is simpler and space saved” and because “[t]he external storage can be easily reprogrammed and maintained.” (Non-Final Act. 10—11.) Appellants’Argument L is unpersuasive because it again addresses only part of the stated motivation (“so that additional processing steps need not be performed on [the] CPU die”) and because we agree that one of skill in art would have been motivated to make the combination at least to save space in the chip and take advantage of the identified benefits associated with external storage. In rejecting claim 15, the Examiner finds “Ando teaches the next clock frequency” but that “Ando, in view of Tobias does not explicitly mention . . . determination of frequency by examining [a] contemporaneous set of operations.” (Non-Final Act. 15.) The Examiner further finds that “Soerensen teaches determination of frequency by examining contemporaneous set of operations” and that it would have been obvious to 4 Although not necessary to our decision, we note that Appellants’ argument is also undercut by the Specification, which explains that “[mjicroprocessors typically have extremely limited amounts of or no non-volatile storage” in part because “a bit of non-volatile storage consumes valuable circuit area, more optimally used for microprocessor circuitry.” Spec. 26:10—20. 10 Appeal 2016-004115 Application 13/103,952 combine so as “to determine the clock frequency requirements by examining the contemporaneous set of operation since this provides optimized power savings.” (Id.) Appellants’ Argument U is that “[t]here is no teaching of record that ‘examining the contemporaneous set of operation[s]’ leads to ‘optimized’ power savings,” that “Soerensen does not suggest that its taught methods are ‘optimal,’” and that “both Ando and Tobias claim reduced power consumption due to their taught methods” so “there is no motivation and no rational underpinning for the proposed modification.” (App. Br. 52— 53.) We agree with the Examiner that Soerensen’s teaching that it would be beneficial to include dynamic (i.e., contemporaneous) adjustments in order to reduce (i.e., optimize) power consumption provides a sufficient reason to combine. Regarding the argument that Ando and Tobias also seek to improve power consumption, we see no reason why one would not seek to reduce or optimize the use of power in multiple ways. Regarding claim 18, the Examiner finds Tobias teaches “that the frequency-voltage characteristic is encoded within storage separate from processor” but “does not explicitly mention that the outside storage is an IC, although it is very much typical that the outside storage is an IC.” (Non- Final Act. 15.) The Examiner further finds that Lawrence teaches “that the frequency-voltage characteristic is encoded in an IC separate from the processor” and that one of ordinary skill would have been motivated use an IC separate from the processor “since this allows the flexibility of operating the processor with external v-f values.” (Id. at 15—16.) In the Answer, the Examiner explains that although “Ando’s chip has flexibility of reprogramming . . . this does not preclude one [of] ordinary skill to use other flexible means such as using external flash memory IC for other motivating 11 Appeal 2016-004115 Application 13/103,952 scenarios, such as bypassing the burden of the reprogramming the CPU die.” (Ans. 34.) We agree with the Examiner that it would have been obvious to one of skill in the art to use an IC, as taught in Lawrence, as the separate storage taught in Tobias. See KSR, 550 U.S. at 417 (“[I]f a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill.”). Element Missing from the Combination Argument X urges that the combination of Ando, Tobias, and Lawrence “fails to teach or suggest the claimed limitations of ‘wherein the relationship is stored in an integrated circuit that is separate from the processor.’” (App. Br. 59.) Specifically, Appellants argue that Lawrence does not teach memory “separate from the processor” because it describes how “the set of data may be loaded into flash memory coupled to the processor.” (Lawrence 118.) This argument is not persuasive because the Examiner relies on Lawrence only for the use of an “IC”; Tobias teaches “externally coupled,” which we agree is sufficient to teach or suggest “separate from the processor,” particularly given that in Tobias it can be “non-volatile storage and the like.” Conclusion Because Appellants do not contest the double patenting rejections and we are not persuaded of Examiner error by Appellants’ Arguments A—X, we sustain the rejections of claims 1—21. 12 Appeal 2016-004115 Application 13/103,952 DECISION The rejections of claims 1—21 are affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 13 Copy with citationCopy as parenthetical citation