Ex Parte Buonpane et al

Patent Trial and Appeal Board

Jun 28, 2016

12174566 (P.T.A.B. Jun. 28, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/174,566 07/16/2008
57299 7590 06/30/2016
Kathy Manke
A vago Technologies Limited
4380 Ziegler Road
Fort Collins, CO 80525
FIRST NAMED INVENTOR
Michael S. Buonpane
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
BUONPANE 2-13-3-13-5 8906
EXAMINER
BANSAL, GURTEJ
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
06/30/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
kathy.manke@broadcom.com
patent.info@broadcom.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL S. BUONP ANE, JAMES D. CHLIP ALA,
RICHARD P. MARTIN, RICHARD MUSCA VAGE, and
ERIC WILCOX
Appeal2014-007689
Application 12/174,5661
Technology Center 2100
Before THU A. DANG, LARRY J. HUME, and SCOTT B. HOW ARD,
Administrative Patent Judges.
HUME, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1---6, 8-13, 15-18, 20, and 21. Appellants have
previously canceled claims 7, 14, 19, and 22. We have jurisdiction under 35
U.S.C. § 6(b).
We AFFIRM.
1 According to Appellants, the real party in interest is Agere Systems, Inc.
Br. 3.
Appeal2014-007689
Application 12/174,566
STATEMENT OF THE CASE2
The Invention
Appellants' disclosed and claimed "invention is directed, in general, to
multiple chips, such as in multi-chip modules (MCMs) and, more
specifically, to off-chip memory associated with the multiple chips." Spec.
iT 1.
Exemplary Claims
Claims 1 and 8, reproduced below, are representative of the subject
matter on appeal (emphases added to contested limitations):
1. A multi-chip module including multiple logic
chips, comprising:
a first logic chip, wherein when a memory request is
generated by said first logic chip, a memory request interceptor
of said first logic chip determines if said first logic chip is
directly coupled to an off-chip shared memory space and, if
said off-chip shared memory space is not directly coupled to
said first logic chip, said memory request is transformed to a
shared memory request; and
a second logic chip, coupled to said first logic chip and
said off-chip shared memory space, including a memory
interface and a memory request interceptor configured to direct
said shared memory request originated at said first logic chip to
said shared memory space via said memory interface,
2 Our decision relies upon Appellants' Appeal Brief ("Br.," filed
Mar. 6, 2014); Examiner's Answer ("Ans.," mailed May 8, 2014); Final
Office Action ("Final Act.," mailed Oct. 4, 2013); and the original
Specification ("Spec.," filed July 16, 2008). We note Appellants did not file
a Reply Brief in response to the factual and legal findings in the Examiner's
Answer.
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Application 12/174,566
wherein a total number of off-chip shared memory spaces
coupled to said multi-chip module is fewer than a total number
of said multiple logic chips.
8. A method of accessing an off-chip shared memory
space of a printed circuit board, comprising:
generating a memory request at a first chip of said
printed circuit board;
determining if said first chip is directly coupled to an off-
chip shared memory space;
transforming said memory request to a shared memory
request when said first chip is not directly coupled to said off-
chip shared memory space; and
directing said shared memory request to said off-chip
shared memory space that is indirectly coupled to said first chip
via a second chip of said printed circuit board, wherein said
second chip is directly coupled to said off-chip shared memory
space through a memory interface of said second chip.
Prior Art
The Examiner relies upon the following prior art as evidence in
rejecting the claims on appeal:
Hady et al. ("Hady") US 2006/0112227 Al May 25, 2006
Pong US 2008/0082759 Al Apr. 3, 2008
Rejections on Appeal
RI. Claims 1---6, 16-18, and 20-21 stand rejected under 35 U.S.C.
§ 102(e) as being anticipated by Pong. Final Act. 2.
R2. Claims 8-15 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Hady. Final Act. 5.
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Application 12/174,566
CLAIM GROUPING
Based on Appellants' arguments (Br. 6-10), we decide the appeal of
anticipation Rejection RI of claims 1-6, 16-18, and 20-21 on the basis of
representative claim 1; and we decide the appeal of anticipation Rejection
R2 of claims 8-15 on the basis of representative claim 8.
Dependent claims that are not argued separately, stand or fall with the
respective independent claim from which they depend. 3
ISSUES AND ANALYSIS
In reaching this decision, we consider all evidence presented and all
arguments actually made by Appellants. We do not consider arguments that
Appellants could have made but chose not to make in the Brief, and we
deem any such arguments waived. 37 C.F.R. § 41.37(c)(l)(iv).
We disagree with Appellants' arguments with respect to claims 1---6,
8-13; 15-18; 20; and 21; and we incorporate herein and adopt as our own:
( 1) the findings and reasons set forth by the Examiner in the action from
which this appeal is taken, and (2) the reasons and rebuttals set forth in the
Examiner's Answer in response to Appellants' arguments. We incorporate
such findings, reasons, and rebuttals herein by reference unless otherwise
noted. However, we highlight and address specific findings and arguments
regarding claims 1 and 8 for emphasis as follows:
3 "Notwithstanding any other provision of this paragraph, the failure of
appellant to separately argue claims which appellant has grouped together
shall constitute a waiver of any argument that the Board must consider the
patentability of any grouped claim separately." 37 C.F.R. § 41.37(c)(l)(iv).
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Application 12/174,566
1. § 102(e) Rejection RI of Claims 1---6, 16-18, and 20-21
Issue 1
Appellants argue (Br. 6-7) the Examiner's rejection of claim 1 under
35 U.S.C. § 102(e) as being anticipated by Pong is in error. These
contentions present us with the following issue:
Did the Examiner err in finding the cited prior art discloses "[a] multi-
chip module including multiple logic chips," "wherein a total number of off-
chip shared memory spaces coupled to said multi-chip module is fewer than
a total number of said multiple logic chips," as recited in claim 1?
Analysis
Appellants contend the Examiner erred because, as allegedly required
by claim 1, the cited prior art does not disclose "an off-chip memory space
for each logic chip," and "the invention as presently claimed takes advantage
of fewer off-chip memories in order to save PCB space." Br. 6 (citing Spec.
i-fi-13--4). Appellants further contend, "Pong, in contrast, is not concerned
with PCB space, as Pong is directed towards management of a global
address space in memory systems. (See, e.g., paragraph [0003] of Pong.)
Pong uses the above-described 'traditional off-chip memory approach.'" Id.
In addition, Appellants contend Pong Figure 3A "explicitly teaches
that each processor 1 OOa-1 OOn has its own external memory (EM) 106a-
106j. Thus, Pong explicitly teaches that there are a same number of memory
and logic chips," such that Pong does not teach the contested limitation of
claim 1. Br. 7.
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Application 12/174,566
As an initial matter of claim construction, we give the claim its
broadest reasonable interpretation consistent with the Specification. See In
re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). "In the patentability
context, claims are to be given their broadest reasonable interpretations ...
limitations are not to be read into the claims from the specification." In re
Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993) (citations omitted).
The Examiner construes the recited '"a total number of off-chip shared
memory spaces' to be the respective memory spaces of [system on chip]
SOC's 100b-100n which hold a copy of the data," (Ans. 3), which "are 'off-
chip' with respect to SOC 1 OOj and further, the total number is fewer than 'a
total number of said multiple logic chips' since[] a total number of logic
chips corresponds to 1 OOa-1 OOn." Ans. 4.
Given the breadth of the contested claim limitation, 4 the Examiner sets
forth a "second interpretation to illustrate that the language used by
Appellant within this limitation appears to be broad enough to cover any
number of circumstances where a set of memory spaces are less than a set of
logic chips." Id.
We note Appellants have not cited to a definition of "off-chip shared
memory spaces" in the Specification that would preclude the Examiner's
broader reading. 5 We further note Appellants do not file a Reply Brief to
4 The Examiner states "the claims merely recite 'a total number of off-chip
memory spaces' and 'a total number of said multiple logic chips'." Ans. 4.
5 Any special meaning assigned to a term "must be sufficiently clear in the
specification that any departure from common usage would be so understood
by a person of experience in the field of the invention." Multiform
Desiccants Inc. v. Medzam Ltd., 133 F.3d 1473, 1477 (Fed. Cir. 1998); see
also Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F.3d 1379, 1381
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Application 12/174,566
rebut the Examiner's claim construction, factual findings, or finding of
anticipation of claim 1.
Based upon the findings and conclusions above, on this record, we are
not persuaded of error in the Examiner's reliance on the disclosure of the
cited prior art to disclose the contested limitation of claim 1, nor do we find
error in the Examiner's resulting legal finding of anticipation. Therefore, we
sustain the Examiner's anticipation rejection of independent claim 1, and
grouped claims 2-6, 16-18, and 20-21 which fall therewith. See Claim
Grouping, supra.
2. § 102(b) Rejection R2 of Claims 8-15
Issue 2
Appellants argue (Br. 8-10) the Examiner's rejection of claim 8 under
35 U.S.C. § 102(b) as being anticipated by Hady is in error. These
contentions present us with the following issue:
Did the Examiner err in finding the cited prior art discloses "[a]
method of accessing an off-chip shared memory space of a printed circuit
board," that includes, inter alia, the step of "determining if said first chip is
directly coupled to an off-chip shared memory space," as recited in claim 8?
Analysis
Appellants contend, "independent Claim 8 does not recite determining
if a memory is indirectly coupled. Instead ... Claim 8 recites determining if
(Fed. Cir. 2008) ("A patentee may act as its own lexicographer and assign to
a term a unique definition that is different from its ordinary and customary
meaning; however, a patentee must clearly express that intent in the written
description.").
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Application 12/174,566
a memory is directly coupled to off-chip memory." Br. 8. In particular,
Appellants disagree with the Examiner "that a cache miss is a determination
of whether or not a memory is directly coupled to a (first) logic chip." Br. 9.
In addition, Appellants argue, "[t]he cited portions of Hady teach that the
off-chip shared memory space (shared cache 18 or main memory 72) is
always present. As such, a determination is not ever needed in Hady of
whether there is an off-chip shared memory space or not." Id.
In response, the Examiner broadly but reasonably construes "the
location which stores the 'requested data' to be the off-chip shared memory
space." Ans. 6. Further:
[I]f the data is not in the shared cache, the data is stored in an
off-chip shared memory space. The step of determining that the
memory space is directly coupled occurs during the detection of
the cache miss. When a miss occurs there has been a
determination that the first chip is not directly coupled and must
send the request on to the bridge. However, when there is a
cache hit, it is determined that the first chip is directly coupled.
Therefore the cited passage teaches determining if the CPU2
core is directly coupled to the requested data by the use of a
hit/miss or whether the request must be sent to the bridge to
access the data.
Id. The Examiner clarifies his interpretation of an "off-chip memory space"
by pointing out the memory space (i.e. location) of the requested data is
construed "to be the 'off chip memory space', not the entire shared cache 18
or entire main memory 72. The memory space holding the requested data is
merely a small part of either the cache or main memory." Ans. 7. Thus, if
the memory space with the requested data is within the cache, then the
memory space is directly coupled, and otherwise the memory is not directly
coupled. Id.
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We note Appellants do not file a Reply Brief to rebut the Examiner's
claim construction, factual findings, or finding of anticipation of claim 8.
Based upon the findings above, on this record, we are not persuaded
of error in the Examiner's reliance on the disclosure of the cited prior art to
disclose the contested limitation of claim 8, nor do we find error in the
Examiner's resulting legal finding of anticipation. Therefore, we sustain the
Examiner's anticipation rejection of independent claim 8, and grouped
claims 8-15 which fall therewith. See Claim Grouping, supra.
CONCLUSIONS
The Examiner did not err with respect to anticipation Rejections RI
and R2 of claims 1---6, 8-13, 15-18, 20, and 21under35 U.S.C. §§ 102(e)
and 102(b) over the cited prior art of record, and we sustain the rejections.
DECISION
We affirm the Examiner's decision rejecting claims 1--6; 8-13; 15-18;
20, and 21.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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