Ex Parte BULZACCHELLI et al

Patent Trials and Appeals BoardMar 29, 2019

14717540 - (D) (P.T.A.B. Mar. 29, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/717,540 05/20/2015 49267 7590 Tutunjian & Bitetto, P.C. 401 Broadhollow Road Suite 402 Melville, NY 11747 04/02/2019 FIRST NAMED INVENTOR JOHN F. BULZACCHELLI UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. Y0R920090007US5(289DIVII) 7894 EXAMINER TRA, ANH QUAN ART UNIT PAPER NUMBER 2842 NOTIFICATION DATE DELIVERY MODE 04/02/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing@tb-iplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JOHN F. BULZACCHELLI and BYUNGSUB KIM Appeal2018-004381 Application 14/717 ,540 Technology Center 2800 Before ROMULO H. DELMENDO, RAEL YNN P. GUEST, and JAMES C. HOUSEL, Administrative Patent Judges. DELMENDO, Administrative Patent Judge. DECISION ON APPEAL The Applicant ("Appellant") 1 appeals under 35 U.S.C. Â§ 134(a) from the Primary Examiner's final decision to reject claims 1, 2, and 4--11. 2 We have jurisdiction under 35 U.S.C. Â§ 6(b). We affirm. 1 The Appellant is the Applicant, "INTERNATIONAL BUSINESS MACHINES CORPORATION" (Application Data Sheet filed May 20, 2015, 5), which is also listed as the real party in interest (Appeal Brief filed December 12, 2017("Appeal Br."), 3). 2 Appeal Br. 7-13; Reply Brief filed March 21, 2018 ("Reply Br."), 2-5; Final Office Action entered June 22, 2017 ("Final Act."), 2-5; Notice of Panel Decision from Pre-Appeal Brief Review entered November 13, 2017; Examiner's Answer entered January 29, 2018 ("Ans."), 2-6. Appeal 2018-004381 Application 14/717 ,540 I. BACKGROUND The subject matter on appeal relates to a double regenerating latch that includes two cascaded differential regenerating latches to achieve improved speed and sensitivity (Specification filed May 20, 2015 ("Spec."), ,r,r 12, 53, 57; Drawing filed August 30, 2016, Fig. 12; Drawings filed May 20, 2015, Figs. 8, 10, 11). Representative claim 1 is reproduced from the Claims Appendix to the Appeal Brief, as follows: 1. A double regenerating latch, comprising: two cascaded differential regenerating latch stages to achieve improved speed and sensitivity in a decision feedback equalizer (DFE); the stages including: a first stage comprising first input transistors and mirrored switch transistors of a first type, cross-coupled load transistors and reset transistors of a second type, wherein the mirrored switch transistors are disposed between the first input transistors and first stage outputs, and a second stage consisting of second input transistors of the second type and cross-coupled load transistors of the first type, such that when the first stage is in an opaque state the reset transistors precharge outputs of the first stage to a power supply voltage, the second input transistors of the second stage are shut off to retain outputs at levels indicative of a previous stored bit, when the first stage is activated, the cross-coupled load transistors of the first stage and of the second type begin to regenerate an input signal and at a same time, an output common- mode of the first stage falls to tum on the second input transistors of the second stage, and the second stage is switched after the output of the first stage achieves a threshold signal level to provide additional regenerative gain. (Appeal Br. 14.) 2 Appeal 2018-004381 Application 14/717 ,540 II. REJECTIONS ON APPEAL On appeal, the Examiner maintains rejections under pre-AIA 35 U.S.C. Â§ I03(a) of: (A) claims 1, 6, and 7 as unpatentable over Yamaguchi, 3 Kuo, 4 and Mohan; 5 and (B) claims 1, 2, and 4--11 6 as unpatentable over Dickson,7 Yamaguchi, Kuo, and Mohan (Ans. 2; Final Act. 2; Non-Final Office Action entered January 31, 2017 ("Non-Final Act."), 2--4)). III. DISCUSSION The Appellant does not provide any separate arguments against Rejection A (Appeal Br. 8-13), but instead, appears to be relying on the arguments and evidence offered against Rejection B, as both rejections rely on common prior art references and reasoning (Final Act. 2-5; Non-Final Act. 2--4). In addition, the Appellant does not argue any claim separately within the meaning of 37 C.F.R. Â§ 4I.37(c)(l)(iv). Therefore, we confine our discussion to claim 1, which we select as representative pursuant to the same rule. Claims 2 and 4--11 stand or fall with claim 1. The Examiner finds that Dickson, Yamaguchi, Kuo, and Mohan teach various elements recited in claim 1 and concludes from these findings that a 3 US 5,134,319, issued July 28, 1992. 4 US 2007/0194830 Al, published August 23, 2007. 5 US 7,800,411 Bl, issued September 21, 2010. 6 The statement of the rejection lists claims 1-7 as rejected, but the discussion makes clear that claims 1, 2, and 4--11 are rejected (Final Act. 2- 5). 7 Timothy 0. Dickson et al., "A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer with Current-Integrating Summers in 45-nm SOI CMOS Technology," IEEE Symposium of VLSI Circuits Digest of Technical Papers 58-59 (2008). 3 Appeal 2018-004381 Application 14/717 ,540 person having ordinary skill in the art would have combined these references in the manner claimed (Final Act. 2--4). Specifically, the Examiner concludes that a person having ordinary skill in the art would have combined Yamaguchi with: Kuo for the purpose of achieving a desired output slew rate (id. at 2-3); further with Mohan for the purpose of amplifying/buffering the outputs of the comparator (id. at 3); and further with Dickson for the purpose of reducing noise (id. at 3--4). The Appellant does not dispute the Examiner's factual findings concerning the scope and content of each prior art reference (Appeal Br. 9- 13). Nor does the Appellant contest the Examiner's articulated reasons for combining the references in the manner claimed (id.). Rather, the Appellant argues that evidence of unexpected results has been ignored and not given proper weight (id. at 10-12). According to the Appellant, "in view of the objective evidence, the combination of Dickson, Yamaguchi, Kuo, and Mohan fails to disclose or suggest two cascaded differential regenerating latch stages to achieve improved speed and sensitivity in a decision feedback equalizer [DFE]" (id. at 12). The Appellant's arguments fail to identify any reversible error in the Examiner's rejections. In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011). Because we discern no error in the Examiner's position on appeal (Ans. 2- 6), we adopt the Examiner's findings, conclusions, and rebuttal to the Appellant's arguments as our own. We add the following for emphasis. Although the Appellant focuses primarily on secondary considerations, the Appellant also appears to be arguing that obviousness cannot be established unless the prior art references are combined for the same reasons as the Inventors (Appeal Br. 12). That is incorrect. "Under 4 Appeal 2018-004381 Application 14/717 ,540 the correct analysis, any need or problem known in the field of endeavor ... can provide a reason for combining the elements in the manner claimed." KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 420 (2007). As our reviewing court has explained, the motivation or reason to combine the references in the manner claimed need not be identical to that of the Inventors. In re Kemps, 97 F.3d 1427, 1430 (Fed. Cir. 1996). In support of unexpected results, the Appellant relies on the results shown in Table 1 (Spec. ,r 58) and Figure 13 (Drawings filed May 20, 2015, Fig. 13) (Appeal Br. 10). Table 1 provides a comparison, in terms of horizontal eye opening (BER (bit error rate)