Ex Parte Bu et al

Patent Trial and Appeal Board

Jan 14, 2013

10810905 (P.T.A.B. Jan. 14, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte HAOWEN BU, BRIAN HORNUNG, P.R. CHIDAMBARAM,
AMITABH JAIN, RAJESH KHAMANKAR, NANDU MAHALINGAM,
and SRINIVASAN CHAKRAVARTHI

___________

Appeal 2010-008107
Application 10/810,905
Technology Center 2800
____________

Before MAHSHID D. SAADAT, CARLA M. KRIVAK, and
GEORGIANNA W. BRADEN, Administrative Patent Judges.

BRADEN, Administrative Patent Judge.

DECISION ON APPEAL

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This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-10 and 19-20. Claims 11-18 have been withdrawn from
consideration. We have jurisdiction under 35 U.S.C. § 6(b). We affirm.

STATEMENT OF THE CASE
Appellants’ invention relates to methods for forming complementary
metal oxide semiconductor (CMOS) transistors. (Abstract.)
Claim 1 is exemplary, with disputed limitation in italics:
1. A method for fabricating a CMOS transistor structure,
comprising the steps of:
providing a semiconductor substrate having a P-type
dopant region to support an N-channel transistor of the CMOS
transistor structure and an N-type dopant region to support a P-
channel transistor of the CMOS transistor structure, each of the
N-type dopant and P-type dopant regions having an overlying
gate stack including a conductive gate structure and a dielectric
gate structure;
forming lightly-doped extension regions in the
semiconductor substrate adjacent each gate stack;
depositing a layer of insulating material in contact with a
total exposed surface of the lightly-doped extension regions;
forming an interfacial layer of nitrogen below the layer
of insulating material and within the total exposed surface of
the lightly-doped extension regions;
forming at least one sidewall layer coupled to the layer of
insulating material;
forming source and drain regions in the semiconductor
substrate adjacent to each of the gate stacks;
forming a capping layer of contiguous silicon nitride over
the semiconductor substrate;
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annealing, after the formation of the capping layer and
with the capping layer in place, the extension regions and the
source and drain regions; and
removing all of the capping layer after the annealing.

REJECTIONS
Claim 1 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ahmad (US 6,037,639) in view of Chen (US
2005/0136583 A1).
Claims 2-10 and 19-20 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Ahmad in view of Chen, and Wieczorek (US
2004/0061228 A1).

ANALYSIS

The Examiner found that the grown layers of SiO2 (items 130 and 136
in Ahmad Fig. 3) correspond to the limitation “depositing a layer of
insulating material in contact with a total exposed surface of the lightly-
doped extension regions.” (Ans. 4-5). We agree with the Examiner.
Appellants first contend that element 118 of Ahmad’s Figure 2 “is the
amorphous ion implant area (column 3 lines 48-67), but not an implantation
of arsenic or phosphorous that is needed for the lightly-doped extension
regions (column 3 lines 36-41).” (Br. 15-16). However, this contention is
not persuasive because, as stated by the Examiner (a) the lightly doped
extension region is implicitly understood by an artisan to be formed on the
entire region before the spacers are formed and (b) Ahmad’s Figures 3-5
depict depositing a layer of insulating material over the exposed surface of
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lightly doped regions, which only remain beneath the spacers after the N+
implantation in Figure 3 is performed to form the N+ source and drain
regions. (Ans. 18-19.)
Appellants further contend that “Ahmad teaches the formation of an
oxide layer over the source/drain region (column 4 line 18) but not in contact
with a total exposed surface of the lightly-doped extension region as
advantageously claimed.” (Br. 16.) Appellants further contend that
“element 136 in Ahmad has the width of a sidewall spacer (column 5 lines
15-16; FIG. 4) and therefore does not have contact with the total exposed
surface of the lightly-doped extension regions.” (Br. 17.) This contention is
not persuasive because Appellants’ argument is directed to the spacer shown
in the final product in Ahmad and not the specific process steps described in
Ahmad. Appellants’ argument focuses on only item 136 and ignores the
process step in Ahmad that describes forming the insulating layer 130,
which, similar to the disputed claim step, is in contact with a total exposed
surface of the lightly doped extension regions formed in the implant areas
118. The Examiner specifically noted that:
As demonstrated in [Ahmad] figures 3-5, a[n] insulative
material is deposited/grown upon the exposed surface of figure
2 which is disclosed to have the claimed LDD [lightly doped
drain] region even though not explicitly shown. It is implicitly
understood from what is known in the art regarding LDD
regions that the depicted insulation layer of figures 3-5 is
clearly over and contacting exposed LDD region of figure 2.
(Ans. 19.)

Figure 3 of Ahmad illustrates that region 118 is completely covered
by insulative material (silicon oxide) 130. As discussed above, it would be
implicitly known to one of skill in the art that the lightly doped extension
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regions are defined by the impurity region 118. Therefore, we agree with
the Examiner that Ahmad discloses covering the entire exposed surface of
the lightly doped extension region with the insulating material 130.
Additionally, Appellants argue “Ahmad teaches the growth of an
oxide layer 130 (column 4 lines16-60) instead of the deposition of an
insulating material.” (Br. 16.) However, the Examiner found the term
“depositing” as being functionally equivalent to “growing” as used in the
Ahmad reference (Ans. 5, 20) as both result in forming an insulting layer.
Absent any evidence to the contrary submitted by the Appellants, we agree
with the Examiner.
We are also unpersuaded by Appellants’ argument (Br. 18) that the
combination of Ahmad and Chen would not have rendered obvious
independent claim 1, which recites the limitation “forming an interfacial
layer of nitrogen below the layer of insulating material and within the total
exposed surface of the lightly-doped extension regions.” The Examiner
found that forming a layer of nitrogen 131 below the SiO2 layer 130 of
Ahmad meets this limitation. (Ans. 5; Ahmad Fig. 3.) We agree with the
Examiner.
Finally, we are unpersuaded by Appellants’ argument (Br. 18-19) that
the combination of Ahmad and Chen would not have rendered obvious
independent claim 1, which recites the limitation “removing all of the
capping layer after the annealing.” The Examiner found that Chen teaches a
capping layer that is capable of being removed after annealing, and
therefore, Chen meets this limitation. (Ans. 6-7, 21; Chen at paragraphs 58-
60.) We agree with the Examiner.
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Appellants further contend “Chen et al. teaches that portions of the
cap layer must remain over the semiconductor substrate in order to serve as a
resistant protection layer for subsequent CMOS processing (paragraphs 0021
and 0055-0056). Therefore, the combination of Ahmad and Chen et al. also
teaches away from the advantageously claimed step of removing all of the
capping layer after the annealing.” (Br. 19.) Appellants then contend “one
of ordinary skill in the art would not combine a method requiring the cap
layer to remain (Ahmad) with a method requiring the removal of portions of
the cap layer (Chen et al.).” (Br. 19.) These contentions are not persuasive
because, as stated by the Examiner, Chen demonstrates a SiN capping layer
was known to be capable of being removed after it serves its function. (Ans.
21.) We also observe that Chen’s Figure 7 depicts the structure of Figure 5
after the remaining portion of the capping layer 24’ is removed.
Accordingly, we sustain the rejection of independent claim 1 under
35 U.S.C. § 103(a).
Claims 2-9 depend from claim 1. The Examiner found teachings in
the cited prior art references for each disputed limitation in these dependent
claims. Appellants made conclusory statements regarding why the
limitations in these claims are not the same as those disclosed and cited in
the prior art. However, Appellants failed to submit any evidence supporting
the arguments that the concentration limitations, the thickness limitations,
and the temperature limitations would not have been obvious or would have
produced unexpected results. Therefore, we sustain the rejection of claims
2-9 under 35 U.S.C. § 103(a), based on the Examiner’s findings and for the
same reasons discussed with respect to independent claim 1.
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Independent claim 10 recites limitations similar to those discussed
with respect to independent claim 1 and dependent claims 2-9. Appellants
have not presented any additional substantive arguments with respect to this
claim. For the same reasons discussed for claim 1, we also sustain the
rejection of claim 10.
Claim 19 depends from independent claim 1 and claim 20 depends
from independent claim 10. Claims 19 and 20 require the steps of forming
the layer of insulating material/silicon oxide and forming the interfacial
layer of nitrogen be performed without breaking vacuum. The Examiner
found that the cited prior art references are silent regarding the use of a
vacuum, and thus concluded that no vacuum was broken. Appellants have
failed to demonstrate that any step in the cited references break vacuum or
that a step was performed that would have required the breaking of a
vacuum. Therefore, we agree with the Examiner and sustain the rejection of
claims 19-20.

DECISION
The Examiner’s decision to reject claims 1-10 and 19-20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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