Ex Parte BrownDownload PDFPatent Trial and Appeal BoardMar 26, 201311343698 (P.T.A.B. Mar. 26, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/343,698 01/31/2006 David A. Brown 12 4961 7590 03/27/2013 Ryan, Mason & Lewis, LLP 90 Forest Avenue Locust Valley, NY 11560 EXAMINER BERTRAM, RYAN ART UNIT PAPER NUMBER 2187 MAIL DATE DELIVERY MODE 03/27/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte DAVID A. BROWN ____________________ Appeal 2010-009431 Application 11/343,698 Technology Center 2100 ____________________ Before DENISE M. POTHIER, BARBARA A. BENOIT, and TRENTON A. WARD, Administrative Patent Judges. WARD, Administrative Patent Judge. DECISION ON APPEAL Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s non- final rejection of claims 1, 2, 4-6, 8-18, and 20. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. STATEMENT OF THE CASE Appellant’s claimed invention relates to logical-to-physical address translation on a per client basis. See generally Abstract. Claim 1 is illustrative with certain disputed limitations italicized: Appeal 2010-009431 Application 11/343,698 2 1. A processor comprising: a plurality of clients; translation configuration circuitry comprising a plurality of translation configuration registers, a given one of the plurality of translation configuration registers storing translation configuration information for at least a given one of the plurality of clients; address translation circuitry coupled to the translation configuration circuitry, the address translation circuitry being configured to utilize the translation configuration information for the given client to generate a physical address from a logical address specified in a request from the given client; and memory controller circuitry coupled to the address translation circuitry, the memory controller circuitry being configured to access a memory utilizing the physical address; wherein the address translation circuitry is configured to perform at least first and second different types of address translation, wherein selection of a given one of the different types of address translation for use with the logical address specified in the request from the given client is based on the translation configuration information stored for the given client in at least the given one of the plurality of translation configuration registers. THE REJECTIONS The Examiner rejected claims 1, 2, 8, 9, 11, 12, and 14-18 under 35 U.S.C. § 103(a) as unpatentable over Carlson (US 4,285,040; issued Aug. 18, 1981), Shrader (US 7,100,002 B2; issued Aug. 29, 2006), Ikeda (US 5,623,688; issued Apr. 22, 1997), and the Microsoft Computer Dictionary (“MCD”). Ans. 3-14.1 The Examiner rejected claims 4-6 and 20 under 35 U.S.C. § 103(a) as unpatentable over Carlson, Shrader, Ikeda, MCD, and Fung (US 4,899,272; issued Feb. 6, 1990). Ans. 14-17. 1 Throughout this opinion, we refer to (1) the Appeal Brief (“App. Br.”) filed Feb. 4, 2010, (2) the Examiner’s Answer (“Ans.”) mailed Apr. 23, 2010, and (3) the Reply Brief (“Reply Br.”) filed June 23, 2010. Appeal 2010-009431 Application 11/343,698 3 The Examiner rejected claim 10 and 13 under 35 U.S.C. § 103(a) as unpatentable over Carlson, Shrader, Ikeda, MCD, and Cole (US 5,179,675; issued Jan. 12, 1993). Ans. 17-19. THE OBVIOUSNESS REJECTION OVER CARLSON, SHRADER, IKEDA, AND MCD CLAIMS 1, 2, 8, 9, 11, 12, and 14-18 The Examiner finds that Carlson teaches many of the recited features of claim 1 (Ans. 3-4) except that Carlson does not expressly teach the claim 1 limitations regarding a plurality of translation configuration registers storing translation configuration information for a client, the address translation circuitry being configured to utilize the translation configuration information for a client to generate a physical address from a logical address, or a memory controller circuit being configured to access a memory utilizing the physical address. Ans. 4-5 (citing claim 1). The Examiner cites the combination of Carlson, Shrader, and Ikeda as teaching these features in concluding that the claim would have been obvious. Ans. 4-6. Appellant argues that the Examiner’s combination is insufficient because Carlson selects a type of address translation based solely on the logical address itself regardless of the client from which a request is received. App. Br. 7; Reply Br. 3. Appellant further argues that Ikeda does not teach that “address translation is performed on a per-user basis,” as required by claim 1, but merely indicates that a given user may be assigned a given number of entries within an address translation table. App. Br. 8; Reply Br. 3. Appeal 2010-009431 Application 11/343,698 4 ISSUE Under § 103, has the Examiner erred in rejecting claim 1 by finding that the combination of the cited prior art teaches the translation configuration circuitry, the address translation circuitry, and memory controller circuitry recited in claim 1? ANALYSIS On this record, we find no error in the Examiner’s obviousness rejection of claim 1. Appellant makes numerous arguments regarding the Examiner’s reliance upon Carlson and Ikeda in rejecting claim 1, and we address Appellant’s arguments seriatim. First, Appellant argues that Carlson fails to teach providing per-client translation configuration, as recited in claim 1. App. Br. 8. More specifically, Appellant argues that rather than selecting a type of address translation for use with a logical address specified in a request from a given client based on the translation configuration information stored for the given client, Carlson selects a type of address translation based solely on the logical address itself regardless of the client from which a request is received. App. Br. 7. Contrary to Appellant’s arguments, the Examiner finds that Carlson teaches having two modes of address translation for at least one client. Ans. 4-5 (citing Carlson, 10:19-29). Specifically, Carlson discloses that the value stored in flip-flop 60 determines whether address translation is carried out in “segment mode” or “sub-segment mode” operation. Carlson, 10:19-29 (disclosing that a value of “1” in the flip-flop 60 defines segment mode address translation and a value of “0” in the flip-flop 60 defines sub-segment Appeal 2010-009431 Application 11/343,698 5 mode address translation). Therefore, the Examiner concludes that flip-flop 60 in Carlson teaches a register holding value to select the type of address translation. Ans. 5. Second, Appellant argues that the flip-flop 60 in Carlson fails to teach per-client translation configuration as recited in claim 1. App. Br. 8. Despite Appellant’s argument, the Examiner does not rely upon Carlson for this feature, but instead cites Ikeda as teaching “address translation is performed on a per-user basis.” Ans. 5 (citing Ikeda, 5:51-65). Ikeda teaches that a local address translation table is used store address translation information for a particular client, such a “1-user mode” in which address tables are used with “32 entries per user.” Ikeda, 5:51-55. Specifically, Ikeda teaches that “[b]y retrieving the contents of the address translation table 115A based on the virtual address obtained from the access controller 114, it is possible to read an entry of the local address translation table 115A1 and an entry of the global address translation table 30 115A2.” Ikeda, 5:26-31. Thus, Ikeda teaches client specific address translation. We find this position reasonable and are not persuaded of error in the Examiner’s finding that Ikeda teaches that address translation can be performed on a per-user basis. Third, Appellant acknowledges that Ikeda teaches that a given user may be assigned a given number of entries within an address translation table, but Appellant argues that Ikeda does not teach the selection of a given one of the different types of address translation. App. Br. 8. Despite Appellant’s argument, the Examiner does not rely upon Ikeda for this claimed feature. See Ans. 4-5. As discussed above, the Examiner finds that Carlson teaches that the data stored in flip-flop 60 selects a type of address Appeal 2010-009431 Application 11/343,698 6 translation. Ans. 4-5 (citing Carlson, 10:19-29). Thus, we are not persuaded of error in the Examiner’s finding that the combination of the user specific address translation in Ikeda with the flip-flop register designation of an address translation type in Carlson teach Appellant’s claimed features regarding the translation configuration circuitry and address translation circuitry recited in claim 1. We are therefore not persuaded that the Examiner erred in rejecting claim 1, and claims 2, 8, 9, 11, 12, and 14-18 not separately argued with particularity. THE OBVIOUSNESS REJECTION OVER CARLSON, SHRADER, IKEDA, MCD, AND FUNG CLAIMS 4 AND 5 Appellant’s claim 4 adds a limitation requiring that one of the translation configuration registers stores information specifying a particular number of banks of a multiple-bank memory that are allocated to the given client. The Examiner relies upon Fung as teaching this feature. Ans. 15 (citing Fung, 5:28-33). Appellant argues that claim 4, dependent from claim 1, is separately patentable because Fung fails to teach or suggest storing information specifying a particular number of banks of a multiple-bank memory that are allocated to the given client. App. Br. 9. Appellant does not argue that Fung fails to teach associating a memory bank with a register value, but that it fails to disclose that the banks are allocated to a given client. App. Br. 9. As with claim 1 above, Appellant’s arguments do not comport with the Examiner’s claim mapping. The Examiner states that Fung teaches “associating a bank of memory with a register value to determine if the addresses are owned by that bank of Appeal 2010-009431 Application 11/343,698 7 memory.” Ans. 15 (Fung, 5:28-33). Thus, the Examiner relies upon Fung for the limited teaching of associating a bank of memory with a register value, and relies upon the combination of the previous discussed teachings of Carlson and Ikeda for register value storage and per-user address translation, respectively. See Ans. 3-6. We are not persuaded of error in the Examiner’s combination. Accordingly, we sustain the Examiner’s rejection of claim 4 and claim 5, not separately argued with particularity. CLAIMS 6 and 20 Appellant argues that claims 6 and 20 are separately patentable because Fung fails to disclose storing information specifying one or more bits of a logical address that are to be used to determine a bank portion of the physical address as required by claims 6 and 20. App. Br. 10. Contrary to Appellant’s arguments, the Examiner finds that Fung teaches registers that store the starting addresses of each bank of memory, which defines where addresses are in the memory and associates a bank of memory with a register value to determine if the addresses are owned by that bank of memory. Ans. 16 (citing Fung, 4:42-49; 5:28-33). As Fung includes teachings that associate a bank of memory with a register value to determine if the addresses are owned by that bank of memory (Fung, 5:28-33), we are not persuaded of error in the Examiner’s findings. Thus, we sustain the Examiner’s rejection of claims 6 and 20. CLAIMS 10 and 13 Although Appellant nominally argue claims 10 and 13 separately (App. Br. 10), Appellant nonetheless relies on arguments similar to those for Appeal 2010-009431 Application 11/343,698 8 claim 1, which we find unpersuasive for the reasons indicated previously. We therefore sustain the Examiner's rejection of these claims. ORDER The Examiner’s decision rejecting claims 1, 2, 4-6, 8-18, and 20 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED babc Copy with citationCopy as parenthetical citation