Ex Parte Blair et al

Patent Trial and Appeal Board

Mar 28, 2017

12817869 (P.T.A.B. Mar. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/817,869 06/17/2010 Cynthia Blair 1012-0199/2010P50113
us
6487
57579 7590 03/30/2017
MT TRPHY RTTAK Rr HOMTT T FR/TNFTNFON TFrHNOT OFTFS
EXAMINER
1255 Crescent Green
Suite 200
O TOOLE, COLLEEN J
CARY, NC 27518 ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
03/30/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
official@mbhiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CYNTHIA BLAIR and HELMUN BRECH1
Appeal 2016-003594
Application 12/817,869
Technology Center 2800
Before BRADLEY R. GARRIS, KAREN M. HASTINGS, and
JENNIFER R. GUPTA, Administrative Patent Judges.
GARRIS, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134, Appellants appeal from the Examiner’s
rejections under 35 U.S.C. § 103(a) of claims 1—28 as unpatentable over
Leighton (US 6,734,728 B1 issued May 11, 2004) in view of Blair
(US 6,177,834 B1 issued Jan. 23, 2001) and/or Yoshimura (US 5,170,241
issued Dec. 8, 1992) alone or in combination with additional prior art. We
have jurisdiction under 35 U.S.C. § 6.
1 Infineon Technologies AG is identified as the real party in interest. App.
Br. 2.
Appeal 2016-003594
Application 12/817,869
We AFFIRM.
Appellants claim a power device 100 comprising a power
transistor 110, a capacitor Cout, inductive bond wires connecting the drain
node D of the power transistor to a second plate 138 of the capacitor, and a
voltage clamping device 160 coupled in parallel with the capacitor and
connected to the output node of the power transistor by the inductive bond
wires, the voltage clamping device operable to limit the voltage at the
second plate of the capacitor to a value below an avalanche breakdown
voltage of the power transistor (independent claim 14, Fig. 1).
Correspondingly, Appellants also claim a voltage clamping circuit
(independent claim 1), a method of suppressing voltage spikes in a power
device (independent claim 8), a method of manufacturing a power device
(independent claim 20), and an integrated voltage clamping device
(independent claim 24). In a particular embodiment, the power transistor
and the capacitor are integrated on the same semiconductor die (dependent
claim 18; see also dependent claim 22).
A copy of representative claims 14 and 18, taken from the Claims
Appendix of the Appeal Brief, appears below.
14. A power device, comprising:
a power transistor;
a capacitor with a first plate coupled to a ground node and a second
plate separated from the first plate by an insulator;
a first plurality of wires coupling a drain node of the power transistor
to the second plate of the capacitor, the first plurality comprising inductive
bond wires connecting the drain node of the power transistor to the second
plate of the capacitor;
a second plurality of wires coupling the second plate of the capacitor
to a DC supply node; and
2
Appeal 2016-003594
Application 12/817,869
a voltage clamping device coupled in parallel with the capacitor and
connected to the output node of the power transistor by the inductive bond
wires, the voltage clamping device operable to limit the voltage at the
second plate of the capacitor to a value below an avalanche breakdown
voltage of the power transistor.
18. A power device according to claim 14, wherein the power
transistor and the capacitor are integrated on the same semiconductor die.
Appellants present arguments directed to the independent claims as a
group (App. Br. 8—19), of which claim 14 is representative, and present
arguments directed to dependent claims 18 and 22 as a group (id. at 19—23),
of which claim 18 is representative. The remaining claims on appeal have
not been separately argued and will stand or fall with their parent claims as
represented by claims 14 and 18.
We will sustain the § 103 rejections advanced in this appeal for the
reasons expressed in the Final Action, the Answer, and below.
In rejecting the independent claims, the Examiner finds that Leighton
fails to disclose the claimed voltage clamping device but concludes that it
would have been obvious to use the voltage clamping device taught by
Yoshimura’s Figure 3 A in the power device of Leighton in order to protect
the power transistor (Final Action 3, 5, 8). In rejecting dependent claims 18
and 22, the Examiner finds that Leighton teaches or would have suggested
integrating the power transistor and capacitor on the same semiconductor die
as claimed (id. at 6, 14 (citing Figs. 4A and 5)).
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Appeal 2016-003594
Application 12/817,869
Appellants argue that the combination of Leighton and Yoshimura
would have resulted in Yoshimura’s clamping device or diode being directly
connected to the drain terminal of Leighton’s power transistor rather than the
connection proposed by the Examiner and required by the independent
claims wherein, for example, the clamping device is coupled in parallel with
the capacitor and connected to the output or drain node of the power
transistor by inductive bond wires (App. Br. 14). According to Appellants,
“[b]y introducing intervening circuit elements between the clamp diode [of
Yoshimura] and the drain terminal of Leighton’s MOSFET (such as
Leighton’s inductor [i.e., bond wire inductance] 314), the effectiveness of
Yoshimura’s clamp diode becomes attenuated” {id. at 15—16).
Appellants’ argument lacks persuasive merit. As convincingly
explained by the Examiner, an artisan with ordinary skill would not have
necessarily combined Leighton and Yoshimura in the manner urged by
Appellants because Yoshimura discloses that the clamping circuit is
externally connected to the power MOSFET (Ans. 3 (citing Yoshimura col.
2,11. 41 44)). On the other hand, it would have been obvious for the artisan
to connect Yoshimura’s external clamping circuit to Leighton’s power
MOSFET via bond wires because Leighton explicitly teaches bond wires
such as bond wire 314 are used to electrically coupled components of power
transistor 300 {id. (citing Leighton col. 5,11. 65—67, col. 6,11. 1, 39-40)).
Moreover, we emphasize that Appellants provide the appeal record with no
evidence in support of their position that, in the Examiner’s proposed
combination of Leighton and Yoshimura, “the effectiveness of Yoshimura’s
clamp diode becomes attenuated” (App. Br. 16). Further, even if
effectiveness were attenuated, the circuit connection proposed by the
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Appeal 2016-003594
Application 12/817,869
Examiner and required by the independent claims does not become
patentable simply because it may be somewhat inferior to the connection
urged by Appellants. See In re Mouttet, 686 F.3d 1322, 1334 (Fed. Cir.
2012).
Concerning dependent claims 18 and 22, Appellants contend that
Figures 4A and 5 of Feighton show “individual chips . . . connected by bond
wires” (App. Br. 21) and that “this is not the configuration encompassed by
claims 18 and 22” (id.). Appellants additionally contend that “Feighton’s
disclosure that the bond wire 314 is used to connect the die 319 to the
capacitor precludes the possibility that these two devices are ‘integrated’ in a
single die” (id. at 22).
Appellants’ contentions are unpersuasive. Contrary to Appellants’
belief, the rejection of these dependent claims is not undermined by the fact
that Feighton connects field effect transistor die 319 to output capacitor 318
with bond wire 314 (see, e.g., Fig. 4A). This is because dependent claims 18
and 22 likewise connect power transistor 110 to capacitor Cout with bond
wires as expressly recited in parent claims 14 and 20 (see, e.g., Fig. 1). In
addition, the Examiner finds that Figures 4A and 5 show the claimed power
transistor and capacitor integrated on the same semiconductor die (Final
Action 6, 14, Ans. 8), and this finding is supported by Feighton’s express
disclosure that Figure 4A “illustrates the physical configuration of a novel
RF power transistor with one die circuit” (col. 5,11. 12—13). Appellants fail
to reveal harmful error in the Examiner’s determination that dependent
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Appeal 2016-003594
Application 12/817,869
claims 18 and 22 do not patentably distinguish over Leighton’s one die
circuit disclosure.2
In summary, Appellants’ arguments do not show reversible error in
the Examiner’s § 103 rejections of independent claims 1, 8, 14, 20, and 24 or
of dependent claims 18 and 22. We sustain, therefore, the § 103 rejections
of claims 1—28.
The decision of the Examiner is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136.
AFFIRMED
2 Furthermore, the Examiner’s determination is reinforced by the Yoshimura
reference which evinces that it was known in the prior art to integrate a
power MOSFET and a diode on the same chip to provide a breakdown
voltage protection circuit on the same MOSFET chip (Yoshimura Figs. 5—6,
col. 5,11. 42^16, col. 6,11. 28-32).
6