Ex Parte Augsburg et al

Patent Trial and Appeal Board

Dec 31, 2012

11343765 (P.T.A.B. Dec. 31, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte VICTOR ROBERTS AUGSBURG,
JAMES NORRIS DIEFFENDERFER, JEFFREY TODD BRIDGES,
and THOMAS ANDREW SARTORIUS
____________

Appeal 2010-006975
Application 11/343,765
Technology Center 2100
____________

Before SCOTT R. BOALICK, BARBARA A. BENOIT, and
JENNIFER L. McKEOWN, Administrative Patent Judges.

BENOIT, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134 involving claims for cache
locking in a processor. The Examiner has rejected all of the pending claims
as anticipated or unpatentable as obvious over prior art. We have
jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part.

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STATEMENT OF THE CASE
Appellants’ invention relates to cache locking without interference
from normal cache allocations in a processor. See generally Abstract;
Spec. ¶ 0001. Claims 1-21 are on appeal. Claims 1, 9, and 13 are
illustrative and read as follows, with key disputed limitations emphasized:
1. A method of restricting allocations in a cache, comprising:
in a restricted mode, allowing only a predetermined set of one or
more types of instructions to allocate cache entries; and
in a non-restricted mode, allowing any memory access instruction to
allocate cache entries.

9. A method of managing a cache, comprising:
entering a restricted mode wherein only one or more predetermined
types of instructions may allocate cache entries;
allocating cache entries using the predetermined types of instructions;
and
exiting the restricted mode and allocating cache entries for any
memory access instruction.

13. A processor, comprising:
a cache memory;
a configuration register having a Block Normal Cache Allocation
(BNCA) bit; and
a cache controller operative to control the allocation of entries in the
cache by memory access instructions, and further operative to disallow said
allocation, except for a predetermined set of one or more types of
instructions, when the BNCA bit is set.

The Rejections
1. The Examiner rejected claims 13 and 18-21 under 35 U.S.C.
§ 102(b) as anticipated by Larsen (US 5,371,872; issued Dec. 6, 1994). Ans.
3-7.
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2. The Examiner rejected claims 1-3, 6, 8, 9, 11, 12, 15, and 17 under
35 U.S.C. § 103(a) as unpatentable over Larsen and Palanca (US
2002/0007441 A1; published Jan. 17, 2002). Ans. 7-11.
3. The Examiner rejected claim 16 under 35 U.S.C. § 103(a) as
unpatentable over Larsen, Palanca, and Alpert (US 5,249,286; issued Sept.
28, 1993). Ans. 12.
4. The Examiner rejected claims 4, 5, 10, and 14 under 35 U.S.C.
§ 103(a) as unpatentable over Larsen, Palanca, and Olukotun (US
2005/0044320 A1; published Feb. 24, 2005). Ans. 12-15.
5. The Examiner rejected claim 7 under 35 U.S.C. § 103(a) as
unpatentable over Larsen, Palanca, and Nicol (US 6,438,655 B1; issued
Aug. 20, 2002). Ans. 15-16.

THE ANTICIPATION REJECTION
The Examiner finds that Larsen discloses every recited limitation of
independent claim 13. Ans. 3-4. Appellants argue that Larsen does not
describe a cache controller operative to control the allocation of entries in
the cache by memory access instructions, and further operative to disallow
the allocation, except for a predetermined set of one or more types of
instructions, when the BNCA bit is set, as recited by claim 13. App. Br. 7-8.
The issue with respect to this rejection is: Under § 102, has the
Examiner erred in rejecting claims 13 and 18-21 by finding that Larsen
discloses “a cache controller operative to control the allocation of entries in
the cache by memory access instructions, and further operative to disallow
the allocation, except for a predetermined set of one or more types of
instructions, when the BNCA bit is set”?
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Analysis
Based on the record before us, we are persuaded of error in the
Examiner’s anticipation rejection of independent claim 13. Appellants argue
the Examiner erred because Larsen does not allow any instructions and/or
data to be allocated to the cache during an interrupt mode, which does not
read on the claimed cache controller which is further operative to disallow
said allocation, except for a predetermined set of one or more types of
instructions, when the BNCA bit is set. App. Br. 7. The Examiner maps
(Ans. 4) this claim element to the portion of Larsen which states: “For
example, an interrupting process may be prevented from placing instructions
in the cache, from placing data in the cache or from placing instructions and
data in the cache” (col. 4, ll. 20-25). Appellants correctly point out that
Larsen’s techniques block any attempted cache entry allocations and
therefore do not anticipate claim 13 which requires disallowing allocation of
entries in the cache, except for a predetermined set of instructions, when the
BNCA bit is set. App. Br. 7.
In response to Appellants’ contentions, the Examiner explains a
hypothetical situation in which Larson’s LD data storage bit is set to allow
storage and the L1 instruction storage bit is set not to allow storage, and
concludes that this hypothetical situation reads on claim 13. Ans. 17 (citing
col. 6, ll. 9-50; col. 7, ll. 16-30). Notably, as Appellants point out (Reply Br.
4), Larsen does not describe the combination of bits presented by the
Examiner in which data is allowed by the LD data storage bit to write to
cache, whereas instructions are not allowed by the L1 instruction storage bit
to write to cache. Rather, Larsen merely discloses the existence of the two
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bits, LD and L1, to control data and instruction storage respectively. The
Examiner’s hypothetical situation, not disclosed in the reference, of using
two bits to provide a similar result of allowing some but not all instructions
to allocate entries in cache memory is not sufficient to anticipate claim 13.
Accordingly, we will not sustain the rejection of claim 13 and its
dependent claim 18.
Independent claim 19 recites a processor comprising means for
controlling the allocation of entries in the means for storing cache entries by
memory access instructions, as well as means for disallowing the allocation,
except for a predetermined set of one or more types of instructions, when the
BNCA bit is set. For similar reasons discussed above with respect to claim
13, we likewise will not sustain the rejection of independent claim 19 and its
dependent claims 20 and 21.

THE OBVIOUSNESS REJECTIONS
In rejecting independent claim 9 as obvious over Larsen and Palanca,
the Examiner relies on Larsen’s disclosure of a CPU examining cache when
processing a memory access instruction where i) if the referenced memory
location is stored in cache, cache is read and ii) if the referenced memory
location is not stored in cache, main memory is read and the cache is
updated for future use. Ans. 9 (citing col. 1, ll. 47-57). The Examiner cites
this disclosure of a CPU examining cache for the claim 9 limitations “only
one or more predetermined types of instructions may allocate cache entries;
allocating cache entries using the predetermined types of instructions; and
exiting the restricted mode and allocating cache entries for any memory
access instruction.” Id. The Examiner cites Palanca for disclosing entering
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a restricted mode. Ans. 10. Appellants contend that the Examiner erred
because Palanca does not teach or suggest entering a restricted mode where
only predetermined types of instructions may allocate cache entries. See
App. Br. 10.
The issue with respect to this rejection is: Under § 103, has the
Examiner erred by finding that Larsen and Palanca collectively teach or
suggest entering and exiting a restricted mode where only predetermined
types of instructions may allocate cache entries?

Analysis
Claims 9-12 and 17
Based on the record before us, we are persuaded of error in the
Examiner’s obviousness rejection of independent claim 9. The Examiner
has cited the same cache memory handling disclosure of Larsen as reading
on claim 9 except for entering the restricted mode, for which the Examiner
relies on Palanca. The Examiner explains that Larsen discloses “only one or
more predetermined types of instructions may allocate cache entries” and
“allocating cache entries using the predetermined types of instructions” in
that Larsen teaches or suggests that the recited predetermined set is a
predetermined set of all types of instructions. Ans. 9 (emphasis added).
We agree with Appellants that Larsen is deficient under § 103
with regard to independent claim 9. App. Br. 10; Reply Br. 5. For
instance, claim 9 recites “exiting the restricted mode and allocating
cache entries for any memory access instruction,” which the Examiner
maintains is disclosed by Larsen’s cache memory handling disclosure.
Ans. 9 (citing col. 1, ll. 47-57). The cited portion of Larsen, however,
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is silent on exiting the restricted mode. Interestingly, the Examiner
relies on Palanca for teaching “entering a restricted mode” and relies
on Larsen for teaching “exiting the restricted mode.” Ans. 9-10. In
any event, we are persuaded that Larsen fails to teach or suggest
“exiting the restricted mode,” as recited by claim 9.
Accordingly, we will not sustain the rejection of independent claim 9
and its dependent claims 11, 12, and 17 as unpatentable over Larsen and
Palanca. Also, because the Examiner has not shown that Olukotun cures the
deficiencies regarding claim 9 (Ans. 14-15), we do not sustain for similar
reasons the rejection of claim 10, which depends from claim 9.
Claim 14
Because the Examiner has not shown that Palanca and/or Olukotun
cures the deficiencies noted above regarding the independent claim 13 (Ans.
14-15), we will not sustain the rejection of claim 14, which depends from
claim 13, for the reasons discussed above with respect to claim 13.
Claims 1-8, 15, and 16
We, however, will sustain the rejection of independent claim 1 as
unpatentable over Larsen and Palanca. Independent claim 1 is strikingly
broad and recites in a restricted mode, allowing only a predetermined set of
one or more types of instructions to allocate cache entries; and in a non-
restricted mode, allowing any memory access instruction to allocate cache
entries. The Examiner rejects claim 1 based on Larsen’s cache memory
handling disclosure used to reject claim 9 (Ans. 7 (citing col. 1, ll. 47-57))
and Palanca teaching a restricted mode and a non-restricted mode (Ans. 7-8).
Unlike claim 9, which recites exiting a restricted mode, claim 1 merely
recites “in a restricted mode” and “in a non-restricted mode.” Here, the
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Examiner also cites Palanca for teaching a restricted mode and a non-
restricted mode. Thus, on balance, we are not persuaded of error in the
rejection of claim 1.
Appellants also argue that Larsen teaches away from the Examiner’s
combination with Palanca because Larsen focuses on “maintaining at least a
section of the cache from being overwritten during an interrupt.” Reply Br.
3. Larsen, however, does not criticize, discredit, or otherwise discourage
investigation into the claimed invention having a restricted mode and a non-
restricted mode. See DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
567 F.3d 1314, 1326-27 (Fed. Cir. 2009) (stating “[a] reference does not
teach away, however, if it merely expresses a general preference for an
alternative invention but does not criticize, discredit, or otherwise discourage
investigation into the invention claimed” (citation omitted) (internal
quotation marks omitted)). We therefore are not persuaded that a person of
ordinary skill, upon reading Larsen’s disclosure, would be discouraged from
allowing only a predetermined set of one or more types of instructions to
allocate cache entries in a restricted mode or allowing any memory access
instruction to allocate cache entries in a non-restricted mode, as recited by
claim 1. See In re Kahn, 441 F.3d 977, 990 (Fed. Cir. 2006) (stating “[a]
reference may be said to teach away when a person of ordinary skill, upon
reading the reference, would be discouraged from following the path set out
in the reference, or would be led in a direction divergent from the path that
was taken by the applicant” (citation omitted) (internal quotation marks
omitted)).
Nor are we persuaded by Appellants’ argument that Larsen teaches
away because the combination of Larsen and Palanca would render the
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claimed invention unsatisfactory for its intended purpose of allowing only a
predetermined set of instruction types to disturb the cache because Larsen
protects a section of cache from being overwritten during an interrupt.
Reply Br. 3-4. Larsen describes protecting a section of cache during an
interrupt, which would not render claim 1 unsatisfactory or inoperable for its
intended purpose. Claim 1 recites “in a restricted mode, allowing only a
predetermined set of one or more types of instructions to allocate cache
entries,” which contrary to Appellants’ assertion, is consistent with
protecting cache during an interrupt.
Thus, we agree that the Examiner’s proposed combination of Larsen
and Palanca predictably uses prior art elements according to their established
functions—an obvious improvement. See KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 417 (2007). We therefore sustain the rejection of independent
claim 1, and its dependent claims 2, 3, 6, 8, and 15 which were not
separately argued with particularity, under § 103 as unpatentable over
Larsen and Palanca.
Claim 16 depends from claim 15, which, in turn, depends from claim
1. Appellants argue with regard to claim 16 that Alpert does not cure the
alleged deficiencies of Larsen and Palanca. App. Br. 10. We are not
persuaded of Examiner error for the reasons discussed above with respect to
claims 1 and 15.
Claim 4 depends from independent claim 1, and claim 5 depends from
claim 4. With regard to claims 4 and 5, Appellants argue that Olukotun does
not cure the alleged deficiencies of Larsen and Palanca. App. Br. 11. For
the reasons discussed above with respect to claim 1, we are not persuaded of
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error in the Examiner’s rejection of claims 4 and 5 and sustain the rejection
of claims 4 and 5.
Claim 7 depends from claim 1. Appellants argue that Nicol does not
cure the alleged deficiencies of Larsen and Palanca. App. Br. 11. We are
not persuaded of Examiner error in the rejection of claim 7 for the same
reasons discussed above with respect to claim 1.

CONCLUSION
Under § 102, the Examiner erred in rejecting claims 13 and 18-21.
Under § 103, the Examiner did not err in rejecting claims 1-8, 15, and
16 but erred in rejecting claims 9-12, 14, and 17.

ORDER
The Examiner’s decision rejecting claims 1-21 is affirmed-in-part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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