Ex Parte Ash et al

Patent Trial and Appeal Board

Mar 20, 2017

12707357 (P.T.A.B. Mar. 20, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/707,357 02/17/2010 Kevin J. Ash TUC920090103US1 2395
78650 7590 03/22/2017
Nelson anH Nelson
EXAMINER
775 High Ridge Drive
Alpine, UT 84004
GIARDINO JR, MARK A
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
03/22/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
dan @ nnpatentlaw .com
alexis @nnpatentlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KEVIN J. ASH, MICHAEL T. BENHASE,
EVANGELOS S. ELEFTHERIOU, LOKESH M. GUPTA,
ROBERT HAAS, YU-CHENG HSU, XIAO YU HU,
JOSEPH S. HYDE II, ROMAN A. PLETKA, and
ALFRED E. SANCHEZ
Appeal 2016-006097
Application 12/707,3571
Technology Center 2100
Before ELENI MANTIS MERCADER, JAMES W. DEJMEK, and
JOHN D. HAMANN, Administrative Patent Judges.
HAMANN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants file this appeal under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 1—7 and 10—18. The Examiner
allowed claims 19 and 20 and objected to claims 8 and 9. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 According to Appellants, the real party in interest is International Business
Machines Corporation. App. Br. 2.
Appeal 2016-006097
Application 12/707,357
THE CLAIMED INVENTION
Appellants’ claimed invention “relates to storage systems and more
particularly relates to integrating a flash-based cache into large storage
systems.” Spec. 11.
Claim 1 is illustrative of the subject matter of the appeal and is
reproduced below.
1. An apparatus to integrate a flash-based cache into a
storage system, the apparatus comprising:
an input/output (“I/O”) enclosure having a plurality of
slots for receiving host adapters and device adapters, wherein a
host adapter is placed into a first slot of the I/O enclosure such
that the host adapter resides within an interior of the I/O
enclosure, and a device adapter is placed into a second slot of the
I/O enclosure such that the device adapter resides within the
interior of the I/O enclosure;
a flash-based caching device (“flash cache”) placed into a
third slot of the I/O enclosure such that the flash cache resides
within the interior of the I/O enclosure, the flash cache
comprising a flash-based memory configured to cache data
associated with data requests handled through the I/O enclosure;
and
a primary processor complex external to the I/O enclosure
that manages data requests handled through the I/O enclosure,
the primary processor complex configured to communicate with
the host adapter, the device adapter, and the flash cache to
manage the data requests.
REJECTIONS ON APPEAL
(1) The Examiner rejected claims 1, 5, and 13—17 under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of (i) Cathy Warrick
etal., The IBM TotalStorage DS8000 Series: Concepts and
Architecture, 24—25 (1st ed. 2005) (hereinafter “TotalStorage”) and
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Application 12/707,357
(ii) Mark Peters, NetApp’s Solid State Hierarchy: With a Focus on Flash
Cache, 6 (Sept. 2009) (hereinafter “Peters”).
(2) The Examiner rejected claims 2—4, 6, and 7 under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of TotalStorage, Peters,
and Forhan et al. (US 2011/0072194 Al; published Mar. 24, 2011)
(hereinafter “Forhan”).
(3) The Examiner rejected claims 10, 12, and 18 under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of TotalStorage, Peters,
and Yoshida (US 2008/0244188 Al; published Oct. 2, 2008).
(4) The Examiner rejected claim 11 under 35 U.S.C. § 103(a) as
being unpatentable over the combination of TotalStorage, Peters, Yoshida,
and Hillman (US 2006/0184735 Al; published Aug. 17, 2006).
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
contentions that the Examiner erred. In reaching our decision, we consider
all evidence presented and all arguments made by Appellants.
We disagree with Appellants’ arguments and we incorporate herein
and adopt as our own the findings, conclusions, and reasons set forth by the
Examiner in (1) the September 17, 2015 Final Office Action (“Final Act.”
2—10) and (2) the May 19, 2016 Examiner’s Answer (“Ans.” 2—5). We
highlight and address, however, specific findings and arguments below for
emphasis.
(1) Flash cache placed into a slot of an I/O enclosure
Appellants argue the combination of TotalStorage and Peters fails to
teach or suggest having “a flash-based caching device (‘flash cache’) placed
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Application 12/707,357
into a” slot of an I/O enclosure, in accordance with claims 1, 13, and 16.
App. Br. 8—10; Reply Br. 2—3. Specifically, Appellants argue TotalStorage
instead teaches that “all slots of the I/O enclosure are configured to receive
either device adapters or host adapters,” rather than a flash cache. App.
Br. 9 (citing TotalStorage 29); Reply Br. 2—3 (citing TotalStorage 21, 23;
Fig. 2-3). Appellants also argue the references have different slot
architectures (i.e., PCI-X for TotalStorage and PCE-Express for Peters) that
“work in completely different ways, have different applications, and have
physically incompatible architectures.” App. Br. 10 (citation omitted); see
also Reply Br. 3 (arguing “the devices taught by TotalStorage and Peters
could not operate with one another without significant modification”).
Appellants contend it would not have been obvious to place a flash cache in
a slot not intended or configured for it (i.e., a slot that is reserved for other
types of devices). See, e.g., Reply Br. 2—3.
The Examiner finds the combined teachings of TotalStorage and
Peters teach or suggest the disputed limitation. Ans. 2—3; Final Act. 2-4.
Specifically, the Examiner finds “it would have been obvious to one having
ordinary skill in the art to implement a flash cache card (the concept of
which is taught by Peters) instead of a host or device adapter in one of the
slots of Total Storage.” Ans. 3; Final Act. 3 (citing TotalStorage 29 (finding
§ 2.3.2 teaches a third I/O slot in an I/O enclosure), Peters 6 (finding Peters
teaches a flash cache controller card configured to cache data associated
with data requests handled by the I/O enclosure)). The Examiner further
finds “it would be obvious to one of ordinary skill in the art to place the
flash card of Peters in one of the slots of Total Storage” to aid I/O
performance, increase shareability, and ease recovery. Ans. 3 (citing Peters
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Application 12/707,357
6, 8); see also Ans. 4 (finding “the concept of a flash cache card would be
obvious to implement in TotalStorage,” rather than “propos[ing] that one
take the exact card taught by Peters and place the card in a slot of the I/O
enclosure taught by TotalStorage”).
We agree with the Examiner’s findings and adopt them as our own.
For example, we agree the combined teachings of TotalStorage and Peters
teach, or at least suggest, having a flash-based caching device (i.e., Peters’
Flash Cache card) — which is flash based memory configured to cache data
associated with data requests (i.e., NAND flash-based Flash Cache that
“read caches for the storage controller” and “cache[s] metadata and user data
with the aim of avoiding disk reads and the added latency and limited IO
throughput that result from such reads”) — placed into a slot in the interior
of an I/O enclosure (e.g., TotalStorage’s I/O enclosure and slots). See
Peters 6, 8; TotalStorage 23, 29. In further support of the findings, we note
Peters also teaches that its Flash Cache card is server based, sitting in the
controller, and, thus, interior to the I/O enclosure. Peters 3, 6 (the Flash
Cache card is placed “in the controller (meaning no additional rack space is
consumed)”).
Additionally, we find Appellants’ argument focusing on the type of
slot (i.e., not intended or configured for the flash cache) unpersuasive. It is
well settled that “it is not necessary that the inventions of the references be
physically combinable to render obvious the invention under review.” In re
Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983). The relevant inquiry is
whether the claimed subject matter would have been obvious to those of
ordinary skill in the art in light of the combined teachings of Peters and
TotalStorage. See In re Keller, 642 F.2d 413, 425 (CCPA 1981)
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(“Combining the teachings of references does not involve an ability to
combine their specific structures.”); In reNievelt, 482 F.2d 965, 968 (CCPA
1973). In addition, we are not persuaded that combining Peters and
TotalStorage’s teachings in the manner proffered by the Examiner is
“uniquely challenging or difficult for one of ordinary skill in the art.” See
Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir.
2007) (citing KSR Int 7 Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007)); see
also KSR, 550 U.S. at 420 (“[I]n many cases a person of ordinary skill will
be able to fit the teachings of multiple patents together like pieces of a
puzzle.”).
(2) Cache data associated with data requests handled through the
I/O enclosure
Appellants argue that “[njeither TotalStorage nor Peters teach using
the ‘Flash Cache card’ for the purpose recited in claim 1, namely to ‘cache
data associated with data requests handled through the I/O enclosure.’”
App. Br. 11. Appellants further argue “it would not necessarily be obvious
to use the combination to ‘cache data associated with data requests handled
through the I/O enclosure.’” Id.
The Examiner finds, and we agree, the combination of Peters and
TotalStorage teaches or suggests the disputed limitation. See, e.g., Ans. 5.
Specifically, the Examiner finds, and we agree, Peters teaches or suggests
the Flash Cache card caches data associated with data requests handled
through the I/O enclosure. See Ans. 4—5 (citing Peters 6 (NAND flash-based
Flash Cache that “read caches for the storage controller” and “cache[s]
metadata and user data with the aim of avoiding disk reads and the added
latency and limited IO throughput that result from such reads”)).
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CONCLUSION
Based on our findings above, we sustain the Examiner’s rejection of
claims 1, 13, and 16. We also sustain the Examiner’s rejections of claims 2—
7, 10-12, 14, 15, 17, and 18, as Appellants did not provide separate
arguments for their patentability.
DECISION
We affirm the Examiner’s decision rejecting claims 1—7 and 10—18
under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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