Ex Parte Ananda Ganesan et al

Patent Trial and Appeal Board

Jan 31, 2017

13384739 (P.T.A.B. Jan. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/384,739 01/18/2012 Senthil- Kumar Ananda Ganesan 82852880 1043
56436 7590
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
BROCKMAN, ANGEL T
ART UNIT PAPER NUMBER
2463
NOTIFICATION DATE DELIVERY MODE
02/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
hpe.ip.mail@hpe.com
chris. mania @ hpe. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SENTHIL-KUMAR ANANDA GANESAN, VASAVI SAGI, and
ANURADHA ANANTHA PADMANABHA
Appeal 2016-002159
Application 13/384,7391
Technology Center 2400
Before ROBERT E. NAPPI, CARL L. SILVERMAN, and SCOTT E.
BAIN, Administrative Patent Judges.
BAIN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—4, 7, 8, 10, 11, and 14—20. We have jurisdiction
under 35 U.S.C. § 6(b).
We affirm-in-part.
1 Appellants identify Hewlett-Packard Development Company, LP and
Hewlett-Packard Company as the real parties in interest. App. Br. 2.
Appeal 2016-002159
Application 13/384,739
STATEMENT OF THE CASE
The claimed invention relates to improving storage automation and
reliability, by creating redundancies in the logical connections between a
host and its storage logical units. Spec. Tflf 2, 12. With such redundancies,
the failure of one logical link is less likely to completely sever the logical
unit from the host. Id. Claims 1, 8, and 11 are independent. Claim 1 is
illustrative of the invention and the subject matter of the appeal, and reads as
follows (with the disputed limitations in italics):
1. A method for creating redundant logical connections,
comprising:
providing a physical connection topology and a logical
connection topology between a host and a logical unit hosted on
a storage array, said physical connection topology and said
logical connection topology comprising all network fabrics to
which both said host and said storage array belong;
determining at least one single point of failure is located
between said host and said logical unit within a particular
network fabric;
attempting to create a fully redundant logical connection
between said host and said logical unit within said particular
network fabric;
if a fully redundant logical connection is not possible in
said particular network fabric, attempting to create a fully
redundant logical connection between said host and said logical
unit using an alternate of said network fabrics', and
if a fully redundant logical connection is not possible in
any alternate network fabric in said topologies, attempting to
create a partially redundant logical connection between said host
and said logical unit within said particular network fabric.
App. Br. 20 (Claims App.).
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Appeal 2016-002159
Application 13/384,739
THE REJECTIONS ON APPEAL
Claims 8 and 16—18 stand rejected under pre-AIA 35 U.S.C. § 102(b)
as anticipated by Thrasher et al. (US 7,275,103 Bl; Sept. 25, 2007)
(“Thrasher”). Final Act. 3^4.
Claims 1—4, 7, 10, 11, 14, 15, 19, and 20 stand rejected under pre-AIA
35 U.S.C. § 103(a) as unpatentable over Thrasher and Desai et al. (US
7,801,859 Bl; Sept. 21, 2010) (“Desai”). Final Act. 4-10.2
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments presented in this appeal. Arguments which Appellants could
have made but did not make in the Briefs are deemed to be waived. See
37 C.F.R. § 41.37(c)(l)(iv). On the record before us, we are persuaded the
Examiner erred in rejecting claims 11, 14, and 15. As to the remaining
claims on appeal, we are not persuaded the Examiner erred, and we adopt as
our own the findings and reasons set forth in the rejections from which the
appeal is taken and in the Examiner’s Answer. We provide the following for
highlighting and emphasis.
35 U.S.C. § 102(b) Rejection
Appellants argue the Examiner erred in finding Thrasher discloses
“discovery of a single point of failure in said at least one logical
2 The Examiner withdrew the rejection of claims 5, 6, 9, 12, and 13 in the
Answer. Ans. 2. Those claims remain objected to as being dependent upon
a rejected base claim, but would be allowable if rewritten in independent
form including all of the limitations of the base claim and any intervening
claims. Id.
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Appeal 2016-002159
Application 13/384,739
connection,” as recited in independent claim 8. App. Br. 10-14; Reply Br.
4—10. Although Appellants concede Thrasher discloses “look[ing] for a
better, alternative path” between a host and logical unit, Appellants contend
a problem “path” is not a “single point of failure.” App. Br. 7—8.
Appellants’ argument, however, does not persuade us of error.
Thrasher discloses an “automatic” identification of a path that falls
below a “quality of service threshold,” which, as the Examiner finds, one of
ordinary skill would understand could include a disconnection between host
and logical unit. Thrasher col. 5,11. 13—20, 40-42; Ans. 3^4. According to
the disclosure of Thrasher, when such a “problem path” is identified, it may
be replaced by creating a “redundant path.” Thrasher col. 5,11. 9—20.
Appellants attempt to distinguish the “paths” in Thrasher from a “single
point of failure,” Reply 8, but as the Examiner finds, one of ordinary skill
would understand that if a logical path has failed (dropped below a specified
service level), then it has been discovered that there is at least one single
point of failure along that path. Ans. 3. To the extent Appellants imply
Thrasher does not identify precisely where the single point of failure is,
along the path, claim 8 (unlike claim 11 as discussed below) does not recite
that requirement.
Appellants do not argue claims 16—18 (which depend from claim 8)
separately. Accordingly, we sustain the rejection of claims 8 and 16—18
under pre-AIA 35 U.S.C. § 102(b) as anticipated by Thrasher.
35 U.S.C. § 103(a) Rejection
Regarding independent claim 1, Appellants argue the Examiner erred
in finding Thrasher teaches “determining at least one single point of failure.”
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Application 13/384,739
App. Br. 16—18. We are not persuaded by this argument, for the same
reasons discussed above in the context of claim 8.
Appellants further argue the Examiner erred in rejecting claim 1
because, according to Appellants, neither Thrasher nor Desai teach “if a
fully redundant logical connection is not possible in said particular network
fabric, attempting to create a fully redundant logical connection . . . using an
alternate of said network fabrics.” App. Br. 18—19; Reply Br. 13—14. In the
Answer, however, the Examiner construes this limitation as having no
patentable weight, because the “term ‘if implies the subject matter which
follows is optional.” Ans. 4. We agree with the Examiner’s construction.
See Ex parte Schulhauser, Appeal 2013-007847, slip op. 6—10 (PTAB April
28, 2016) (precedential) (A “conditional limitation in a method claim [is]
afford[ed] ... no patentable weight.”). Accordingly, we do not reach
Appellants’ arguments regarding the teachings of Thrasher or Desai related
to this limitation (as well as the final claim limitation, which is also
conditional).
Appellants do not argue the claims depending from claim 1
separately. For the foregoing reasons, we sustain the rejection of claim 1
and its dependent claims 2-4, 7, 19, and 20 under pre-AIA 35
U.S.C. § 103(a) as unpatentable over Thrasher and Desai.
Regarding independent claim 11 (and its dependent claims), however,
we are persuaded by Appellants’ argument the Examiner erred. Claim 11,
unlike independent claims 1 and 8, recites “determining where a single point
of failure is located between a host and a logical unit.” App. Br. 28 (Claims
App.). The Examiner does not address this distinction in the Answer (and
does not address claim 11 separately), and we discern no finding in the
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Application 13/384,739
record regarding where the prior art teaches this limitation. In the Final
Office Action, the Examiner cites Thrasher Figure 3 A as teaching this
limitation, but Figure 3A is merely a high level block diagram illustrating
paths between a host and logical unit and does not suggest “where” a single
point of failure may be “located.” Final Act. 8.
Accordingly, we do not sustain the rejection of claim 11 and its
dependent claims 14 and 15 under pre-AIA 35 U.S.C. § 103(a) as
unpatentable over Thrasher and Desai.
DECISION
We AFFIRM the Examiner’s rejections of claims 1—4, 7, 8, 10, and
16-20.
We REVERSE the Examiner’s rejections of claims 11,14 and 15.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 41.50(f).
AFFIRMED-IN-PART
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