Ex Parte 8250295 et al

Patent Trial and Appeal Board

Nov 10, 2016

95002399 (P.T.A.B. Nov. 10, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

NETLIST, INC.
Requester

v.

Patent of SMART MODULAR TECHNOLOGIES, INC.
Patent Owner
____________________

Appeal 2017-010752
Reexamination Control No. 95/002,399
Patent No. 8,250,295 B2
Technology Center 3900
__________________

Before JEFFREY B. ROBERTSON, DENISE M. POTHIER, and
JEREMY J. CURCURI, Administrative Patent Judges.

Opinion for the Board filed by Administrative Patent Judge DENISE M.
POTHIER.

Opinion Dissenting-in-Part filed by Administrative Patent Judge JEREMY J.
CURCURI.

POTHIER, Administrative Patent Judge.

DECISION UNDER 37 C.F.R. § 41.77(f)
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I. STATEMENT OF CASE
In an earlier Decision (“Dec.”) mailed November 14, 2016, we reversed the
Examiner’s decision confirming claims 1–7 of U.S. Patent No. 8,250,295 (the ’295
patent) and determining claims 9, 13, 15, 19, and 22 of the ’295 patent are
patentable. Dec. 31, 33. We presented rejections against claims 1–7, 9, 13, 15, 19,
and 22, designating these rejections as new grounds. Id. at 31–33. Patent Owner
elected to reopen prosecution before the Examiner pursuant to 37 C.F.R.
§ 41.77(b)(1) (“PO Response”), submitting claim amendments and a Second
Supplemental Declaration of William Slemmer, dated January 23, 2017 (“2d Supp.
Slemmer Decl.”). Requester filed comments under 37 C.F.R. § 41.77(c) dated
February 24, 2017 (“3PR Comments”). On April 11, 2017, Patent Owner’s request
to reopen prosecution for consideration of claims 1–7, 9, 13, 15, 19, and 22 was
granted and the proceeding was remanded to the Examiner. Order 4–5.
On remand, the Examiner maintained the rejections of claims 1–7, 9, 13, 15,
19, and 22 in the “Determination Under 37 C.F.R. 41.77(d)” (Ex. Deter.) mailed
May 8, 2017. Ex. Deter. 5–8, 21. Patent Owner submitted comments (“PO
Comments”) as set forth in 37 C.F.R. § 41.77(e) on June 8, 2017. Requester
submitted a reply (“3PR Reply”) to the Patent Owner’s comments as set forth in 37
C.F.R. § 41.77(e) on July 10, 2017.
This proceeding has been returned to the Board under 37 C.F.R. § 41.77(f).
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Claim Status
Claims 1–7, 9, 13, 15, 19, and 22 are subject to reexamination. App. Br. 1;
RAN 1–2.1 Our new Decision is deemed to incorporate our earlier Decision,
except for any portion specifically withdrawn. 37 C.F.R. § 41.77(f).
Illustrative, original claim 1 reads as follows:
1. A memory module connectable to a computer system, the
memory module comprising:
a board;
a plurality of double-data-rate (DDR) memory devices mounted
to the board, the plurality of DDR memory devices arranged in a first
number of ranks;
a circuit that is coupled to said board and that receives from the
computer system a set of input control signals that includes a set of
first chip select signals and an address signal and that generates a set
of second chip select signals based at least in part upon values of said
set of first chip select signals and a portion of the address signal;
wherein a number of chip select signals of the set of second
chip select signals corresponds to a first number of DDR memory
devices arranged in the first number of ranks;
wherein a number of chip select signals of the set of first chip
select signals corresponds to a second number of DDR memory
devices arranged in a second number of ranks, the second number of
DDR memory devices smaller than the first number of DDR memory
devices and the second number of ranks less than the first number of
ranks;
wherein at least one signal of the set of second chip select
signals has a value to selectively activate a respective rank of the first
number of ranks;
wherein the circuit provides one or more of the received set of
input control signals to said at least one respective activated rank;
wherein the set of input control signals further includes RAS,
CAS, WE, BA;
wherein the circuit includes an emulator and a register; and

1 Requester’s Appeal Brief (App. Br.) was filed November 4, 2015, and the
Examiner’s Right of Appeal Notice (RAN) was mailed August 4, 2015.
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wherein the emulator receives from the computer system at
least a portion of the set of input control signals that includes RAS,
CAS, WE, the set of first chip select signals and the portion of the
address signal;
wherein the emulator generates the set of second chip select
signals in response to the at least a portion of the set of input control
signals received by the emulator;
wherein the register receives at least another portion of the set
of input control signals that includes RAS, CAS, WE, BA and the
remaining portion of the address signal; and
wherein the register provides one or more of the input control
signals received by the register to said at least one respective activated
rank.

PO Response 4–5.

Prior Art
The following evidence of unpatentability is relevant to the rejections
presented in the November 14, 2016 Decision:
Takeda JP H10-320270 Dec. 4, 1998

JEDEC Standard No. 21-C, PC2100 and PC1600 DDR SDRAM Registered DIMM
Design Specification, Release 11b, Rev. 1.3, pages 4.20.4-1–4.20.4-82 (Jan. 2002)
(“JEDEC 21-C”).

JEDEC Solid State Technology Association, JEDEC Standard, Double Data Rate
(DDR) SDRAM Specification, JESD79C (Revision of JESD79B) 1-75 (Mar. 2003)
(“JEDEC 79C”).

Hynix Semiconductor, 128Mx72 bits Registered DDR SDRAM DIMM
HYMD512G726(L)8-K/H/L Rev 0., 1-16 (May 2002) (“Hynix”).

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The following Declarations are presented in this proceeding:
Declaration of Dr. Edward P. Sayre Pursuant to 37 C.F.R. § 1.132 dated
April 25, 2013 (Sayre Decl.),
Second Supplemental Declaration of Dr. Edward P. Sayre Pursuant to 37
C.F.R. § 1.132 dated February 23, 2017 (2d Supp. Sayre Decl.),
Declaration of William Slemmer Under 37 C.F.R. § 1.132 dated March 26,
2013 (Slemmer Decl.),
Declaration of William Slemmer Under 37 C.F.F. § 1.132 dated May 29,
2014 (Supp. Slemmer Decl.), and
Second Supplemental Declaration of William Slemmer Under 37 C.F.R.
§ 1.132 dated January 23, 2017 (2d Supp. Slemmer Decl.).

Maintained Rejections
In the Examiner’s Determination, the Examiner maintains the following new
grounds of rejection:
References Basis Claims Presented/Maintained
Takeda and
JEDEC 21-C
§ 103(a) 1–7
Dec. 18–26;
Ex. Deter. 5, 212
Takeda and Hynix § 103(a) 1–7
Dec. 18–26;
Ex. Deter. 5, 21

2 Like Patent Owner, we assume the rejection of Takeda and JEDEC 21-C (Ground
1) is being maintained. PO Comments 1 n.1. That is, although the Examiner does
not list Takeda and JEDEC 21-C as a maintained rejection (Ex. Deter. 5, 21), the
determination addresses JEDEC 21-C throughout its discussion. See, e.g., id. at 9
(discussing the rejections do not rely on Takeda alone but are combined with
JEDEC 21-C, Hynix, and JEDEC 79C), 12 (stating Patent Owner is incorrect that
Takeda cannot be combined with JEDEC 21-C).
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Takeda/JEDEC 21-C,
and JEDEC 79C
§ 103(a)
9, 13, 15, 19,
and 22
Dec. 26–27;
Ex. Deter. 5, 21
§ 112 ¶ 1 9, 13, and 22
Dec. 27—30; Ex.
Deter.
5–8, 21

II. ISSUES
We review the new grounds of rejection based upon the issues identified by
Patent Owner in its request to reopen and comments on the Examiner’s
Determination, and in light of new evidence and arguments thereto. Cf. Ex parte
Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential) (citing In re Oetiker, 977
F.2d 1443, 1445 (Fed. Cir. 1992)).
The main issue is whether Patent Owner has provided sufficient arguments
and evidence to overcome the new grounds of rejection for claims 1–7, 9, 13, 15, 19,
and 22 presented in the November 14, 2016 Decision.

III. ANALYSIS
A. Claim Construction
1. “A [S]et of [F]irst [C]hip [S]elect [S]ignals” Recited in Claim 1
In the earlier Decision, we construed the above phrase in claim 1 to mean
“multiple first chip select signals in light of the claims, the ’295 patent’s
disclosure, the prosecution history of the ’295 patent, the expert testimony of how
one skilled in the art would have understood this term, and the ordinary meaning of
the word ‘set.’” Dec. 18. Patent Owner and Requester have not commented on
this construction. We maintain this claim interpretation for purposes of this new
Decision.
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Furthermore, claims 1–7, 9, 13, 15, 19, and 22 do not require the signals in
the recited “set of first chip select signals” to have different values. Ex. Deter. 18.

B. The Rejections
1. Takeda and (a) JEDEC 21-C or (b) Hynix
The Examiner maintains the rejection of claims 1–7 based on Takeda and (a)
JEDEC 21-C or (b) Hynix under 35 U.S.C. § 103 as presented in the earlier
Decision. Ex. Deter. 5, 21; see also Dec. 16–26.
Patent Owner reasserts that Takeda only discloses a single chip select signal
and fails to teach the recited “set of first chip select signals” in claim 1. PO
Response 10–17; PO Comments 4–23. Patent Owner also repeats that Takeda’s
/S0 and /S2 in Figure 2 cannot have different values, which purportedly
demonstrates that these components are a single chip select signal. PO Response
26–29; PO Comments 8.
In Patent Owner’s Comments related to the Examiner’s Determination,
Patent Owner further presents a procedural argument that
[G]iven the ambiguity of where the signals carried on wires /S0 and
/S2 emanate from, the Examiner cannot say that it is more likely than
not that /S0, /S2 in fact derive from different sources and therefore
constitute two separate signals. It is at least as likely (if not more so)
that /S0 and /S2 derive from a common source and therefore represent
a single signal . . . . [T]hen as a matter of law the Board/Examiner
cannot make out a prima facie of obviousness by a preponderance of
the evidence based on Takeda.

PO Comments 10 (bolding and emphasis omitted); see also id. at 10–12.
Upon consideration of the new evidence and arguments, Patent Owner has
not demonstrated that Takeda’s /S0 and /S2 are a single, drive signal. Dec. 20
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(citing Takeda ¶¶ 11–12 and Sayre Decl. ¶ 56). At the outset, we agree with
Requester that our discussion in our previous Decision related to the possibility of
/S0 and /S2 having different values is not critical to our conclusion that Takeda
teaches or suggests the recited “set of first chip select signals” as recited in claim 1.
3PR Reply 3–4 (quoting PO Comments 7). As such, to any extent our previous
Decision may be interpreted as improperly shifted the burden on Patent Owner to
demonstrate Takeda’s /S0 and /S2 cannot have different values (see PO Response
21–22), this particular statement does not undermine the overall determination that
Takeda teaches or suggests claim 1’s disputed “set of first chip select signals”
because the claims do not require the chip select signals to have different values.
We reiterate that determining “two signals having the same value does not
persuasively demonstrate that [Takeda’s] signals are in fact a single chip select
signal; rather, they are two chip select signals which have the same value in the
timing chart of Figure 3.” Dec. 23. For example, Requester highlights our
previous Decision indicates that Takeda teaches and suggests /S0 and /S2 are both
drive signals and Patent Owner does not discredit this specific finding. 3PR
Comments 8 (citing Dec. 20), 10. The Examiner repeats the Requester’s position
and concludes both /S0 and /S2 are drive signals. Ex. Deter. 10 (citing Dec. 19–
20, Sayre Decl. ¶ 56, and Takeda ¶ 123). Thus, even assuming Patent Owner is
correct that /S0 and /S2 must always have the same value (see e.g., PO Response
14; PO Comments 18), this evidence does not sufficiently demonstrate error
determining Takeda’s /S0 and /S2 are separate chip select signals (i.e., “a set of
first chip select signals” as recited in claim 1) with the same values.

3 The Examiner cites to Takeda 6:38–39, which is contained within Takeda ¶ 12.
We will refer to Takeda’s paragraph numbers throughout this opinion.
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We also stated in our previous decision Takeda does not show the source of
/S0 and /S2. Dec. 21 (stating “[n]or does Takeda’s Figure 2, or any other figure for
that matter, show the existing connections and circuitry prior to receiving the drive
signals . . . .”) Patent Owner focuses on this finding, asserting that “it cannot be
known with certainty whether /S0 and /S2 derive from a single source or multiple
sources.” PO Comments 9. However, the test for obviousness does not require
“certainty.” Id. Rather, “there must be some articulated reasoning with some
rational underpinning to support the legal conclusion of obviousness.” In re Kahn,
441 F.3d 977, 988 (Fed. Cir. 2006). That is, an obviousness “analysis need not
seek out precise teachings directed to the specific subject matter of the challenged
claim, for [the Office] can take account of the inferences and creative steps that a
person of ordinary skill in the art would employ.” KSR Int’l Co. v. Teleflex Inc.,
550 U.S. 398, 418 (2007).
In the previous Decision, we stated “Figure 2 shows two inputs, /S0 and /S2,
at the bottom left of the figure.” Dec. 19. That is, Takeda’s Figure 2 teaches and
suggests to an ordinarily skilled artisan each of /S0 and /S2 are distinct, drive
signals. See Takeda, Fig. 2. Additionally, the rejection further relies on Figure 2
and Takeda’s discussion of every other input as a drive signal (see Takeda ¶ 12) in
determining that each of /S0 and /S2 would have been recognized by ordinarily
skilled artisans as a distinct drive signal. Dec. 20 (citing Sayre Decl. ¶ 56) (stating
“one skilled in the art would have appreciated /S0 and /S2 are drive signals
covered by ‘etc.’” in Takeda).
In response to Mr. Slemmer’s testimony related to signal fan-out (id. at 21
(citing Slemmer Decl. ¶ 53)), we noted in the previous Decision that “Takeda does
not discuss /S0 and /S2 are the result of fanning out a single signal to reduce
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loading” as asserted (id. at 21) in determining that Takeda’s /S0 and /S2 at least
teach or suggest to one skilled in the art two distinct signals. However, even
presuming without agreeing that /S0 and /S2 are the result of fanning out, these
signals function as two chip select signals. See Takeda, Fig. 2; see also Sayre
Decl. ¶ 56 (discussing one skilled in the art would have understood Takeda’s rank
selection happens using chip select signals CS0–CS7, which are generated in
response to two first chip select signals S0 and S2). Moreover, the claims do not
place any restriction on the source of the chip select signals. PO Response 4–8.
As such, we have articulated reasons with some rational underpinning to
conclude Takeda’s /S0 and /S2 are two chip select signals. The Examiner agrees.
Ex. Deter. 10–11. Additionally, as Requester indicates, the argument concerning
In re Rijckaert, 9 F.3d 1531 (Fed. Cir. 1993) and Par Pharmaceutical, Inc. v. TWI
Pharmaceuticals, Inc., 773 F.3d 1186, 1195-96 (Fed. Circ. 2014) (PO Comments
10–11) is misplaced. 3PR Reply 6–7. In particular, the obviousness rejection
relies on what Takeda teaches and suggests to one skilled in the art and not the
concept of inherency to demonstrate some assumed, claimed relationship. Dec.
19–24.
Takeda and JEDEC 21-C collectively include an additional basis for
supporting that one skilled in the art would have recognized Takeda’s /S0 and /S2
inputs are two distinct signals. Requester states the newly presented evidence,
JEDEC 21-C, chapter 4.20.24, concerning non-DDR SDRAM (synchronous

4 JEDEC Standard 21-C, PC133 SDRAM Registered DIMM Design Specification,
Release 11a, Rev. 1.4, pages 4.20.2.1–4.20.2.75 (Feb. 2002). Patent Owner labels
this evidence Exhibit A. PO Response, Ex. A. For purposes of this decision, we
refer to this exhibit as JEDEC 21-C, chapter 4.20.2 but cite to its specific pages
using JEDEC 21-C, p. 4.20.2-X.
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dynamic random-access memory) DIMMs (Dual In-line Memory Modules),
demonstrates /S0 and /S2 are received from the computer system on two separate,
register pins #30 and #45. 3PR Comments 10 (citing JEDEC 21-C, p. 4.20.2-8 and
2d Supp. Sayre Decl. ¶¶ 16–18); see also JEDEC 21-C, p. 4.20.2-10. The
Examiner echoes Requester’s position. Ex. Deter. 11. This exhibit suggests to one
skilled in the art that Takeda’s /S0 and /S2, given JEDEC 21-C’s SDRAM DIMM
Pinout table, are separate signals entering distinct register locations through two
separate DIMM pins (i.e., #30 and #45). See 3PR Comments 10 and 3PR Reply
17–18; 2d. Supp. Sayre Decl. ¶¶ 16–18; Micron 5.5
Concerning this new evidence, Patent Owner contends pins and wires “are
[not] the same as signals. Signals come in a variety of forms and are only one type
of content that may be carried on wires or applied to pins in an integrated circuit.”
PO Comments 8. Although we agree that pins and wires are not the same as
signals, pins and wires carry signals. Moreover, Patent Owner does not provide
evidence or clarify what other “type of content . . . may be carried on wires or
applied to pins” other than signals. See id. Patent Owner further contends that
separate pins does not mean the inputs represent separate signals, essentially
because the nomenclature “S0/S2” purportedly means these signals have the same
value. PO Response 30–31. For the above reasons, we are not persuaded.
Patent Owner further states that “[i]t is common JEDEC nomenclature to
refer to multiple inputs that can potentially have different values by use of ‘-’. For
example, signals BA0 and BA1 may each have different values and are therefore

5 Micron, Inc., 128MB/256MB(x72) 168-PIN REGISTERED SDRAMS DIMMs
SYCHRONOUS DRAM MODULE 1-24 (2002). Patent Owner labels this evidence,
Exhibit B. PO Response, Ex. B. For purposes of this decision, we refer to this
exhibit as Micron.
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designated ‘BA0-BA1’. That is in contrast with the signal of S0 and S2 which must
have the same value and is therefore designated ‘S0/S2’.” PO Comments 16
(citing 2d Supp. Slemmer Decl. ¶ 38). Patent Owner later contends “[o]ne skilled
in the art would understand that the nomenclature /S0, /S2 is used in Takeda to
represent a single signal value provided on two unconnected lines” and “the
JEDEC 21-C, 4.20.2 SDRAM specification, which is applicable to Takeda, shows
a single ‘S0/S2’ signal having one value.” PO Response 26–27 (citing 2d Supp.
Slemmer Decl. ¶¶ 36–38 and Micron 1). We are not persuaded.
Mr. Slemmer testifies that “[i]t was well known to use different names, such
as ‘S0’ and ‘S2’, to represent a single signal value provided on two unconnected
lines” and refers to JEDEC 21-C as evidence for this testimony. 2d Supp.
Slemmer ¶ 36 (citing JEDEC 21-C, chap. 4.20.2); see id. at ¶¶ 36–38. Yet the
annotated, partial view of the register shown in JEDEC 21-C, p. 4.20.2-10 and
reproduced by Patent Owner (PO Response 13) does not describe or show S0 and
S2 inputs are as asserted, such that one skilled in the art would have concluded that
their values must be the same and represent a single signal. JEDEC 21-C, p.
4.20.2-10. For example, one skilled in the art may recognized the “-” in JEDEC
21-C is used to indicate sequential series of values (e.g., BA0 and BA1 as “BA0-
BA1”), whereas the “/” is used to indicate two signals that are not sequential (e.g.,
“S0/S2” excludes S1). See id. Granted, JEDEC 21-C, chapter 4.20.4, addressing
DDR SDRAM technology, shows S0 and S1 as two separate lines entering the
register. PO Response 15–16 (citing JEDEC 21-C, p. 4.20.4-16). But, this same
Block Diagram also depicts other series signals, such as BA0-BA1, entering as one
line even though they are multiple signals. JEDEC 21-C, p. 4.20.4-16.
Furthermore, as both Requester and the Examiner indicate, the registers shown in
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JEDEC 21-C and Micron are only show “a functional ‘Block Diagram,” and do not
show the signal-level detail. 3PR Comments 14 (citing 2d Supp. Sayre Decl. ¶ 17);
see also Ex. Deter. 13-14. Because the nomenclature does not appear to be
consistent in these diagrams in JEDEC 21-C, we determine this evidence is
inconclusive to demonstrate that the “/” on page 4.20-10 is a single signal.
On the other hand, Micron’s “Address Table” of a non-DDR SDRAM
technology labels both (1) BA0 and BA1 (e.g., “BA0, BA1”) and (2) S0 and S2
(e.g., “S0, S2”) with a “,”. Micron 1. Patent Owner does not dispute that the bank
address signals (e.g., BA0 and BA1) are separate and distinct signals. See
generally PO Response. As such, Micron suggests to one skilled in the art that, in
non-DDR technology, S0 and S2 are like BA0 and BA1—namely, each is a
separate and distinct signals.
Finally, Dr. Banerjee’s testimony6 states Takeda describing /S0 and /S2 as
two chip select signals is accurate. See Banerjee’s Decl. ¶¶ 7, 12.
Based on the entire record, the evidence demonstrating Takeda’s /S0 and /S2
are two chip select signals outweighs the evidence presented asserting that /S0 and
/S2 are a single chip select signal. We thus disagree that there is “no basis to
conclude that the preponderance of evidence” supports an obviousness rejection
based on Takeda. PO Comments 10.
Moreover, as indicated by Requester and the Examiner, the maintained
rejections are not based solely on Takeda and further rely on JEDEC 21-C or

6 Smart Modular Techs., Inc. v. Netlist, Inc., Case No. 2:12-CV-023319-MCE-EFB
(E.D. Ca.), Document 87, BANERJEE DECLARATION IN SUPPORT OF
DEFENDANT NETLIST INC.’S OPPOSITION TO PLAINTIFF’S MOTION
FOR PRELIMINARY INJUNCTION. Patent Owner labels this evidence, Exhibit
C. PO Response, Ex. C. For purposes of this decision, we refer to this exhibit as
the Banerjee’s Declaration or Banerjee’s Decl.
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Hynix in rejecting claim 1. See 3PR Comments 9; see also Ex. Deter. 9. Granted,
Hynix and portions of JEDEC 21-C (e.g., Chapter 4.20.4) discuss DDR SDRAM
technology, which is not the same as Takeda’s non-DDR SDRAM technology.
See PO Response 11–12 (citing 2d Supp. Slemmer Decl. ¶¶ 15, 18–19); see also
3PR Comments 9 (citing 2d Supp. Sayre Decl. ¶ 13 and stating “DDR was
provided in 2000” after this 1997 publication). However, as noted above, some
non-DDR SDRAM evidence suggests to one skilled in the art that Takeda’s /S0
and /S2 are two distinct signals. See, e.g., Micron 1. On other hand, as previously
explained, other non-DDR SDRAM evidence does not sufficiently demonstrate
that Takeda’s /S0 and /S2 are a single signal. See, e.g., JEDEC 21-C, p. 4.20.2-
10).
Even more, Jacob,7 which cited in Dr. Sayre’s Second Supplemental
Declaration, explains DDR DRAMS “are very similar to single data rate [] in all
other characteristics” than “DDR doubles the data bandwidth available from single
data rate SDRAM.” Jacob 7, § 1.3.1, cited in 2d Supp. Sayre Decl. ¶ 14; see also
3PR Comments 11–13 (referring to 2d Supp. Sayre Decl. ¶ 14). Jacob describes
such “very similar[,] . . . other characteristics” include the same signaling
technology, the same interface specification, and the same pinouts on the DIMM
carriers. Jacob 7, § 1.3.1. Thus, an ordinarily skilled artisan would have
recognized that the immediately above-noted concepts and principles concerning
DDR SDRAM are applicable to and suitable for SDR (single data rate) SDRAM,

7 Bruce L. Jacob, Synchronous DRAM Architectures, Organizations, and
Alternative Technologies, University of Maryland 1–22 (2002), available at
https://www.ece.umd.edu/~blj/CS-590.26/references/DRAM-Systems.pdf (last
visited October 21, 2017).
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such as Takeda’s non-DDR SDRAM technology. Patent Owner’s argument to the
contrary are unavailing. PO Comments 33–36.
We thus disagree with Patent Owner and Mr. Slemmer (2d Supp. Slemmer
¶¶ 30–34, 44) that Takeda and JEDEC 21-C or Hynix are not interchangeable for
purposes of teaching signaling technology, interface specifications, or pinout on
the DIMM carrier or that one skilled in the art would not have looked to DDR
technology for additional teachings. See PO Response 12 (arguing the references
are not interchangeable or substitutable), 14 (arguing an artisan would not look to
DDR technology when designing or modifying a non-DDR SDRAM memory
device), and 14–17 (arguing Takeda cannot be combined with the DDR SDRAM
Specification of JEDEC 21-C); see also PO Comments 14–17 (arguing Takeda
cannot be combined with JEDEC 21-C), 33–36. Although Takeda addresses
non-DDR technology, we agree with Requester and the Examiner that one skilled
in the art at the time of the invention would have recognized Takeda is not limited
to non-DDR technology and would have looked to DDR SDRAM technologies for
its characteristics that are very similar to non-DDR technology (e.g., signaling,
interface specification, and pinouts). See 3PR Comments 11–13 (citing Takeda
¶ 17; Request8, Exs. 18 and 19, p. 2; and 2d Supp. Sayre Decl. ¶¶ 10, 13, 14); see
also Ex. Deter. 12–14, 17 and 3PR Reply 16–17.
We further disagree that the rejections use impermissible hindsight as argued
by Patent Owner or that there is no reason to combine Takeda with JEDEC 21-C or
Hynix. PO Response 16; PO Comments 33–37. We agree with the Examiner and
Requester that the obviousness rejections do not solely rely on Takeda and that one
skilled in the art, employing their background knowledge, would have further look

8 See Request for Inter Partes Reexamination filed Sept. 15, 2012 (“Request”).
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to JEDEC 21-C, Hynix, and JEDEC 79C to arrive at the memory module recited in
claim 1. See Ex. Deter. 9–10; see also 3PR Comments 17–18.
Additionally, we agree with Requester that Dr. Sayre’s comments regarding
Takeda’s Figure 4 or any alleged modification to Figure 4 (see, e.g., PO Comments
37) are not part of the obviousness rejections or how Takeda is modified in the
maintained rejections. See Dec. 18–26 (referring to Non-Final Act. 5–179 and
Request 24–26, Ex. 18). Instead, this discussion is used to assert Takeda’s /S0 and
/S2 are two chip select signals as recited. 3PR Comments 19–20 (citing Sayre
Decl. ¶¶ 42–46) and 3PR Reply 15–16; see also Ex. Deter. 19–20. Also, because
these arguments related to Figure 4 (see PO Comments 24–33) are not in response
in the Examiner’s determination, we also agree that the arguments concerning this
purported combination changing Takeda’s principle of operation are improper. See
37 C.F.R. §41.77(e), cited in 3PR Reply 16.
We disagree that combining DDR SDRAM technology with non-DDR
teachings, such as Takeda, would have destroyed Takeda’s principle of operation
to be a SDRAM having memory storage devices or otherwise render Takeda
unsatisfactory for its intended purpose. PO Response 29–31; PO Comments
23–33. In contrast, Jacob demonstrates that one skilled in the art would have
recognized many similar characteristics between non-DDR and DDR technology,
such that an artisan would have looked to DDR SDRAM teachings concerning
signaling, interface specifications, and pinouts and apply such teachings to Takeda.
See Jacob 7, cited in 2d Supp. Sayre Decl. ¶ 14.
Patent Owner also argues Takeda’s Figures 2 and 3 are inoperable and not
enabled. PO Response 17–26; PO Comments 23–33. Specifically, Patent Owner

9 See Non-Final Office Action mailed Dec. 7, 2012 (“Non-Final Act.).
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contends “Takeda’s Figure 2 circuitry does not and cannot use /S0 and /S2 to select
a particular bank of SDRAM memory” (PO Response 18) but rather would select
all or no banks (id. at 20–21). Patent Owner further contends Figure 2’s AND and
NAND gates do not yield the described results. Id. at 19–20 (citing Takeda
6:36–7:6, Fig. 3 and 2d Supp. Slemmer Decl. ¶¶ 59–61). Even more, Patent
Owner argues the solutions provided by Requester’s experts demonstrate “making
the Takeda bank control unit workable is far from trivial” and “insurmountable.”
Id. at 23; see also id. at 20–23 (citing Banerjee Decl. ¶ 14, Sayre Decl. ¶¶ 64–67,
2d Supp. Sayre Decl. ¶¶ 69–70). Patent Owner asserts that six out of the eight
CS0-CS7 values in each of periods 2, 5, 8, and 11 in Figure 3 are illegal commands
under JEDEC 21-C. Id. at 23–26 (citing Takeda 7:8–13, 2d Supp. Slemmer Decl.
¶¶ 75–84, and JEDEC 21-C, p. 3.11.5-510,11).
Regardless of Takeda’s flaws, we agree with the Examiner and Requester
that Takeda is good for all that it teaches. Ex. Deter. 16 (quoting Beckman
Instruments v. LKB Produkter AB, 892 F.2d 1547, 1551 (Fed. Cir. 1989)); see also
3PR Comments 16. As such, even if Figures 2 and 3 of Takeda do not match the
accompanying description to activate a bank as testified (see 2d Supp. Slemmer
Decl. ¶¶ 59–62 and Banerjee’s Decl. ¶ 14, both cited in PO Response 19–21; see
also 2d Slemmer Decl. ¶¶ 75–84, cited in PO Response 23–26), Takeda should not

10 JEDEC Standard 21-C, SDRAM Architectural and Operational Features,
Release 4, pages 3.11.5-1, 3.11.5-3, and 3.11.5-5–18. Patent Owner labels this
evidence, Exhibit D. PO Response, Ex. D. For purposes of this decision, we refer
to this exhibit as JEDEC 21-C, chapter 3.11.5 but cite to its specific pages using
JEDEC 21-C, p. 3.11.5-X.
11 Chapter 3.11.5 of JEDEC 21-C, which includes the reproduced “SDRAM
FUNCTION TRUTH TABLE,” only includes the idle state of the truth table.
Other states (e.g., row active, read, and write) do not illustrate illegal commands
when S, RE, and CE have the same, asserted values. JEDEC 21-C, p. 3.11.5–5.
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be disregarded completely. See Beckman, 892 F.2d at 1551. Takeda’s teaching
describing generating eight chip select signals (i.e., CS0-CS7) and activating
specific banks in response to input signals S0, S2, RE, CE, WE, A12, and A13 (see
Takeda ¶¶ 5, 12, Claim 1), is good for all it teaches. 3PR Comments 16.
Moreover, Takeda’s discussion in this regard should also be considered in light of
an ordinarily skilled artisan employing one’s background knowledge and creative
inferences. See 3PR Comments 15–17; see also Ex. Deter. 15–16.
With that in mind, Dr. Sayre testifies that an ordinarily skilled artisan would
have been able to design and implement Takeda’s circuitry to achieve its desired
objective when employing the artisan’s creative inferences and background
knowledge without undue experimentation.12 See 3PR Comments 16–18 (citing
Sayre Decl. ¶¶ 61–68). Dr. Sayre provides one such, possible truth table that
would provide the described result in Takeda and notes one skilled in the art would
have known how to transcribe this table into appropriate logic gates. See Sayre
Decl. ¶¶ 64–68. Although Patent Owner criticizes Dr. Sayre for not provided a
specific circuit for Takeda’s bank control unit, Patent Owner does not specifically
dispute the findings and conclusions by Dr. Sayre would not have been known or
recognized by an ordinary skilled artisan. PO Response 22–23.
Rather, Patent Owner contends Dr. Sayre disagrees with Dr. Banerjee’s
solution and argues this provides sufficient evidence that making Takeda’s
described bank control unit is “far from trivial.” PO Response 23. However, just

12 Both Dr. Sayre and Mr. Slemmer indicate that one skilled in the art “would have
a Bachelors of Science in Electrical Engineering or similar field and 2-3 years of
experience in memory device and/or memory board design” as well as possess a
working knowledge of JEDEC memory specifications. Slemmer Decl. ¶ 2; Sayre
Decl. ¶ 17.
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because two experts may not agree on how to design Takeda’s bank control unit as
described, this does not demonstrate sufficiently that those skilled in the art would
not know how to make or use the invention in accordance with the disclosure in
Takeda without undue experimentation. See Ex. Deter. 15–17 (citing Sayre Decl.
¶¶ 61–68). Moreover, Dr. Sayre’s truth table provides a showing how Takeda’s
disclosure would have enabled one skilled in the art as to how to make and use
claim 1’s invention, despite assertions to the contrary. See, e.g., PO Comments 23
(stating “[t]here has been no such showing that the . . . disclosure of Takeda would
enable one of ordinary skill to make and use the invention.”)
Patent Owner also argues that Takeda’s /S0 and /S2 are used to activate all
ranks and the address signal selects rank. PO Comments 27–28, 32–33, and
36–37. Based on this understanding, Patent Owner asserts /S0 and /S2 do not
contribute to actual rank13 selection process. See id. We previously addressed this
argument. 3PR Reply 18 (quoting Dec. 25). Additionally, although we appreciate
Mr. Slemmer’s insights related to this argument, his position has insufficient
supporting evidence. See, e.g., Slemmer Decl. ¶¶ 50–51.
Patent Owner also states Requester and the Examiner improperly shifted the
rejections by focusing the secondary references to teach the recited “set of first
chip select signals,” and such a shift is unfair. PO Comments 35. We are not
persuaded. The rejection focuses primarily on Figure 2’s separate inputs for /S0
and /S2 as well as Takeda’s drive signal discussion to support that /S0 and /S2
inputs are two separate signals. Dec. 19–21; see also 3PR Reply 18. Also, given
that Patent Owner uses JEDEC 21-C to support its position that Takeda’s /S0 and

13 Patent Owner states it is assuming the terms “rank” and “bank” are synonymous
for purposes of discussion. PO Comments 26 n.4.
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/S2 inputs are purportedly a single signal (see PO Response 13–17 (discussing
JEDEC 21-C, chaps. 4.20.2, 4.20.4)), we determine that using this same evidence
to bolster that these inputs are distinct signals is fair and does not shift the thrust of
the rejections.
As to any remaining contentions, we agree with the Examiner’s and
Requester’s findings and conclusions. 3PR Comments 7–21 and 3PR Reply 2–21;
see also Ex. Deter. 9–21.
Accordingly, the record does not demonstrate persuasively that the
Examiner erred in maintaining the art rejections of claim 1 and claims 2–7, 9, 13,
15, 19, and 22, not separately argued.

2. 35 U.S.C. § 112, First Paragraph Rejection
Patent Owner presented amendments to dependent claims 9, 13, 15, 19, and
22 in its request to reopen prosecution. PO Response 6–8. In response, Requester
argues claims 9, 13, and 22 fail to meet the certain requirements under 35 U.S.C.
§ 112, first paragraph—(1) written description and (2) enablement. 3PR
Comments 4–7. The Examiner agrees. Ex. Deter. 6–8.
1. Written Description
Requester asserts claims 9, 13, and 22 require generating the second chip
select signals based on two components: a portion of the address signal and the
auto refresh command. 3PR Comments 5; 3PR Reply 21–24. In Requester’s view,
the disclosure only has support for an “or” relationship (e.g., address signal or auto
refresh command), pointing to OR logic gates 810, 812, 814. 3PR Reply. at 5–6
(citing the ’295 patent, Fig. 8, Supp. Slemmer Decl. ¶ 22, and 2d Supp. Sayre Decl.
¶ 7). The Examiner agrees. Ex. Deter. 6–7.
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In contrast, Patent Owner contends claims 9, 13, and 22 have written
description support in the ’295 patent. PO Comments 37–42. Specifically, Patent
Owner states claim 9 does not require the asserted two preconditions of generating
the second chip select signals based on both a portion of the address signal and an
auto refresh command. Id. at 39. Rather, Patent Owner notes claim 9 recites
generating the second chip select signals based on first chip select signals and a
portion of the address signal and in response to auto refresh signal. Id. at 39–40.
We agree with Patent Owner claim 9 does not require the second chip select
signals are generated based on both a portion of an address signal and an auto
refresh command. As Patent Owner states,
The relevant portions of claim 1 and claim 9 recite:

a circuit...that generates a set of second chip select signals
based at least in part upon values of said set of first chip
select signals and a portion of the address signal (claim 1)

the circuit generates the set of second chip select signals . . . in
response to the set of input control signals indicating an auto
refresh command or an auto precharge command based at least
in part upon values of the set of first chip select signals (claim
9)

(Emphasis added)[.]

PO Comments 39; PO Response 4, 6.
As the above quotation indicates, claim 9 can be construed to specify when
the second chip select signal is generated (i.e., in response to input control signals
that indicate an auto refresh or auto precharge command) and not that the
generated second chip selects signals are based on such commands. PO Comments
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40; see also Supp. Slemmer Decl. ¶ 8 (stating “the ordinary meaning of ‘in
response to’ is a reaction to an event or input.”)
Additionally, as broadly recited, claim 9 recites two different instances when
a respective rank of first number of ranks is activated using at least one second
chip select signal—(1) “during a read or a write” or (2) “in response to the set of
input control signals indicating an auto refresh command or an auto precharge
command.” PO Response 6 (Claim 9). Both of these instances recite when (i.e.,
“during” or “in response to”) a rank is activated and not on what the generated
second chip select signal set is based. See id. In the latter instance, the ’295 patent
discloses at least one scenario where the second chip select signals are generated in
response to input control signals indicating an auto refresh or auto precharge
command as recited in claim 9. The ’295 patent discusses generating either rcs2
and rcs3 (e.g., second chip select signals) when (1) CS0 Auto Precharge all Banks
Command are issued, (2) CS1 Auto Precharge all Banks Command are issued, (3)
CS0 Auto Refresh all Banks Command are issued, or (4) CS1 Auto Refresh all
Banks Command are issued. The ’295 patent 7:15–20, quoted in PO Reply 40; see
id., Fig. 6A.
Requester responds to this discussion in the ’295 patent, asserting “there is
no ‘set of second chip select signals (e.g., rcs0-rcs3 provided as output from CPLD
604)’ that has this ‘as well as’ [i.e., based at least in part upon the values of a
portion of the address signal as well as occurring in response to the set of input
control signals indicating an auto refresh command or an auto precharge
command] relationship.” 3PR Reply 21 (underlining omitted). That is, claim 1,
from which claim 9 depends, recites “a circuit . . . that generates a set of second
chip select signals based at least in part upon values of said set of first chip select
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signals and a portion of the address signal,” and claim 9 recites “the circuit
generates the set of second chip select signals with at least two signals of the set of
second chip select signals each having a value to selectively activate a respective
individual rank of the first number of ranks, in response to the set of input control
signals indicating an auto refresh command or an auto precharge command.” PO
Response 4, 6. Requester argues the ’295 patent illustrates the second chip select
signals are based on either (1) a portion of the address signal or (2)(a) an auto
precharge or (b) an auto refresh command. 3PR Reply 22–23. As such, when an
auto precharge command issues, Requester states the ’295 disclosure does not
show second chip select signals generated based on a value of a portion of the
address signal as claim 1, from which claim 9 depends, requires. See id. at 23–25.
We agree.
The ’295 patent’s Figure 8 shows more details of Figure 6’s CPLD (complex
programmable logic device) 604, generating second chip select signals, rcs0-3a,b.
The ’295 patent 3:32–34, Figs. 6, 8. This embodiment shows Auto Refresh
circuitry 806 and Auto Precharge circuitry 808. Id. at 9:16–26, Fig. 8. For
example, OR gates 810 and 814 provide a scenario, when Auto Precharge
commands issue, where the second chip select signals (e.g., rcs2a-b and rcs3a-b)
are generated based on values of (1) the set of first chip select signals (e.g., cs0 and
cs1 inputted into Auto Refresh circuitry 806 and Auto Pre-charge circuitry 808 as
cs), (2) cs0 provided to multiplexer wcs2, (3) cs1 provided to multiplexer wcs3,
and (4) a portion of the address signal (e.g., add(n) at OR gate 814). See id. at
8:25–28, Fig. 8. Figure 8 also shows an alternative scenario where the second chip
select signals (e.g., rcs2a-b and rcs3a-b) are generated when Auto Refresh
commands issue. See id. at 8:31–33, Fig. 8.
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However, the record reflects in the latter scenario, when an auto refresh
command is provided (i.e., output from Auto Refresh circuitry 806 has a value of
1), the add(n) value into OR gate 814 is of no importance. See id., Fig. 8. As an
example, Mr. Slemmer states the output of OR gate 814 will be 1 when a refresh
command is provided and thus gate 814’s output in this scenario is 1 “regardless of
the value of the add(n) signal provided to OR gate 814.” Supp. Slemmer Decl.
¶ 32. That is, when an auto refresh command issues, Mr. Slemmer states the
add(n) input “does not contribute to the determination of the chip select signal.” Id.
¶ 60. Other supporting evidence also demonstrates the address signal does not
matter during an auto refresh command (e.g., “X” in the ADDR column of Truth
Table 1a - Commands) or that that the address bits are “Don’t Care.”14 See JEDEC
79C, p. 12 (TRUTH TABLE 1a and n.7), 20; see also 3PR Comments 6 and Supp.
Second Slemmer Decl. ¶ 38.
As such, the ’295 patent does not describe or show the claimed invention of
claim 9 in sufficient detail that one skilled in the art can reasonably conclude the
inventor had possession of the claimed invention, which requires both (1) “a circuit
. . . that generates a set of second chip select signals based at least in part upon
values of said set of first chip select signals and the address signal” as recited in
claim 1 (PO Response 4) (emphasis added)) and (2) “the circuit generates the set of
second chip select signals with at least two signals of the set of second chip select
signals each having a value to selectively activate a respective individual rank . . .
in response to the set of input control signals indicating an auto refresh command”
as recited in claim 9 (id. at 6). As noted above, when an auto refresh command is

14 On the other hand, this same table indicates an address value “Code” is used
during a precharge command. JEDEC 79C, p. 12.
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issued, the second chip select signals are generated even when an address signal
input is “Don’t Care” (e.g., “X” in Truth Table 1a or “Don’t Care.”) See JEDEC
79C, p. 12, 20.
Notably, Figure 8 demonstrates that an add(n) must be used in the OR gate
814, regardless of its value, even in the scenario where the auto refresh input is
issued. See the ’295 patent, Fig. 8; see also PO Comments 44 (stating “[j]ust
because the AUTO refresh command does not care about the value of the address
signal does not mean that the address signal does not exist and cannot be used in
the generation of the set of second chip select signals as required by the claims of
the '295 patent.”) However, as Requester further indicates, claim 1, from which
claim 9 depends, requires more than using the address signal— namely, claim 1
requires generating the second chip select signals based on the address signal’s
value. 3PR Reply 25. That is, claim 1, and thus claim 9’s further limitation of “at
least two signals of the set of second set chip select signals” used to activate ranks
“in response to the set input control signals indicating an auto refresh command”
are generated based on a value of “the address signal.” PO Response 4, 6 (reciting
“values of . . . the address signal”).
Accordingly, we agree with the Examiner’s determination that the ’295
patent does not describe or show claim 9’s invention in sufficient detail that one
skilled in the art can reasonably conclude that the inventor had possession of the
claim’s full scope. Likewise, we agree claims 13 and 22, which are similar in
scope to claim 9, lack written description support.

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2. Enablement
Requester also asserts that the recited auto refresh command in claims 9, 13,
and 22 conflicts with the limitations in claim 1 as discussed above, such that an
ordinarily skilled artisan would not know how to make or use the claims 9’s, 13’s,
or 22’s inventions. 3PR Comments 6–7; 3PR Reply 25–26. As explained above,
we agree that there is a conflict between claims 1 and 9, 13, or 22. The conflict
can be resolved by omitting the language that the second chip select signals are
generated based on the address signal portion’s value in claim 1. However, as the
claims currently stand as discussed above, the conflict cannot be resolved by one
skilled in the art such that one skilled in the art would have known how to make or
use the full scope of claims 9, 13, and 22 without undue experimentation. See Ex.
Deter. 7–8.
Accordingly, we agree with the Examiner’s determination that to reject
claim 9, 13, and 22 under 35 U.S.C. § 112, first paragraph.

IV. CONCLUSIONS AND DECISIONS
For the above reasons, Patent Owner has not provided sufficient evidence
and argument to overcome the new grounds of rejection, including the obviousness
rejections of claims 1–7, 9, 13, 15, 19, and 22 of the ’295 patent based on the
references presented in the earlier Decision and (2) the § 112, first paragraph
rejection of claims 9, 13, and 22.
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. §§ 1.304, 1.956, and 41.79(e). See 37
C.F.R. § 41.79.
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In the event neither party files a request for rehearing within the time
provided in 37 C.F.R. § 41.79, and this decision becomes final and appealable
under 37 C.F.R. § 41.81, a party seeking judicial review must timely serve notice
on the Director of the United States Patent and Trademark Office. See 37 C.F.R.
§§ 90.1 and 1.983.
37 C.F.R. § 41.77(f)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

NETLIST, INC.
Requester

v.

Patent of SMART MODULAR TECHNOLOGIES, INC.
Patent Owner
____________________

Appeal 2017-010752
Reexamination Control No. 95/002,399
Patent No. 8,250,295 B2
Technology Center 3900
__________________

Before JEFFREY B. ROBERTSON, DENISE M. POTHIER, and
JEREMY J. CURCURI, Administrative Patent Judges.

CURCURI, Administrative Patent Judge, dissenting-in-part.
I agree with the Majority that Patent Owner has not provided sufficient
evidence and argument to overcome the obviousness rejections of claims 1–7, 9,
13, 15, 19, and 22 of the ’295 patent based on the references presented in the
earlier Decision.
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I write separately because I do not agree with the Majority that Patent Owner
has not provided sufficient evidence and argument to overcome the § 112, first
paragraph rejections of claims 9, 13, and 22.
We give the contested claim limitations the broadest reasonable
interpretation consistent with the Specification. See In re Morris, 127 F.3d 1048,
1054 (Fed. Cir. 1997).
The relevant portion of claim 1 recites “a circuit… that generates a set of
second chip select signals based at least in part upon values of said set of first chip
select signals and a portion of the address signal.”
The ’295 patent’s Figure 8 depicts second chip select signals rcs0a, rcs0b,
rcs1a, rcs1b, rcs2a, rcs2b, rcs3a, rcs3b. Figure 8 depicts first chip select signals
cs0, cs1. Further, Figure 8 depicts a portion of the address signal ~add(n), add(n).
When the output of OR gate 810 is deasserted, the values of ~add(n) and
add(n) become the outputs of OR gates 812 and 814, respectively. The second chip
select signals rcs0a, rcs0b, rcs1a, rcs1b, rcs2a, rcs2b, rcs3a, rcs3b are affected by
the values of ~add(n) and add(n) while the output of OR gate 810 is deasserted.
When the output of OR gate 810 is asserted, the outputs of OR gates 812 and
814 are asserted, and the values of ~add(n) and add(n) do not affect these outputs.
In turn, the second chip select signals rcs0a, rcs0b, rcs1a, rcs1b, rcs2a, rcs2b, rcs3a,
rcs3b are not affected by the values of ~add(n) and add(n) while the output of OR
gate 810 is asserted.
I conclude the broadest reasonable interpretation of claim 1’s “a circuit…
that generates a set of second chip select signals based at least in part upon values
of said set of first chip select signals and a portion of the address signal” includes
the embodiment depicted in the ’295 patent’s Figure 8, where the second chip
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select signals are at some times (for example, while the output of OR gate 810 is
deasserted), but not at all times (for example, while the output of OR gate 810 is
asserted), affected by a portion of the address signal. Put another way, the second
chip select signals exist over time, and the claim language only requires at least
some time where they are affected by a portion of the address signal, which is
consistent with the embodiment illustrated in Figure 8.
Turning to claim 9, the relevant portion of claim 9 recites “the circuit
generates the set of second chip select signals… in response to the set of input
control signals indicating an auto refresh command or an auto precharge command
based at least in part upon values of the set of first chip select signals.”
In light of the discussion above, I conclude the broadest reasonable
interpretation of claim 9’s “the circuit generates the set of second chip select
signals… in response to the set of input control signals indicating an auto refresh
command or an auto precharge command based at least in part upon values of the
set of first chip select signals” includes the embodiment depicted in the ’295
patent’s Figure 8, with this claim language being directed to operation while the
OR gate 810 is asserted. Put another way, claim 1 broadly covers the embodiment
of Figure 8, while claim 9 more narrowly covers the embodiment of Figure 8,
specifically reciting read, write, auto refresh, and auto precharge operations. Again,
the second chip select signals exist over time, and the claim language does not
require that they are always affected by a portion of the address signal.
Given my construction, which construes the claims in a way to read on the
embodiment disclosed in Figure 8 of the ’295 patent, I find these same disclosures
in the Specification, including the Drawing, adequate to convey reasonably to
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those skilled in the art that Patent Owner had possession of the recited subject
matter in claims 9, 13, and 22 as of the filing date.
As well, I find these same disclosures adequate to enable the recited subject
matter. Accordingly, I would not sustain the rejections of claims 9, 13, and 22
under 35 U.S.C. § 112, first paragraph.
For these reasons, I dissent-in-part.

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FOR PATENT OWNER:

Schwegman Lundberg & Woessner, P. A.
PO Box 2938
Minneapolis, MN 55402

FOR THIRD-PARTY REQUESTERS:

Morrison & Foerster LLP
707 Wilshire Boulevard
Los Angeles CA 90017