Ex Parte 8127266 et al

Patent Trials and Appeals Board

Sep 23, 2014

95002207 - (D) (P.T.A.B. Sep. 23, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/002,207 09/13/2012 8127266 3169.001REX2 3549
26111 7590 09/24/2014
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
GE, YUZHEN
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
09/24/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
Requester and Respondent

v.

TELA INNOVATIONS, INC.
Patent Owner and Appellant
____________________

Appeal 2014-005984
Reexamination Control 95/002,207
Patent US 8,127,266 B1
Technology Center 3900

____________

Before RICHARD M. LEBOVITZ, JEFFERY B. ROBERTSON, and
ANDREW J. DILLON, Administrative Patent Judges.

DILLON, Administrative Patent Judge.

DECISION ON APPEAL

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Patent US 8,127,266 B1

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STATEMENT OF THE CASE
Owner appeals under 35 U.S.C. § 134(b) (2011) from the final
decision of the Examiner adverse to the patentability of claims 1-20 of US
8,127,266 B1 (“the ‘266 patent”). We have jurisdiction under 35 U.S.C. §
315 (2002).
We heard oral argument in this Appeal on September 10, 2014, a
transcript of which will be entered into the electronic record in due course.
We affirm.
Related Proceedings
Owner informs us that there are two co-pending inter partes
reexaminations on related patents:
U.S. Patent No. 8,185,865, issued May 22, 2012 is undergoing
reexamination and has been assigned control number 95/002,214. A Right
of Appeal Notice was issued on January 31, 2014. Owner filed a Notice of
Appeal on March 3, 2014.
U.S. Patent No. 7,441,211, issued October 21, 2008 is undergoing
reexamination and has been assigned control number 95/001,832. A
Decision affirming the Examiner was issued on March 31, 2014. (See
Decision on Appeal in Appeal No. 2014-000592.) A Request for Rehearing
was filed on April 30, 2014.

Invention
The ’266 patent describes a method and apparatus for a gate-length
biasing methodology for optimizing integrated digital circuits. The gate-
length biasing methodology replaces a nominal gate-length of a transistor
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with a biased gate-length, where the biased gate-length includes a bias
length that is small compared to the nominal gate-length. See Abstract.
Owner describes the ’266 patent as directed to improving integrated
circuits (“ICs”) by reducing wasted power in circuits that have enough
margin to operate a little more slowly while still accomplishing their
intended function and meeting their performance goals. The ’266 patent
further describes improving ICs by increasing the speed of circuits that need
to go faster. According to Owner, the basis for these enhancements is the
recognition that (1) for short-channel transistors, off-state leakage current
changes at a faster rate than does on-state drive current as a function of gate-
length, and, (2) small increases in the gate-length of transistors in non-
critical timing paths can significantly decrease the total off-state leakage
current in an IC without interfering with its desired functionality or meeting
its timing performance goals. (Owner’s App. Br. 12-13).
.
Prior Art
Pramanik US 6,928,635 B2 Aug. 9, 2005
Sato US 6,009,248 Dec. 28, 1999

Tsai, Y. et al., Influence of Leakage Reduction Techniques on
Delay/Leakage Uncertainty, Proceedings of the 18th International
Conference on VLSI Design” held jointly with 4th International Conference
on Embedded Systems Design (VLSID '05), January 3-7, 2005 (hereinafter
“Tsai”);

Rejections
Claims 1-20 are subject to reexamination. Claims 1-5, 7-13, and 19
stand rejected by the Examiner under 35 U.S.C. § 102 as anticipated by U.S.
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Patent No. 6,928,635 (“Pramanik”). Claims 6, 14-18, and 20 stand rejected
under 35 U.S.C. § 103 as obvious over Pramanik, Admitted Prior Art, and
Tsai. Claims 1-20 are original patent claims. Claims 1 and 7 are
independent.

Claim 1 is selected as representative of the claimed subject matter.
1. A method for preparing a layout used in making a
semiconductor device, comprising:
identifying a transistor in a nominal layout that includes shape
geometries usable in making of the semiconductor device, the
identified transistor selected for gate-length biasing;

using an annotated layout to select the identified transistor, the
annotated layout providing information defining gate-length
biasing to be performed on the identified transistor of the
nominal layout to produce the layout used in manufacturing
when making the semiconductor device; and

producing a biased layout, the biased layout has a gate-length
biased transistor resulting from the gate-length biasing defined
using the information provided by the annotated layout, the
method implemented by a processor executing a program;

wherein the information provided by the annotated layout itself
identifies a modification of a gate length of the identified
transistor in the nominal layout; using the biased layout to
manufacture the semiconductor device.

Owner’s Contentions

Owner contends that the Examiner erred in entering the following
grounds of rejections against claims 1-20. (Owner’s App. Br. 7-9):
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A. The rejection of claims 1-5, 7-13, and 19 under 35 U.S.C. § 102(e)
as anticipated by Pramanik;
B. The rejection of claim 18 under 35 U.S.C. § 103(a) as being
unpatentable over Pramanik and Admitted Prior Art;
C. The rejection of claim 6, 14-18, and 20 under 35 U.S.C. § 103(a) as
being unpatentable over Pramanik and Tsai.

Requester’s Contentions
Requester appeals the failure of the Examiner to adopt the proposed
rejection of claims 1-20 under 35 U.S.C. §103(a) as unpatentable over Sato
and Tsai.
1

1
On September 3, 2014, Requester, Taiwan Semiconductor Manufacturing
Co., Ltd, served notice that it no longer intends to participate in the present
reexamination. In view of that notice and our decision to sustain the
Examiner’s rejection of all claims on other grounds, we do not reach the
merits of Requester’s cross appeal. See Tempo Lighting, Inc. v Tivoli, LLC,
2014 WL 503128 (Fed. Cir. Feb. 10, 2014).
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ANALYSIS
Representative Claim
Owner distinguishes all the cited prior art based on the limitations of
claim 1 and, beyond urging patentability on the basis of similar limitations
within claim 7, does not provide arguments for separate patentability for any
other claim. Accordingly, we will decide the appeal on the basis of claim 1
alone. See 37 C.F.R. § 41.67(c)(1)(vii).

Claim Interpretation
During reexamination, claims of an unexpired patent are givens their
broadest reasonable interpretation consistent with the specification as they
would be construed by one of ordinary in the art. In re Am. Acad. of Sci.
Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). The Office must apply the
broadest reasonable meaning to the claim language, taking into account any
definitions presented in the specification. Id. (citing In re Bass, 314 F.3d
575, 577 (Fed. Cir. 2002)).
“Annotated Layout ”
Owner urges that the position of the Examiner with respect to the
rejection of claim 1 under 35 U.S.C. § 102(e) as anticipated by Pramanik, as
set forth in the Right of Appeal Notice, is improper in view of the failure of
Pramanik to disclose the claimed “annotated layout.” Owner’s App. Br. 19.
Owner argues, as similarly recited in claims 1 and 7, an “annotated
layout” necessarily includes “providing information defining gate-length
biasing to be performed on the identified transistor.” In this manner, Owner
urges the claimed invention “allows each transistor that is identified for gate-
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length biasing to also have its gate-length biasing individually specified.”
Id. at 14.
Owner contrasts this with the teaching by Pramanik of “tags.” Owner
asserts that the “tags” merely identify transistors within the critical path and
do not convey both types of information (i.e. the identity of a transistor and
the amount of gate-length biasing). Consequently, Owner asserts the “tags”
of Pramanik “only identify the gates that lie in a critical path and are subject
to a different set of post-layout processing rules (e.g., gate-length biasing).”
Id. at 20-21.
Owner acknowledges that the tagged gates within Pramanik are
processed utilizing a different set of processing rules, but disputes the
position of Examiner that the “tags” convey information that actually
modifies a gate-length of a specified transistor. Instead, Owner argues that
the information for performing post-layout processing on selected transistors
“is self-contained in Pramanik’s tools and not delivered by its tags.” Id. at
21.
Owner contrasts this situation with the “annotated layout” of the
claimed invention, which Owner asserts contains both an identification of
which transistors are selected for gate-length biasing and “instructions to be
received and carried out by the post-layout processing tools.” Id. at 23.
Initially, the Examiner finds that layout 511 of Figure 5 of Pramanik
reads on the “annotated layout” of independent claims 1 and 7. RAN 4. As
evidence of this, the Examiner cites Pramanik at col. 4, lines 15-21 which
describes layout 511 feeding information into a post-layout tool 512, noting
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that in one embodiment “post-layout processing tool 512 selectively
modifies transistor gate lengths for critical transistors. . .” Id. at 6.
With regard to Owner’s arguments that the “tags” of Pramanik fail to
provide post-layout processing information, the Examiner finds that Owner’s
claims fail to expressly recite that the “annotated layout” conveys specific
bias information to the post-layout processing tools. Consequently, the
Examiner finds that the identification of specific gates utilizing “tags,” as
shown by Pramanik, conveys processing information which may be utilized
to apply different amounts or degrees of gate-length biasing to those tagged
gates, as claimed. RAN 4, 7.
We concur with the Examiner. We find that many of Owner’s
arguments are not commensurate with the scope of the appealed claims. For
example, we find no requirement in the appealed claims that the
“information” provided by the annotated layout be “received and carried out
by the post-layout processing tools” as argued by Owner. Owner App. Br.
23. We find that the claims merely require the provision of information
within an annotated layout which defines gate-length biasing to be
performed and thereafter using that information to produce a biased layout to
manufacture the semiconductor device. We find nothing within the appealed
claims that requires the gate-length biasing information to be coupled to the
post-layout processing tools, as opposed to utilizing the gate-length biasing
information to select which set of processing rules already stored within the
post-layout processing tools should be utilized for processing a particular
transistor, as disclosed by Pramanik.
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Owner attempts to distinguish Pramanik, arguing that “the
information for performing post-layout processing on selected transistors is
self-contained in Pramanik’s tools and not delivered by its tags.” Appeal Br.
21. This argument is not consistent with the language of the claim. The
claims recite that “the information provided by the annotated layout itself
identifies a modification of a gate length of the identified transistor in the
nominal layout” and that information is used in the step of “producing a
biased layout.” Contrary to Owner’s contention that the information for
performing the processing must be in the tags, the claim only requires that a
modification of gate-length is identified, but there is no distinct requirement
that all the information for performing the post-layout is present in the
claimed “information.
Consequently, we find the “tags” of Pramanik, along with the
different described processing rules to be utilized for tagged gates and other
gates, meet the claimed limitations at issue in the present appeal. This is
particularly true in view of the recitation within Pramanik that the disparate
processing rules cause modification of gate lengths. See Pramanik, Col. 5,
lines 4-18.
We therefore find that the Examiner did not err in rejecting claim 1
under 35 U.S.C. § 102(e) as anticipated by Pramanik. For the same reasons
we set forth above, we find no error in the Examiner’s rejection of claim 7 in
the face of the same arguments by Owner, as well as claims 2-4, 8-13, and
19 which were not argued separately.
Owner argues the Examiner erred in the rejection of claim 18 under
35 U.S.C. § 103(a) as being unpatentable over Pramanik and Admitted Prior
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Art in view of the alleged failure of Pramanik to disclose an “annotated
layout” as argued above. Owner’s App. Br. 29.
As we have addressed above, we find that Pramanik discloses the
claimed “annotated layout” and consequently we find no error in this
rejection.
Finally, Owner argues that the Examiner erred in rejecting claims 6,
14-18 and 20 under 35 U.S.C. § 103(a) as being unpatentable over Pramanik
and Tsai. Owner acknowledges that the teaching of the relationship between
gate length and drive current, as well as the relationship between gate length
and leakage current, described by Tsai, was known. However, Owner once
again disputes that this combination discloses “a method for selecting
nominal transistors from a layout and for conveying to a post-layout
processing tool both the identification of the selected transistors and the
amount or manner of changing the nominal gate length of the selected
transistors as is claimed in the ’266 patent.” Id. at 30.
As we set forth above, Owner’s claims do not require that gate-length
biasing information be “conveyed” to a post-layout processing tool, only that
information which defines the gate-length biasing to be performed is utilized
to manufacture a semiconductor device. We have described our finding that
such information may be, in our opinion, an indication of which of multiple
previously stored processing rules should be applied to a particular
transistor, as disclosed by Pramanik.
We therefore find no error in the Examiner’s rejection of claims 6, 14-
18 and 20 under 35 U.S.C. § 103(a) as being unpatentable over Pramanik
and Tsai.
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DECISION
The Examiner’s decision adverse to the patentability of claims 1-20 is
affirmed.
Requests for extensions of time in this proceeding are governed by 37
C.F.R. §§ 1.956 and 41.79(e).
In the event neither party files a request for rehearing within the time
provided in 37 C.F.R. § 41.79, and this decision becomes final and
appealable under 37 C.F.R. § 41.81, a party seeking judicial review must
timely serve notice on the Director of the United States Patent and
Trademark Office. See 37 C.F.R. §§ 90.1 and 1.983.

AFFIRMED

Patent Owner:

STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005

Third Party Requester:

DAVID M. O’DELL
HAYNES AND BOONE, LLP, IP Section
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219

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