Ex Parte 7360050 et al

Patent Trial and Appeal Board

Nov 16, 2012

95001205 (P.T.A.B. Nov. 16, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,205 07/01/2009 7360050 2805.002REXB 4486
26111 7590 11/16/2012
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
CHOI, WOO H
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/16/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

NVIDIA CORPORATION
Respondent
v.

RAMBUS, INC.
Patent Owner, Appellant
____

Appeal 2012-003817
Reexamination Control No. 95/001,205
Patent 7,360,050 B2
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON APPEAL
Appellant, patent owner Rambus, Inc., appeals under 35 U.S.C. §§
134(b) and 306 from a Right of Appeal Notice rejecting claims 1-26 and 38-
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31.1 Claim 27 was confirmed. We have jurisdiction under 35 U.S.C. §§
134(b) and 306. An oral hearing was conducted on September 19, 2012.

STATEMENT OF THE CASE
This proceeding arose from a request by NVIDIA Corporation for an
inter partes reexamination of U. S. Patent 7,360,050 B2 (hereinafter, the
‘050 patent), entitled “Integrated Circuit Memory Device Having Delayed
Write Capability,” and issued to Richard M. Barth, Frederick A. Ware,
Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar,
James A. Gasbarro, and David Nguyen (April 15, 2008).
The ‘050 patent describes memory devices (col. 1, l. 21). Claim 1 on
appeal reads as follows:
1. An integrated circuit memory device comprising:
a memory core including a plurality of memory cells;
a first set of pins to receive, using the clock signal, a row address,
followed by a column address;
a second set of pins to receive, using the clock signal:
a sense command, the sense command to specify that the
memory device activate a row of memory cells of the
plurality of memory cells identified by the row address,
and
a write command during a first time period, the write command
to specify that the memory device receive write data and
store the write data at a location in the row of memory
cells, the location identified by the column address,
wherein the write command is posted internally to the

1 Respondent and Third-Party Requester (hereinafter “NVIDIA
Corporation”) states that “it no longer intends to participate in the present
reexamination” (Notice of Non-Participation in Inter Partes Reexamination,
filed February 8, 2012). We will therefore not consider issues set forth in
Third-Party Requester’s Cross Appeal (filed September 23, 2011) and
associated briefs and papers.
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memory device after a first delay has transpired from the
first time period; and
a third set of pins to receive the write data after a second delay has
transpired from the first time period.

(App. Br. 36, Claims Appendix.)

The Examiner relies on the following prior art references:
Ware US 5,430,676 Jul. 4, 1995
Ryan US 6,044,429 Mar. 28, 2000
Gillingham US 6,088,774 Jul. 11, 2000
Gustavson US 6,226,723 B1 May 1, 2001
Inagaki JP 57-210495 Dec. 24, 1982

JEDEC Standard, Configurations for Solid State Memories, JEDEC
Standard No. 21-C, Release 4 (1993) (hereinafter, “JEDEC”).

Shigeo Ohshima et al., “High Speed DRAMs with Innovative Architectures,
IEICE Trans. Electron., Vol. E77-C, No. 8 (1994) (hereinafter, “Ohshima”).

The Examiner rejects the claims as follows:
Claims 1, 3, and 7-10 under 35 U.S.C. § 102(b) as anticipated by
Ware.
Claims 1-3, 5-20, 22, 23, 25, 26, and 28-31 under 35 U.S.C. § 103(a)
as unpatentable over Ware and Gustavson; claims 2, 5, 6, 11-14, 16, 17, 19,
20, 22, 23, 25, 26, and 28-31 under 35 U.S.C. § 103(a) as unpatentable over
Ware and Ohshima; claims 1, 3, 7-11, and 15-18 under 35 U.S.C. § 103(a)
as unpatentable over Ware and JEDEC; claims 2, 5, 6, 12-14, 19, 20, 23, 25,
26, and 28-31 under 35 U.S.C. § 103(a) as unpatentable over Ware, JEDEC,
and Gustavson; and claims 2, 5, 6, 19, 20, 23, 26, 28, 29, and 31 under 35
U.S.C. § 103(a) as unpatentable over Ware, JEDEC, and Inagaki.
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Claim 4, 21, and 24 under 35 U.S.C. § 103(a) as unpatentable over
Gillingham and Ryan and claims 4 and 21 under 35 U.S.C. § 103(a) as
unpatentable over Gillingham and Ohshima.
The Examiner confirms patentability of claim 27.

ISSUE
Did the Examiner err in rejecting claims 1-26 and 28-31?

FINDINGS OF FACT
1) Ware discloses “latency between the clock cycle with the . . .
write command and the clock cycle with the first word of write data is zero”
but that “there is a delay of tCAA which occurs [for a read command]” (col. 8,
ll. 52-55).
2) Ware discloses that because of “wasted clock cycles” (col. 8, l.
56) when the write latency is zero, “the write latency is made programmable
so that is can be adjusted to equal the read latency” (col. 8, ll. 59-61).
3) Ware discloses an example of programming latency in which
“DRAM control logic 500 . . . delays a signal to initiate an operation (Start
R/W) 505 a certain number of clock cycles dependent upon the information
loaded into the latency control register 510” (col. 8, ll. 63-67; Fig. 17) to
“determine whether the signal 505 is immediately input or input after a
predetermined delay….” (col. 9, ll. 6-7).

PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
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claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co. of Kansas City,
383 U.S. 1, 17-18 (1966).
“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).

ANALYSIS
Ware Reference- Anticipation (claims 1, 3, and 7-10)
The Examiner rejects claims 1, 3, and 7-10 as anticipated by Ware.
We agree with the Examiner for at least the reasons set forth by the
Examiner (see, e.g., Right of Appeal Notice (hereinafter, “RAN”) 11-13).
Claim 1 recites that a write command is “posted internally to the
memory device after a first delay has transpired from the first time period”
(App. Br. 36). Appellant argues that Ware fails to disclose this feature (see,
e.g., App. Br. 15-16). However, as the Examiner points out and as described
above, Ware discloses that when a read latency2 is equal to a finite value
(e.g., tCAA) and a write latency3 is equal to zero, there may be undesired

2 The time measured “between the clock cycle with the . . . read command
and the clock cycle with the first word of read data” (col. 8, ll. 47-49).
3 The time measured “between the clock cycle with the . . . write command
and the clock cycle with the first word of write data” (col. 8, ll. 52-54).
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“wasted clock cycles.” In order to address this problem, according to Ware,
the write latency is “made programmable” so that the write latency may be
“adjusted to equal the read latency (FF 1-3).
Ware further discloses an example of programming the latency such
that “a signal to initiate an operation (Start R/W) 505” is delayed within
“DRAM control logic 500” (FF 1-3; Fig. 17; col. 8, ll. 63-66). Hence, Ware
discloses that a write latency is “programmed” so that “a signal to initiate an
operation (Start R/W)”4 is delayed. In other words, Ware discloses a delay
that transpires from when the write command is received (i.e., “the clock
cycle with the . . . write command” – col. 8, ll. 52-53) to when “a signal to
initiate an operation” (col. 8, ll. 64-65) (i.e., the write operation) is applied.
This process is further illustrated in Fig. 17 where a signal to “initiate read or
write sequence” is delayed within the DRAM logic (element 500, Fig. 17).
Appellant has not sufficiently pointed out any meaningful differences
between these features disclosed by Ware and the presently claimed
invention since both claim 1 recites and Ware discloses a delay between
when the write command is received to when a signal is applied (i.e., when
the write command is posted, as recited in claim 1).
Appellant argues that “Ware does not describe its Start R/W signal as
a write command” (App. Br. 16) but does not indicate a specialized
definition of “write command” in the Specification. In the absence of a
specific definition of the term “write command,” we construe the term

4 Col. 8, ll. 64-65 – in this case, a signal responsive to the write command
since Ware discloses this “exemplary structure” for programming the write
latency “so that it can be adjusted to equal . . . the read latency” (col. 8, ll.
60-61)
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broadly but reasonably and in light of the Specification to include any
instruction or functional data element that specifies that a device receive
write data. This definition comports with a plain and customary meaning as
would have been understood by one of skill in the art as well as the claim
requirement that a write command specify “that the memory device receive
write data.”
Appellant disagrees with this broad but reasonable construction of the
term “write command” because, according to Appellant, such a construction
is “laden with additional meaning in this part” (Oral Hearing Transcript, p.
7, l. 1). Specifically, Appellant argues that a “write command” as recited
cannot be a “data element”5 or an “instruction”6 (Id. at p. 7). Appellant
further states that a write command “specifies that the memory device
receive write data” (Id. at p. 7, ll. 13-14) but that “the Start R/W . . . [of]
Ware does not specify the device receive write data” (Id. at p. 8, ll. 1-2). We
are not persuaded by Appellant’s arguments.
Notably, Appellant does not provide an alternative definition of the
term “write command.” Instead, Appellant states that a “data element”
cannot be a “write command” because a data element “is a different class of
signal than . . . command signals . . . [or] clock signal[s]” (Oral Hearing
Transcript, p. 7, ll. 2-4). However, Appellant does not indicate how a “data

5 Appellant argues that a “data element . . . is a different class of signal than
the command signals, which is a different class of signal than are clock
signal[s]” (Oral Hearing Transcript, p. 7, ll. 2-4).
6 Appellant argues that “[a]n instruction itself . . . [is] something that needs
to be either interpreted or decoded . . . [b]ut a timing signal . . . does not
specify that the device receive write data” (Oral Hearing Transcript, p. 7, ll.
8-12).
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element” differs from a “write command” even assuming that a “data
element” is somehow different from a “command signal” or a “clock
signal.” For example, Appellant does not indicate in what way a “data
element” supposedly differs from a “command signal” or “clock signal” and
does not indicate how such alleged differences, even assuming any
differences exist, pertain to a “write command.”
Likewise, Appellant states that an “instruction” cannot be a “write
command” because an instruction must be “something that needs to be either
interpreted or decoded” (Oral Hearing Transcript, p. 7, ll. 8-12). First,
Appellant does not provide support for the contention that an “instruction”
needs to be “interpreted” or “decoded.” Even assuming that an “instruction”
does, in fact, need to be “interpreted” or “decoded” as Appellant argues,
Appellant has not sufficiently demonstrated how such an “instruction”
(supposedly needing to be “interpreted” or “decoded”) differs in any way
from a “write command” as claimed.
As Appellant points out, claim 1, for example, recites that a write
command specifies “that the memory device receive write data.” While
Appellant argues that “the Start R/W signal” of Ware “does not specify the
device receive write data” (Oral Hearing Transcript, p. 8, ll. 1-2), Appellant
does not provide sufficient evidence to demonstrate that “Start R/W” of
Ware does not, in fact, “specify the device receive write data” as recited in
claim 1.
As described above and as pointed out by the Examiner, Ware
discloses a “clock cycle with the . . . write command” (col. 8, ll. 52-53)
associated with a write latency that “is made programmable” (col. 8, ll. 60)
by delaying “a signal to initiate an operation” (col. 8, ll. 64-65). We
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disagree with Appellant’s assertion that Ware fails to disclose a write
command since Ware explicitly discloses a “write command” (see, e.g., col.
8, l. 53) and an exemplary structure in which a “Start R/W” instruction
initiates an operation that one of skill in the art would have understood to be
a write operation. Since “Start R/W” specifies that a device receive write
data (i.e., initiates a write operation), we disagree with Appellant that there
is any meaningful difference between the “write command” and “Start R/W”
of Ware and the claimed “write command.”
While Appellant argues that “[t]he Start R/W signal [of Ware] is not a
write command” (App. Br. 17), Appellant does not provide an adequate
showing of any differences between the “write command” or “Start R/W” of
Ware and a “write command” as recited in claim 1. As described above, the
“Start R/W” of Ware, for example, is delayed (see, e.g., Fig. 17) and initiates
an operation (e.g., a write operation – e.g., Fig. 17) while the claimed “write
command” is also delayed “posted . . . after a first delay”) and also specifies
“that the memory device receive write data.” In both cases, a write
operation is being specified (after a delay).
Appellant argues that the “Start R/W” of Ware differs from the
claimed “write command” because the “Start R/W” of Ware “is actually a
single bit” (App. Br. 17). Hence, Appellant implies that the write command
recited in claim 1 must not be a “single bit” but does not indicate where in
the claim such a requirement is imposed upon the “write command.” Nor do
we independently find such a requirement in claim 1.
Appellant also argues that the “Start R/W” of Ware differs from the
claimed “write command” as received in claim 1 because “[Ware] does not
even indicate whether the initiated operation is a read or a write operation”
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(App. Br. 17). We disagree with Appellant for at least the reasons set forth
above. For example, Ware discloses that the Start R/W “initiate[s] . . . [a]
write sequence” (see, e.g., Fig. 17). Appellant does not sufficiently
demonstrate any differences between initiating a “write sequence” (Ware)
and initiating a “write operation.”
Appellant argues that “Ware does not disclose how . . . the Start R/W
signal results in a delayed internal presentation of a write command” and
that “there is nothing in . . . Ware that speaks to the delay of the internal
posting of the write command” (App. Br. 18). As described above, Ware
discloses receiving a write command (e.g., receiving a write command in a
“clock cycle with the . . . write command” – col. 8, ll. 52-53), making the
associated write latency “programmable so that it can be adjusted” (col. 8, ll.
60-61), and delaying the “signal to initiate an operation” (col. 8, ll. 64-65).
Given Ware’s explicit disclosure of delaying an instruction that specifies
that a device receive write data (i.e., delaying a “write command”), we
disagree with Appellant’s assertion.
Appellant also argues that Ware discloses a “Start R/W signal” that
“. . . if anything, corresponds to the amount of data ‘latency.’ (Murphy
Decl., ¶¶ 35, 37.)” (App. Br. 19). However, as described above, Ware
addresses the problem of “wasted clock cycles” by making a write latency
“programmable” (col. 8, l. 60) and further provides a specific example of
programming such a latency. One of ordinary skill in the art would have
understood that the “latency” (or delay) being programmed in the specific
example of Ware (the specific example immediately following and flowing
from Ware’s description of the problem in which Ware explicitly discloses
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that a write latency needs to be programmed) is a write latency (see, in
general, col. 8, ll. 52-67).
Appellant also argues that “Figure 2 [of Ware] does not show any
items to delay the signals . . . nor does it show anything remotely equivalent
to the write delay block 2709 in FIG. 20 of the ‘‘050 patent’” (App. Br. 19).
However, as described above, Appellant has not provided sufficient
evidence that Ware fails to disclose the claimed invention.
Appellant does not provide additional arguments in support of claims
3 or 7-10 (App. Br. 23-24). The Examiner did not err in rejecting claims 1,
3, and 7-10 as anticipated by Ware.

Ware Reference- Obviousness (claims 1-3, 5-20, 22, 23, 25, 26, and 28-31)
Regarding claims 11 and 22, Appellant argues that “Ware’s Start R/W
signal . . . is not delayed internally ‘in response to the write command’”
(App. Br. 22-23). As described above, Ware discloses a “clock cycle”
containing a “write command” (col. 8, ll. 52-53), a delay between this clock
cycle/write command and “the first word of write data” (col. 8, l. 54), and
programming “the write latency [i.e., the delay between the write command
and “the first word of write data”]. . . so that it can be adjusted” (col. 8, ll.
60-61) by delaying “a signal to initiate an operation (Start R/W) 505 a
certain number of clock cycles” (col. 8, ll. 64-65). In other words, in Ware,
a write command is received, then the delay measured from when the write
command is received to when write data is received is adjusted by delaying
Start R/W. Since Ware does not disclose that Start R/W is adjusted when a
write command is not received, delaying Start R/W is performed “in
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response to” the write command. Appellant does not provide a sufficient
explanation of any differences.
Appellant argues that it would not have been obvious to one of
ordinary skill in the art to combine the Ware reference with any other
reference because “Rambus’ Direct RDRAM technology have achieved
substantial commercial success” (App. Br. 31) and “Rambus has extensively
licensed the ‘050 patent” (Id). However, we agree with the Examiner that
Appellant has failed to adequately demonstrate a nexus since Appellant does
not provide sufficient evidence that clearly connects the alleged commercial
success to the merits of the claimed invention. The weight given to evidence
of secondary considerations is dependent upon whether there is a nexus
between the merits of the claimed invention and the evidence offered.
Stratoflex, Inc. v. Aeroquip Corp., 713 F.2d 1530, 1539 (Fed. Cir. 1983).
As one example, Appellant has not sufficiently established that the
sale of “500 million memory devices incorporating the Rambus . . . memory
interface” (App. Br. 31) constitutes “commercial success” when considered
in relation to overall market share. In fact, Appellant does not appear to
provide any data pertaining to overall market share. Even assuming that the
sale of “500 million memory devices” would have constituted “commercial
success” as Appellant argues, Appellant has merely alleged that “500 million
memory devices” “incorporated” the “Rambus . . . memory interface.”
Appellant has not adequately demonstrated that any of the “500 million
memory devices” were sold because of the “Rambus . . . memory interface”
supposedly contained therein. In other words, Appellant does not establish a
nexus between the patented invention and the alleged commercial success.
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Appellant argues that “Rambus has extensively licensed the ‘050
patent” (App. Br 31). As above and as pointed out by the Examiner,
Appellant does not provide an adequate showing that a nexus exists between
the specific features of the claimed invention and the alleged licensing
activity.
Appellant states that while the Patent Owner must show some causal
relation between an invention and commercial success (citing Merck & Co.,
Inc. v. Teva Pharmaceuticals USA, Inc., 395 F.3d 1364, 1376 (Fed. Cir.
2005)), the Patent Owner, according to Appellant, need not demonstrate that
“the claimed invention must be the sole cause of the commercial success”
(App. Br. 32). Even assuming this allegation to be true, Appellant has not
established the required nexus between the claimed invention and any
alleged commercial success (or licensing). We agree with Appellant’s
implication that Appellant failed to demonstrate that the claimed invention
was the “sole” cause of any potential commercial success (or licensing).
More importantly, however, without an adequate showing of a nexus
between the claimed invention and any alleged commercial success (or
licensing), Appellant has failed to adequately demonstrate that “the claimed
invention” was a cause of the commercial success (assuming that
commercial success even occurred) or that the claimed invention was in any
way related to any commercial success (or licensing) that might (or might
not) have occurred. Therefore, we are not persuaded by Appellant’s
arguments pertaining to secondary considerations as they relate to the
Examiner’s obviousness rejections.

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Gillingham Reference (claims 4, 21, and 24)
Claims 4 and 21 recites that a second delay corresponds to the third
delay minus a turnaround time. Claim 24 recites that a first delay
corresponds to the second delay minus a turnaround time. The Gillingham
reference (U.S. Patent No. 6,008,774 – the ‘774 patent) was filed September
19, 1997 (issued July 11, 2000) and is related to U.S. Provisional
Applications 60/026,594 (September 20, 1996); 60/055,349 (August 11,
1997), and 60/057,092 (August 27, 1997). While the Examiner states that
Gillingham (the ‘774 patent) discloses a second delay corresponding to the
third delay minus a turnaround time (RAN 8), the Examiner appears to agree
that U.S. Provisional Application 60/026,594 does not disclose this feature,
thus according the Gillingham reference the priority date of August 11,
1997.
Appellant provides a Declaration by “the assignee of [the ‘050
patent]” (Declaration of Craig E. Hampel under 37 C.F.R. § 1.131, dated
April 2, 2010, ¶ 2), which states that the inventors of the ‘050 patent
“conceived of the inventions claimed in the [‘050 patent]” prior to January 2,
1997 and “continued diligently from prior to January 2, 1997 to October 10,
1997, which is the earliest filing date of [the ‘050 patent]” (Declaration of
Craig E. Hampel under 37 C.F.R. § 1.131, filed April 2, 2010, ¶ 14). The
Examiner appears to agree with Appellant, however, regarding claims 4, 21,
and 24 (which recite a delay time corresponds to another delay time minus a
channel turnaround time, or similar feature), the Examiner states that Patent
Owner has not demonstrated that “the timing diagram [in the Davis email]
shows an offset, or second delay time, of 8 cycles set to match a third delay
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time (9 cycles) minus a channel turnaround time (1 cycle)” (RAN 23, citing
Davis email – Exhibit CA).
We disagree with the Examiner for at least the reasons set forth by
Appellant (App. Br. 27-30). As Appellant points out, the Davis email
appears to show the disputed claimed feature at least with the specific
example described in the Davis email of a write delay time of 8 cycles being
equal to a read delay time of 9 cycles minus a channel turnaround time of 1
cycle (see, e.g., App. Br. 29).
The Examiner erred in rejecting claims 4, 21, and 24 as unpatentable
over Gillingham and Ryan or claims 4 and 21 as unpatentable over
Gillingham and Ohshima.

CONCLUSION
The Examiner erred in rejecting claims 4, 21, and 24 as unpatentable
over Gillingham and Ryan or claims 4 and 21 as unpatentable over Ryan and
Ohshima.
The Examiner did not err in rejecting claims 1, 3, and 7-10 as
anticipated by Ware; claims 1-3, 5-20, 22, 23, 25, 26, and 28-31 as
unpatentable over Ware and Gustavson; claims 2, 5, 6, 11-14, 16, 17, 19, 20,
22, 23, 25, 26, and 28-31 as unpatentable over Ware and Ohshima; claims 1,
3, 7-11, and 15-18 as unpatentable over Ware and JEDEC; claims 2, 5, 6,
12-14, 19, 20, 23, 25, 26, and 28-31 as unpatentable over Ware, JEDEC, and
Gustavson; and claims 2, 5, 6, 19, 20, 23, 26, 28, 29, and 31 as unpatentable
over Ware, JEDEC, and Gustavson.

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DECISION
The Examiner’s decision to reject claims 4, 21, and 24 as unpatentable
over Gillingham and Ryan and claims 4 and 21 as unpatentable over
Gillingham and Ohshima is reversed.
The Examiner’s decision to reject claims 1, 3, and 7-10 as anticipated
by Ware; claims 1-3, 5-20, 22, 23, 25, 26, and 28-31 as unpatentable over
Ware and Gustavson; claims 2, 5, 6, 11-14, 16, 17, 19, 20, 22, 23, 25, 26,
and 28-31 as unpatentable over Ware and Ohshima; claims 1, 3, 7-11, and
15-18 as unpatentable over Ware and JEDEC; claims 2, 5, 6, 12-14, 19, 20,
23, 25, 26, and 28-31 as unpatentable over Ware, JEDEC, and Gustavson;
and claims 2, 5, 6, 19, 20, 23, 26, 28, 29, and 31 as unpatentable over Ware,
JEDEC, and Inagaki is affirmed.

AFFIRMED-IN-PART
rvb

PATENT OWNER

STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YOURK AVENUE, NW
WASHINGTON, DC 20005

THIRD PARTY REQUESTER

DAVID M. O’DELL
HAYNES AND BOONE, LLP.IP SECTION
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219