Ex Parte 7287119 et al

Patent Trial and Appeal Board

Nov 16, 2012

95001189 (P.T.A.B. Nov. 16, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,189 05/18/2009 7287119 2805.002REX8 8867
26111 7590 11/16/2012
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
CHOI, WOO H
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/16/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

NVIDIA CORPORATION
Respondent
v.

RAMBUS, INC.
Patent Owner, Appellant
____

Appeal 2012-004035
Reexamination Control No. 95/001,189
United States Patent 7,287,119 B2
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON APPEAL
Appellant, patent owner Rambus, Inc., appeals under 35 U.S.C. §§
134(b) and 306 from a Right of Appeal Notice rejecting claims 1-8 and 10-
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23.1 Claim 9 was confirmed. We have jurisdiction under 35 U.S.C. §§
134(b) and 306. An oral hearing was conducted on October 3, 2012.

STATEMENT OF THE CASE
This proceeding arose from a request by NVIDIA Corporation for an
inter partes reexamination of U. S. Patent 7,287,119 B2 (hereinafter, the
‘119 patent), entitled “Integrated Circuit Memory Device with Delayed
Write Command Processing,” and issued to Richard M. Barth, Frederick A.
Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M.
Abhyankar, James A. Gasbarro, and David Nguyen (October 23, 2007).
The ‘119 patent describes memory devices (col. 1, l. 22). Claim 1 on
appeal reads as follows:
1. An integrated circuit memory device comprising:
a memory core including a plurality of memory cells;
a first set of pins coupled to the memory core, the first set of pins to
receive a row address that identifies a row of the memory core, followed by
a column address that identifies a column location of the row;
a second set of pins coupled to the memory core, the second set of
pins to receive a sense command followed by a write command, wherein the
sense command specifies sensing of the row, wherein the write command
specifies that the memory device receive write data to be stored at the
column location, wherein the write command is presented internally to the
memory device after a first delay time has transpired from when the write
command is received at the second set of pins; a third set of pins to receive

1 Respondent and Third-Party Requester (hereinafter, NVIDIA Corporation)
“withdraws its appeal to the Board, including all of its Appeal Briefs and
supporting papers” (“Notice of Withdrawal of Third-Party Requester’s
Appeal and Other Papers,” filed February 17, 2012, p. 1). In view of Third-
Party Requester’s withdrawal from these proceedings, we need not consider
issues set forth in Third-Party Requester’s cross appeal (i.e., Third Party
Requester’s Cross-Appeal Brief in Inter Partes Reexamination Pursuant to
37 C.F.R. § 41.67, filed July 19, 2011) and associated briefs and papers.
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the write data after a second delay time has transpired from when the write
command is received at the second set of pins; and

a column access path coupled to the third set of pins and the memory
core, the column access path to convey the write data to the column location.

(App. Br. 38, Claims Appendix.)

The Examiner relies on the following prior art references:
Ware US 5,430,676 Jul. 4, 1995
Ryan US 6,044,429 Mar. 28, 2000
Gillingham US 6,088,774 Jul. 11, 2000
Gustavson US 6,226,723 B1 May 1, 2001
Inagaki JP 57-210495 Dec. 24, 1982

JEDEC Standard, Configurations for Solid State Memories, JEDEC
Standard No. 21-C, Release 4, November 1993 (hereinafter, “JEDEC”).

Shigeo Ohshima et. al., High Speed DRAMs with Innovative Architectures,
IEICE Trans. Electron., Vol. E77-C, No. 8, August 1994 (hereinafter,
“Ohshima”).

The Examiner rejects the claims as follows:
Claims 1, 2, 6, and 19 under 35 U.S.C. § 102(b) as anticipated by
Ware.
Claims 4, 5, 7, 8, 10-17, and 20-23 under 35 U.S.C. § 103(a) as
unpatentable over the combination of Ware and one of Gustavson or
Ohshima; claims 1, 2, 6, 13, 17, 19, 21, and 22 under 35 U.S.C. § 103(a) as
unpatentable over the combination of Ware and JEDEC; claims 4, 5, 14-16,
20, and 23 under 35 U.S.C. § 103(a) as unpatentable over the combination of
Ware, JEDEC, and Gustavson; and claims 4, 5, 7, 10-12 16, and 20 under 35
U.S.C. § 103(a) as unpatentable over the combination of Ware, JEDEC, and
Inagaki.
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Claim 3 and 18 under 35 U.S.C. § 103(a) as unpatentable over the
combination of Gillingham and one of Ryan or Ohshima.
The Examiner confirms patentability of claim 9.

ISSUE

Did the Examiner err in rejecting claims 1-8 and 10-23?

FINDINGS OF FACT
1) Ware discloses “latency between the clock cycle with the . . .
write command and the clock cycle with the first word of write data is zero”
but that “there is a delay of tCAA which occurs [for a read command]” (col. 8,
ll. 52-55).
2) Ware discloses that because of “wasted clock cycles” (col. 8, l.
56) when the write latency is zero, “the write latency is made programmable
so that is can be adjusted to equal the read latency” (col. 8, ll. 59-61).
3) Ware discloses an example of programming latency in which
“DRAM control logic 500 . . . delays a signal to initiate an operation (Start
R/W) 505 a certain number of clock cycles dependent upon the information
loaded into the latency control register 510” (col. 8, ll. 63-67; Fig. 17) to
“determine whether the signal 505 is immediately input or input after a
predetermined delay . . . .” (col. 9, ll. 6-7).

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PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co. of Kansas City,
383 U.S. 1, 17-18 (1966).
“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).

ANALYSIS
Ware Reference – Anticipation (claims 1, 2, 6, 19)
The Examiner rejects claims 1, 2, 6, and 19 as anticipated by Ware.
We agree with the Examiner for at least the reasons set forth by the
Examiner (see, e.g., Right of Appeal Notice (hereinafter, “RAN”) 10-12).
Claim 1 recites that a write command is “presented internally . . . after
a first delay time has transpired from when the write command is received.”
Appellant argues that Ware fails to disclose this feature (see, e.g., App. Br.
17-18). However, as the Examiner points out and as described above, Ware
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discloses that when a read latency2 is equal to a finite value (e.g., tCAA) and a
write latency3 is equal to zero, there may be undesired “wasted clock
cycles.” In order to address this problem, according to Ware, the write
latency is “made programmable” so that the write latency may be “adjusted
to equal the read latency (FF 1-3).
Ware further discloses an example of programming the latency such
that “a signal to initiate an operation (Start R/W) 505” is delayed within
“DRAM control logic 500” (FF 1-3; Fig. 17; col. 8, ll. 63-66). Hence, Ware
discloses that a write latency is “programmed” so that “a signal to initiate an
operation (Start R/W)”4 is delayed. In other words, Ware discloses a delay
that transpires from when the write command is received (i.e., “the clock
cycle with the . . . write command” – col. 8, ll. 52-53) to when “a signal to
initiate an operation” (col. 8, ll. 64-65) (i.e., the write operation) is applied.
This process is further illustrated in Fig. 17 where a signal to “initiate read or
write sequence” is delayed within the DRAM logic (element 500, Fig. 17).
Appellant has not sufficiently pointed out any meaningful differences
between these features disclosed by Ware and the presently claimed
invention since both claim 1 recites and Ware discloses a delay between
when the write command is received to when a signal is applied (i.e., when
the write command is posted, as recited in claim 1).

2 The time measured “between the clock cycle with the . . . read command
and the clock cycle with the first word of read data” (col. 8, ll. 47-49).
3 The time measured “between the clock cycle with the . . . write command
and the clock cycle with the first word of write data” (col. 8, ll. 52-54).
4 Col. 8, ll. 64-65 – in this case, a signal responsive to the write command
since Ware discloses this “exemplary structure” for programming the write
latency “so that it can be adjusted to equal . . . the read latency” (col. 8, ll.
60-61)
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Appellant argues that “[t]he Start R/W signal [of Ware] is not a write
command” (App. Br. 18) but does not indicate a specialized definition of
“write command” in the Specification. In the absence of a specific
definition of the term “write command,” we construe the term broadly but
reasonably and in light of the Specification to include any instruction or
functional data element that specifies that a device receive write data. This
definition comports with a plain and customary meaning as would have been
understood by one of skill in the art as well as the claim requirement that a
write command specify “that the memory device receive write data.”
As described above and as pointed out by the Examiner, Ware
discloses a “clock cycle with the . . . write command” (col. 8, ll. 52-53)
associated with a write latency that “is made programmable” (col. 8, ll. 60)
by delaying “a signal to initiate an operation” (col. 8, ll. 64-65). We
disagree with Appellant’s assertion that Ware fails to disclose a write
command since Ware explicitly discloses a “write command” (see, e.g., col.
8, l. 53) and an exemplary structure in which a “Start R/W” instruction
initiates an operation that one of skill in the art would have understood to be
a write operation. Since “Start R/W” specifies that a device receive write
data (i.e., initiates a write operation), we disagree with Appellant that there
is any meaningful difference between the “write command” and “Start R/W”
of Ware and the claimed “write command.”
While Appellant argues that “[t]he Start R/W signal [of Ware] is not a
write command” (App. Br. 18), Appellant does not adequately demonstrate
any differences between the “write command” or “Start R/W” of Ware and a
“write command” as recited in claim 1. As described above, the “Start
R/W” of Ware, for example, is delayed (see, e.g., Fig. 17) and initiates an
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operation (e.g., a write operation – e.g., Fig. 17) while the claimed “write
command” is also delayed “posted . . . after a first delay”) and also specifies
“that the memory device receive write data.” In both cases, a write
operation is being specified (after a delay).
Appellant argues that the “Start R/W” of Ware differs from the
claimed “write command” because the “Start R/W” of Ware “is actually a
single bit” (App. Br. 18). Hence, Appellant implies that the write command
recited in claim 1 must not be a “single bit” but does not indicate where in
the claim such a requirement is imposed upon the “write command.” Nor do
we independently find such a requirement in claim 1.
Appellant also argues that the “Start R/W” of Ware differs from the
claimed “write command” as received in claim 1 because “[Ware] does not
even indicate whether the initiated operation is a read or a write operation”
(App. Br. 18). We disagree with Appellant for at least the reasons set forth
above. For example, Ware discloses that the Start R/W “initiate[s] . . . [a]
write sequence” (see, e.g., Fig. 17). (Id. at 18). Appellant does not
sufficiently demonstrate any differences between initiating a “write
sequence” (Ware) and initiating a “write operation.”
Appellant argues that “Ware does not disclose how . . . the Start R/W
signal results in a delayed internal presentation of a write command” and
that “there is nothing in . . . Ware that speaks to . . . [the delay of] the
internal presentation of the write command” (App. Br. 19). As described
above, Ware discloses receiving a write command (e.g., receiving a write
command in a “clock cycle with the . . . write command” – col. 8, ll. 52-53),
making the associated write latency “programmable so that it can be
adjusted” (col. 8, ll. 60-61), and delaying the “signal to initiate an operation”
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(col. 8, ll. 64-65). Given Ware’s explicit disclosure of delaying an
instruction that specifies that a device receive write data (i.e., delaying a
“write command”), we disagree with Appellant’s assertion.
Appellant also argues that Ware discloses a “Start R/W signal” that
“. . . if anything, corresponds to the amount of data ‘latency’ (Murphy Decl.,
¶¶ 35, 37.)” (App. Br. 21). However, as described above, Ware addresses
the problem of “wasted clock cycles” by making a write latency
“programmable” (col. 8, l. 60) and further provides a specific example of
programming such a latency. One of ordinary skill in the art would have
understood that the “latency” (or delay) being programmed in the specific
example of Ware (the specific example immediately following and flowing
from Ware’s description of the problem in which Ware explicitly discloses
that a write latency needs to be programmed) is a write latency (see, in
general, col. 8, ll. 52-67).
Appellant also argues that “Figure 2 [of Ware] does not show any
items to delay the signals . . . nor does it show anything remotely equivalent
to the write delay block 2709 in FIG. 20 of the ‘119 patent” (App. Br. 20).
However, as described above, Appellant has not provided sufficient
evidence that Ware fails to disclose the claimed invention.
Appellant does not provide additional arguments in support of claims
2, 10, or 19 (App. Br. 23-24). The Examiner did not err in rejecting claims
1, 2, 10, and 19 as anticipated by Ware.

Ware Reference - Obviousness (claims 1, 2, 4-8, 10-17, and 19-23)
Regarding claim 7, Appellant argues that that Ware fails to disclose or
suggest a “‘first delay time . . . is capable of being different than the second
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delay time’” as recited in claim 7 (see, e.g., App. Br. 29-30). Appellant
proposes a scenario in Ware where “the second delay . . . is shorter in time
than the first delay” and states that in such a case, “this is not consistent with
claim 7” (App. Br. 30). However, if the second delay “is shorter in time
than the first delay,” as Appellant states, then the second delay is capable of
being “different than” the first delay since the second delay is necessarily
“different than” the first delay (and is therefore “capable of” being different
than the first delay) if the second delay is, in fact, “shorter in time” than the
first delay. We are therefore not persuaded by Appellant’s argument.
Regarding claim 12, Appellant argues that Ware does not disclose
“anything about the length of time before the write command is presented
internally with respect to the length of time between when the read
command is received and before the read command is presented internally”
(App. Br. 30-31). Claim 12 recites a first delay (i.e., time from when a write
command is received to the time when the write command is presented
internally) is greater than the time from when a read command is received to
when the read command is presented internally to the memory device. The
Examiner states that “Ware teaches setting the first delay time . . . to be
greater than the time between the receipt of the read command and its
internal release” (RAN 16).
However, Ware appears to disclose adjusting a write latency “to equal
[the] read latency” (col. 8, l. 61) rather than adjusting a time between
receiving a write command and presenting the write command internally to
be greater than the time between receiving a read command and presenting
the read command internally to the memory device. The Examiner also does
not state that any of Gustavson, Shshima, JEDEC, or Inagaki discloses or
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suggests this feature. Therefore, we agree with Appellant that Ware in
combination with any of Gustavson, Ohshima, JEDEC, or Inagaki does not
disclose this feature.
The Examiner erred in rejecting claim 12 as unpatentable over Ware
and one of Gustavson, Ohshima, or the combination of JEDEC and Inagaki
but did not err in rejecting claims 1, 2, 4-8, 10, 11, 13-17, and 19-23 as
unpatentable over Ware and one of Gustavson, Ohshima, JEDEC, or the
combination of JEDEC and any one of Gustavson or Inagaki.
Appellant argues that it would not have been obvious to one of
ordinary skill in the art to combine the Ware reference with any other
reference because “Rambus’ Direct RDRAM technology have achieved
substantial commercial success” (App. Br. 32) and “Rambus has extensively
licensed the ‘119 patent” (App. Br. 33). However, we agree with the
Examiner that Appellant has failed to adequately demonstrate a nexus since
Appellant does not provide sufficient evidence that clearly connects the
alleged commercial success to the merits of the claimed invention. The
weight given to evidence of secondary considerations is dependent upon
whether there is a nexus between the merits of the claimed invention and the
evidence offered. Stratoflex, Inc. v. Aeroquip Corp., 713 F.2d 1530, 1539
(Fed. Cir. 1983).
As one example, Appellant has not sufficiently established that the
sale of“500 million memory devices incorporating the Rambus . . . memory
interface” (App. Br. 32) constitutes “commercial success” when considered
in relation to overall market share. In fact, Appellant does not appear to
provide any data pertaining to overall market share. Even assuming that the
sale of “500 million memory devices” would have constituted “commercial
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success” as Appellant argues, Appellant has merely alleged that “500 million
memory devices” “incorporated” the “Rambus . . . memory interface.”
Appellant has not adequately demonstrated that any of the “500 million
memory devices” were sold because of the “Rambus . . . memory interface”
supposedly contained therein. In other words, Appellant does not establish a
nexus between the patented invention and the alleged commercial success.
Appellant argues that “Rambus has extensively licensed the ‘119
patent” (App. Br 33). As above and as pointed out by the Examiner,
Appellant does not provide an adequate showing that a nexus exists between
the specific features of the claimed invention and the alleged licensing
activity.
Appellant states that while the Patent Owner must show some causal
relation between an invention and commercial success (citing Merck & Co.,
Inc. v. Teva Pharmaceuticals USA, Inc., 395 F.3d 1364, 1376 (Fed. Cir.
2005)), the Patent Owner, according to Appellant, need not demonstrate that
“the claimed invention must be the sole cause of the commercial success”
(App. Br. 33). Even assuming this allegation to be true, Appellant has not
established the required nexus between the claimed invention and any
alleged commercial success (or licensing). We agree with Appellant’s
implication that Appellant failed to demonstrate that the claimed invention
was the “sole” cause of any potential commercial success (or licensing).
More importantly, however, without an adequate showing of a nexus
between the claimed invention and any alleged commercial success (or
licensing), Appellant has failed to adequately demonstrate that “the claimed
invention” was a cause of the commercial success (assuming that
commercial success even occurred) or that the claimed invention was in any
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way related to any commercial success (or licensing) that might (or might
not) have occurred. Therefore, we are not persuaded by Appellant’s
arguments pertaining to secondary considerations as they relate to the
Examiner’s obviousness rejections.

Gillingham Reference (Claims 3 and 18)
Claim 3 recites a second delay time that matches the third delay time
minus a channel turnaround time and claim 18 recites that the second delay
time corresponds to the third delay time minus a channel turnaround time.
The Gillingham reference (U.S. Patent No. 6,008,774 – the ‘774 patent) was
filed September 19, 1997 (issued July 11, 2000) and is related to U.S.
Provisional Applications 60/026,594 (September 20, 1996); 60/055,349
(August 11, 1997), and 60/057,092 (August 27, 1997). While the Examiner
states that Gillingham (the ‘774 patent) discloses “matching the delay time
accounting for a channel turnaround time (Figure 5B, gaps 525, 530; see
also c8:4-19)” (RAN 7), the Examiner appears to agree that U.S. Provisional
Application 60/026,594 does not disclose this feature, thus according the
Gillingham reference the priority date of August 11, 1997.
Appellant provides a Declaration by “the assignee of [the ‘119
patent]” (Declaration of Craig E. Hampel under 37 C.F.R. § 1.131, executed
on September 8, 2010, ¶ 2), which states that the inventors of the ‘119 patent
“conceived of the inventions claimed in the [‘119 patent]” prior to January 2,
1997 and “continued diligently from prior to January 2, 1997 to October 10,
1997, which is the earliest filing date of [the ‘119 patent]” (Declaration of
Craig E. Hampel under 37 C.F.R. § 1.131, filed April 2, 2010, ¶ 14).
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The Examiner appears to agree with Appellant, however, regarding
claims 3 and 18 the Examiner states that Appellant has not demonstrated that
“the timing diagram [in the Davis email] shows an offset, or second delay
time, of 8 cycles set to match a third delay time (9 cycles) minus a channel
turnaround time (1 cycle)” (RAN 23, citing the Davis email) – Exhibit CA).
In other words, the Examiner finds that Appellant has merely demonstrated
prior conception and reduction to practice or diligence with constructive
reduction to practice of a write delay time (e.g., of 8 cycles – Davis email)
that is less than a channel turnaround time (of 1 cycle – Davis email) less
than a read delay time (of 12 cycles, according to the Examiner – Davis
email) rather than a write delay time (e.g., of 8 cycles – Davis email) that
matches or corresponds to a channel turnaround time (of 1 cycle – Davis
email) less than a read delay time (of 9 cycles – Davis email), as required by
claim 3 or 18.
We disagree with the Examiner for at least the reasons set forth by
Appellant (App. Br. 26-28). As Appellant points out, the Davis email
appears to show the disputed claimed feature at least with the specific
example described in the Davis email of a write delay time of 8 cycles being
equal to a read delay time of 9 cycles minus a channel turnaround time of 1
cycle (see, e.g., App. Br. 26-28).
The Examiner erred in rejecting claims 3 and 18 as unpatentable over
Gillingham any one of Ohshima or Ryan.

CONCLUSION
The Examiner erred in rejecting claims 3 and 18 over Gillingham and
one of Ryan or Ohshima and claim 12 over Ware and one of Gustavson,
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Ohshima, or the combination of JEDEC and Inagaki. The Examiner did not
not err in rejecting claims 1, 2, 4-8, 10, 11, 13-17, and 19-23 over Ware
(alone or in combination with Gustavson, Ohshima, JEDEC, or Inagaki).

DECISION
The Examiner’s decision to reject claims 3 and 18 as obvious over
Gillingham and one of Ryan or Ohshima and claim 12 as obvious over Ware
and one of Gustavson, Ohshima, or the combination of JEDEC and Inagaki
is reversed.
The Examiner’s decision to reject claims 1, 2, 6, and 19 as anticipated
by Ware; claims 4, 5, 7, 8, 10, 11, 13-17, and 20-23 as unpatentable over
Ware and any one of Gustavson or Ohshima; claims 1, 2, 6, 13, 17, 19, 21,
and 22 as unpatentable over Ware and JEDEC; claims 4, 5, 14-16, 20, and
23 as unpatentable over Ware, JEDEC, and Gustavson; and claims 4, 5, 7,
10, 11, 16, and 20 as unpatentable over Ware, JEDEC, and Inagaki is
affirmed.

AFFIRMED-IN-PART
rvb

PATENT OWNER

STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005

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THIRD PARTY REQUESTER

HAYNES AND BOONE, LLP IP SECTION
2323 VICTORY AVENUE
SUITE 700
DALLAS, TX 75219