Ex Parte 6961834 et al

Patent Trial and Appeal Board

Feb 1, 2016

95000669 (P.T.A.B. Feb. 1, 2016)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/000,669 05/30/2012 6961834 ART-12-5015REX 9136
25226 7590 02/02/2016
MORRISON & FOERSTER LLP
755 PAGE MILL RD
PALO ALTO, CA 94304-1018
EXAMINER
CAMPBELL, JOSHUA D
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
02/02/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

ARTERIS, INC.,
Requester,

v.

SONICS, INC.,
Patent Owner.
____________

Appeal 2015-006299
Reexamination Control 95/000,669
Patent 6,961,834 B2
Technology Center 3900
____________

Before STEPHEN C. SIU, BRADLEY W. BAUMEISTER, and
IRVIN E. BRANCH, Administrative Patent Judges.

SIU, Administrative Patent Judge

DECISION ON APPEAL
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Sonics, Inc. (“Patent Owner”) appeals under 35 U.S.C. §§ 134 and
315 the Examiner’s rejections of claims 10–17 over various references and
Arteris, Inc. (“Requester”) appeals under 35 U.S.C. §§ 134 and 315 the
Examiner’s non-adoption of the rejections of claims 1–9 and 18–20 over
various references. PO App. Br. 5–6;1 3PR App. Br. 6–7.2 We have
jurisdiction under 35 U.S.C. §§ 134 and 315. An oral hearing was
conducted on November 16, 2015.
STATEMENT OF THE CASE
This proceeding arose from a May 30, 2012 request by Arteris, Inc.
(“Requester”) for an inter partes reexamination of claims of U.S. Patent
6,961,834 B2, titled “Method and Apparatus for Scheduling of Requests to
Dynamic Random Access Memory Device,” and issued to Wolf-Dietrich
Weber, on November 1, 2005 (“the ’834 patent”).
The ’834 patent describes a method and system of multiple
independent initiators sharing a dynamic random access memory subsystem.
Spec. 2:32–34.
Claims 1, 10, and 18 read as follows:
1. A process for scheduling requests to access a target
resource on a system on a chip, said requests originating from
at least two threads, which come from at least one initiator, said
process comprising combining both 1) a thread result of
scheduling the requests between the threads coming from the at
least one initiator sending those requests, where the scheduling
of the requests between the threads is based on thread state and

1 Patent Owner Appeal Brief, Inter Partes Reexamination, filed December
29, 2014 (“PO App. Br.”).
2 Brief on Appeal by Appellant Requestor in an Inter Partes Reexamination
Proceeding, filed December 29, 2014 (“3PR App. Br.”).
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2) a resource result of scheduling of initiator access to the target
resource for the requests in order to maximize target resource
performance and then processing in the system on the chip a
combined scheduled result of the at least two threads, where the
combined scheduled result of the at least two threads has at
least one of read and write requests, and wherein the at least
one of read and write requests within each thread are processed
in the order that they were issued.

10. A scheduling apparatus for scheduling access to a
resource, comprising:
an input coupled to receive at least one access request
originating from at least one thread from at least one initiator;
logic to combine scheduling of requests between threads
and scheduling of initiator access to the resource and processing
requests within each thread in the order that they are issued.

18. An apparatus for a system on a chip, comprising:
means for scheduling requests of initiator access to a target
resource in order to maximize target resource performance,
wherein the requests originate from at least two threads, which
come from at least one initiator on the system on the chip:
means for combining both i) scheduling of the requests
between the threads based on thread state, and ii) the scheduling
of the requests of initiator access to the target resource; and
means for scheduling of the requests of initiator access to
the target resource and processing requests within each thread
in the order that they are issued.

The cited references are as follows:
Sreenan US 5,742,772 Apr. 21, 1998
Lentz US 5,754,800 May 19, 1998
Huang US 6,212,562 B1 Apr. 3, 2001
Strongin US 6,219,769 B1 Apr. 17, 2001

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L. Lamport, “How to Make a Make a Multiprocessor Computer that
Correctly Executes Multiprocess Programs,” Sept. 1979 (“Lamport”).

Yoshiaki Sudo, et al., “Distributed-thread Scheduling Methods for
Reducing Page-Thrashing,” 1997 (“Sudo”).

Scott Rixner et al., “Memory Access Scheduling,” 2000 (“Rixner”).

Requester appeals the Examiner’s non-adoption of the rejection of
claims 1–9 and 18–20 under 35 U.S.C. § 102 as anticipated by, or under
35 U.S.C. § 103(a) as unpatentable over, any one of Sreenan, Lentz,
Strongin, Huang, or Sudo; under 35 U.S.C. § 103(a) as unpatentable over
Lamport and any one of Sreenan, Lentz, Strongin, Huang, or Sudo; and
under 35 U.S.C. § 112, 1st paragraph; claims 1–9 under 35 U.S.C. § 112,
2nd paragraph; and claim 2 under 35 U.S.C. § 112, 4th paragraph.
Patent Owner appeals the Examiner’s rejection of claims 10–17 under
35 U.S.C. § 102 as anticipated by either one of Lentz or Strongin or under
35 U.S.C. § 103(a) as unpatentable over Lamport and either one of Lentz or
Strongin; claims 10–12 and 16 under 35 U.S.C. § 102 as anticipated by
either one of Sreenan or Huang or under 35 U.S.C. § 103(a) as unpatentable
over Lamport and either one of Sreenan or Huang; and claims 10–16 under
35 U.S.C. § 102 as anticipated by Sudo or under 35 U.S.C. § 103(a) as
unpatentable over Sudo and Lamport.
ISSUE
Did the Examiner err in rejecting claims 10–17 over certain grounds
and not rejecting claims 1–9 and 18–20 over the stated grounds?
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PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co., 383 U.S. 1, 17–
18 (1966).
“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).
ANALYSIS
Patent Owner’s Appeal (Claims 10-17)
Lentz
Claim 10 recites logic to combine scheduling of requests between
threads and scheduling of initiator access to the resource. Patent Owner
argues that Lentz discloses “I/O devices . . . mak[ing] requests to the
memory array” and “considers only the priority of one request versus the
priority of another request in granting access to the memory array.” PO
App. Br. 13. In other words, Patent Owner argues that Lentz fails to
disclose scheduling of initiator access to the resource, as recited in claim 10.
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Requester argues that Lentz discloses this feature. 3PR Resp. Br. 8–93
(citing Lentz 1:60 – 2:8, 2:31–49, 3:7–9, 36–40, 53–57, 14:33–41, claim 3;
Horst Supp. Aff.4 ¶¶ 12–16). We agree with Requester.
For example, Lentz discloses “providing read[] access to the memory
. . . by all processors in a manner which provides for minimum memory . . .
latency while . . . providing for cache coherency.” Lentz 1:67 – 2:4. In
other words, Lentz discloses providing processors with read access to
memory (i.e., scheduling access requests (from processors or “initiators”) to
the resource (or memory)). Lentz also discloses “instructions and data
requests” from controller units that are “pass[ed] . . . to the appropriate
memory port” so that “the necessary data [is sent to or received from] the
[memory control unit].” Lentz 2:32–40. Hence, Lentz discloses requests
from controllers for providing access to memory. Patent Owner does not
point out sufficient differences between the scheduling of “initiator” access
to a “resource,” as recited in claim 10, and the system of Lentz that also
schedules “initiator” access (e.g., processor or controller unit access) to a
“resource” (e.g., a memory).
Regarding claim 12, Patent Owner argues that “[a]t most, Lentz
describes only accounting for a single factor, device priority” and that
“claim 12 is patentable over Lentz for at least this reason.” PO App. Br. 15.
Requester argues that Lentz discloses this feature. 3PR Resp. Br. 9 (citing
Lentz 1:60 – 2:8, 2:31–49, 3:7–9, 3:36–40, 3:53–57, 14:33–41, claim 3;

3 Respondent Brief by Third Party Requestor, filed January 29, 2015 (“3PR
Resp. Br.”).
4 Supplemental Affidavit of Robert W. Horst Under 37 C.F.R. § 1.132, dated
September 25, 2013 (“Horst Supp. Aff.”).
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Horst Supp. Aff. ¶¶ 12–16). We are not persuaded by Patent Owner’s
argument for at least the reasons set forth by Requester.
For example, Lentz discloses “enabl[ing] the processors to access the
[memory] . . . [by] assign[ing] priority to the processors . . . [and] in a
manner which provides for minimum memory . . . latency” and that
assigning priority includes consideration of whether “[t]here is a row match
between a requested address and the address of a previously serviced
request.” Lentz 1:60 – 2:3, 14:45–46. Lentz further discloses that a “row
match comparison is to determine if the present request has the same row
address as a previous request” and “[i]f it does, the port need not incur the
time penalty.” Lentz 13:51–53. In other words, Lentz discloses scheduling
access of processors based on a combination of more than one factor (e.g.,
priority of processors and row address within memory, at least) and not only
“a single factor,” as Patent Owner contends.
In support of claim 14, Patent Owner presents a new argument that
does not appear to have been previously presented to the Examiner. In this
new argument, Patent Owner argues that Lentz discloses an “arbitration
scheme” that “may depend on the number of past times a device has been
serviced or denied service,” but fails to disclose a thread scheduling history
that comprises thread bandwidth usage, as recited in claim 14. PO App. Br.
15–16. Requester argues that Lentz discloses this feature. 3PR Resp. Br. 9.
We are not persuaded by Patent Owner’s newly presented argument.
For example, Lentz discloses that priority of access of devices or
processors may also be based on monitoring “the number of times a device
is granted priority” and determining if the device “is a bus ‘hog’.” Lentz
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5:5. One of skill in the art would have understood that a device that is
deemed a “bus hog” based on monitoring of past behavior of the device
would have historically exhibited high bandwidth usage (hence, a “bus
hog”).
Patent Owner does not provide additional arguments with respect to
the combination of Lentz and Lamport. PO App. Br. 16.
Strongin
Patent Owner argues that Strongin discloses “a memory system that
relies on the ability to reorder memory requests,” but fails to disclose
“processing requests within each thread in the order that they are issued,” as
recited in claim 10. PO App. Br. 16. We are not persuaded by Patent
Owner’s argument for at least the reasons set forth by Requester. 3PR Resp.
Br. 10–11 (citing Strongin 11:22–35, 13:54–63, 15:4–7, 11–17, 57–65, Fig.
6; Horst Aff.5 ¶ 11). For example, as Requester explains, Strongin discloses
that “an ordinal number . . . indicates a request’s order relative to other
requests from the same source” and that an “origin-sensitive first-stage
memory access request reordering device . . . reorder[s] the memory request
on the basis of the source from which the memory transaction originates [or]
the ordinal number.” Strongin 15:4–7, 11–16. In other words, Strongin
discloses that memory requests are ordered based on the “source” of requests
(i.e., based on threads) such that requests within a “thread” (i.e., from a
specific source) may be processed in the order that they are issued (i.e.,
based on the “ordinal number”).

5 Affidavit of Robert W. Horst Under 37 C.F.R. § 1.132 (“Horst Aff.”).
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Strongin further discloses that, in the “origin-sensitive first-stage,” re-
ordering requests may be based on “identification of which stream or thread
resulted in an access” or “whether or not an access can be completed out of
order.” Strongin 13:54–63. In Fig. 6A, as Requester explains, Strongin
discloses that the order of requests in a thread (i.e., from a specified source)
may be deemed “important” (i.e., “order important? Y/N” – Strongin Fig.
6A). In other words, Strongin discloses at least one embodiment in which
the order of requests within a thread (i.e., from a specified source of
requests) is deemed “important” such that “access” cannot be “completed
out of order.” Patent Owner does not explain persuasively a difference
between the disputed claim feature and Strongin’s disclosure of processing
requests from each thread (i.e., from a specified source of requests) in the
order they are issued (i.e., based on “ordinal number” when “order
important” is set to “Y” such that access is not “completed out of order”).
Patent Owner argues that Strongin discloses “source priority and
memory utilization efficiency in reordering memory accesses,” but fails to
disclose logic that utilizes a combination of thread quality of service (QOS)
guarantees and resource cost function scheduling, as recited in claim 12. PO
App. Br. 17–18. We are not persuaded by Patent Owner’s argument for at
least the reasons set forth by Requester. 3PR Resp. Br. 11–12 (citing
Strongin 5:12–23, 13:51 – 14:5, 13:30–36, 17:52–60, 24:47–55; Horst Supp.
Aff. ¶¶ 21–22). For example, Requester argues that Strongin discloses “that
the scheduling takes into account the priority of the source” and equates the
“designated QoS,” as recited in claim 12, with “a designated priority” of
Strongin. 3PR Resp. Br. 11. We credit Requester’s declarant’s (Dr. Robert
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W. Horst) explanation that “a set of requests” of Strongin may or may not be
deemed to be “definitely needed” (i.e., based on “priority”) and, if not, “may
be discarded.” Requests that are of higher priority (as disclosed by
Strongin), according to Dr. Horst, would receive “a higher guaranteed
quality of service (QOS)” and would “receive higher quality service than
others” or be scheduled based on a “QOS guarantee.” Horst Supp. Aff. ¶ 21.
Patent Owner does not refute this testimony persuasively.
Patent Owner argues that Requester’s contention “incorrectly
equate[s] QOS guarantees with . . . device priority” because such requests
“are not related to QOS guarantees” and that “device priorities are not QOS
guarantees.” PO Reb. Br. 9.6 Patent Owner does not provide further
supporting evidence to persuasively demonstrate how or why priority is
supposedly “incorrectly equated” with QoS guarantees. Without such a
showing, Patent Owner’s unsubstantiated, conclusory statements are given
little weight.
Patent Owner argues that it would not have been obvious to one of
ordinary skill in the art to have combined the teachings of Strongin and
Lamport because, according to Patent Owner, doing so “would change the
principle of operation of Strongin” and “would impermissibly render the
memory system of Strongin unsatisfactory for its intended purpose.” In
particular, Patent Owner argues that Strongin must “reorder memory
requests, even from the same thread” and that the combination of Strongin
and Lamport “would result in all memory requests from a processor being

6 Patent Owner’s Rebuttal Brief Under 41.66(D)/41.71, filed April 20, 2015
(“PO Reb. Br.”).
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sequential.” PO App. Br. 19. We are not persuaded by Patent Owner’s
argument for at least the reasons set forth by Requester. 3PR Resp. Br. 12.
For example, as previously discussed, Strongin discloses an
embodiment in which the “order” of requests is deemed “important” (i.e.,
the “order important?” flag set to “Y”) such that requests within a thread are
processed in order. We disagree with Patent Owner that the “intended
purpose” or “principle of operation” of Strongin is to “reorder memory
requests” within the same thread because, if reordering memory requests
within the same thread was, in fact, the “principle of operation” of Strongin,
one of skill in the art would not expect the Strongin system to violate its own
“principle of operation” by providing for an affirmative response to the
“order important?” flag and resulting lack of reordering of memory requests
within the same thread.
Requester’s Appeal
Written Description - Claims 1-9 and 18-20
Claim 1 recites “thread result” and “resource result.” Requester
argues that there is insufficient written description support for these claim
terms. 3PR App. Br. 14. The Examiner states that the Specification
discloses these features. RAN 307 (citing Spec. Fig. 3). Patent Owner
concurs with the Examiner. PO Resp. Br. 4.8 We are not persuaded by
Requester’s arguments for at least the reasons set forth by the Examiner and
Patent Owner. For example, as the Examiner points out, the Specification

7 Right of Appeal Notice, dated September 26, 2014 (“RAN”).
8 Patent Owner’s Respondent Brief Under 41.66(B)/41.68, filed January 29,
2015 (“PO Resp. Br.”).
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discloses a “Thread QOS Scheduler” that provides an output. Spec. Fig. 3.
The Specification also discloses a “DRAM Scheduler” that provides an
output. Spec. Fig. 3. One of skill in the art would have understood that the
output would be a “result” (i.e., a “thread result” or “resource result”).
Requester argues that the terms “thread result” and “resource result”
“are not used anywhere in the Specification of the ’834 patent.” 3PR App.
Br. 14. However, Requester does not demonstrate sufficiently that exact
terms must be disclosed in the Specification to satisfy the written description
requirement. Rather, the Specification provides sufficient written
description support if it conveys with reasonable clarity to those skilled in
the art that Patent Owner was in possession of the invention as claimed. See,
e.g., Vas-Cath, Inc. v. Mahurkar, 935 F.2d 1555, 1563–64 (Fed. Cir. 1991).
We agree with the Examiner and Patent Owner that the disclosure in the
Specification of a “thread scheduler” providing an output would convey with
reasonable clarity to those skilled in the art that Patent Owner was in
possession of a “thread result” and that the disclosure in the Specification of
a “DRAM Scheduler” (the DRAM being a “resource”) providing an output
would convey with reasonable clarity to those skilled in the art that Patent
Owner was in possession of a “resource result.”
Claim 1 also recites “at least two threads, which come from at least
one initiator.” Claim 18 recites a similar feature. Requester argues that the
Specification discloses only “scheduling request between threads coming
from different initiators, not . . . scheduling requests between threads coming
from a single initiator.” 3PR App. Br. 14 (citing Spec. 1:7–9, 13–16, 32–33,
2:32–39, 41–48). Patent Owner argues that this feature is disclosed in the
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Specification. PO Resp. Br. 5 (citing Spec. 2:40–50). The Examiner states
that the Specification discloses “requests coming from 3 different threads
into the scheduler.” RAN 30 (citing Spec. Fig. 3, 3:25–30).
The Specification discloses “a DRAM scheduling system” in which
“[r]equests . . . from different initiators are communicated across different
threads.” Spec. 2:44–46. Hence, the Specification discloses that each
initiator provides a thread of requests. Patent Owner does not point out that
the Specification also discloses that an initiator provides “at least two
threads,” as recited in claims 1 and 18.
The Specification also discloses “one embodiment of the DRAM and
Thread Scheduler” in which “requests . . . from different threads are
presented and sequenced to the DRAM controller.” Spec. 3:25–28. Hence,
the Specification discloses the access requests are sequenced. The Examiner
(or Patent Owner) does not demonstrate sufficiently that the Specification
also discloses that the at least two threads (of requests) come from one
initiator, as recited in claims 1 and 18.
The Examiner erred in not adopting the rejection of claims 1–9 and
18–20 under 35 U.S.C. § 112, first paragraph.
Indefiniteness - Claims 1-9
Claim 1 recites combining a “thread result” and “a resource result.”
Claim 2 further recites that the combining comprises “using a combination
of thread quality of service (QoS) scheduling and resource scheduling.”
Claim 3 depends from claim 2 and recites that the combining further
comprises “determining an order of requests to meet QoS guarantees” and
“determining an order of requests for resource efficiency.”
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Requester argues that claims 1 and 2 (and claim 3) are “insolubly
ambiguous” because “the element recited in claim 2 . . . is already
encompassed within the [combining of claim 1].” 3PR App. Br. 16. Patent
Owner argues that claims 2 (and dependent claim 3) are definite because “it
is clear that the additional factors recited in . . . claims [2 and 3] are part of
the ‘combining’ of claim 1.” PO Resp. Br. 6. We agree with Patent Owner.
Claim 1 recites combining a thread result and a resource result. Claim
2 recites that the combining comprises using a combination of thread quality
of service scheduling and resource scheduling. One of skill in the art would
have understood that claim 2 includes combining a thread result and a
resource result that comprises using a combination of thread quality of
service scheduling and resource scheduling, as recited in claim 2. We are
not persuaded by Requester’s argument that “using a combination of thread
quality of service scheduling and resource scheduling,” as recited in claim 2,
is “already encompassed within” combining a thread result and a resource
result. Even if the limitation recited in claim 2 is somehow “already
encompassed within” the limitation recited in claim 1, Requester does not
explain sufficiently how such an encompassing of claim features would
result in ambiguity to one of skill in the art.
Claim 1 recites scheduling the requests between the threads “based on
thread state.” Claim 7 recites that the scheduling “is determined by
prioritizing threads according to bandwidth usage and sequencing the
requests from the different threads.” Claim 8 recites that the scheduling “is
selected from the group consisting of absolute and cost-function
scheduling.” Claim 9 recites that the scheduling is “selected from the group
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consisting of deciding when to close dynamic random access page (DRAM)
and open another, and deciding when to switch DRAM requests to use a
different physical bank of DRAM, and deciding when to switch direction of
a bus coupled to the DRAM.”
Requester argues that “[i]t is unclear whether the ‘scheduling’ referred
to in each of claims 7–9 are encompassed within any of the types of
scheduling recited in claim 1, or whether they are referring to different acts
of scheduling” and that the claim recitation “makes it uncertain as to
whether they are meant to refer to a new scheduling, or merely to the
‘process for scheduling.’” 3PR App. Br. 17.
We are not persuaded by Requester’s arguments. One of skill in the
art would have understood that claim 1 requires scheduling based on thread
state and that claims 7–9 require additional scheduling as recited in each of
claims 7–9. Requester does not explain sufficiently how the presumed fact
that any of the “scheduling” recited in any of claims 7–9 may or may not be
an integral part of the “scheduling” recited in claim 1 or why a separate
“scheduling” would result in ambiguity to one of skill in the art.
The Examiner did not err in not adopting the rejection of claims 1–9
under 35 U.S.C. § 112, second paragraph.
35 U.S.C. § 112, fourth paragraph - Claim 2
Claim 1 recites combining a thread result (based on thread state) and a
resource result of scheduling of initiator access to the target resource. Claim
2 depends from claim 1 and recites that the “combining comprises using a
combination of thread quality of service (QoS) scheduling and resource
scheduling.”
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Requester argues that “[c]laim 2 [which depends from claim 1] is . . .
actually broader than claim 1” because “the elements of the combining step
of claim 1 . . . are actually species of the elements of the combination recited
in claim 2.” 3PR App. Br. 18. Specifically, Requester argues that “the
Specification . . . teaches that one way to provide ‘quality of service (QOS)
scheduling’ as recited in claim 2 is to provide ‘a thread result . . . based on
thread state’ as recited in claim 1” and that “the Specification . . . teaches
that one way to provide ‘resource scheduling’ as recited in claim 2 is to
provide ‘a resource result of scheduling of initiator access to the target
resource for the requests in order to maximize target resource performance’
as recited in claim 1.” 3PR App. Br. 18 (citing Spec. 3:32–34, 38–40). We
are not persuaded by Requester’s argument.
As Requester points out, the Specification discloses that “one way to
provide” QoS scheduling is by using “a thread result” based on thread state.
However, this disclosure, without more, is insufficient to demonstrate that
providing QoS scheduling does not further limit the use of a “thread result”
based on thread state. For example, the Requester does not allege that the
Specification discloses using a “thread result” based on thread state is only
used for providing QoS scheduling or that providing QoS scheduling can
only be accomplished by using a “thread result” based on thread state.
Hence, the Specification does not preclude a condition in which a “thread
result” based on a thread state may be used to provide QoS scheduling and
may also be used to provide other features. Under this hypothetical
scenario, claim 2 would further limit claim 1 by reciting a specific use of a
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“thread result” based on thread state, the specific use being to provide QoS
scheduling.
The Examiner did not err in not adopting the rejection of claim 2
under 35 U.S.C. § 112, fourth paragraph.
Lentz - obviousness
Claim 1 recites combining “a thread result of scheduling the requests
between the threads . . . based on thread state” and “a resource result of
scheduling of initiator access to the target resource for the requests in order
to maximize target resource performance.” The Examiner states that Lentz
fails to disclose “the combination,” as recited in claim 1. RAN 53. Patent
Owner concurs with the Examiner. PO Resp. Br. 11–13 (citing Jantsch Aff.9
¶¶ 10, 24, 25; Lentz 14:35–42, 62–65). We are not persuaded by Patent
Owner’s arguments for at least the reasons set forth by Requester. 3PR App.
Br. 21–22 (citing Lentz 1:60 – 2:8, 2:31–49, 3:7–9, 36–40, 53–57, 14:33–41,
claim 3; Horst Supp. Aff. ¶¶ 12–16).
For example, as previously discussed, Lentz discloses “enabl[ing] the
processors to access the [memory] . . . [by] assign[ing] priority to the
processors . . . [and] in a manner which provides for minimum memory . . .
latency” and that assigning priority includes consideration of the “intrinsic
priority of the device” and whether “[t]here is a row match between a
requested address and the address of a previously serviced request.” Lentz
1:60–2:3, 14:44–46. Lentz further discloses that a “row match comparison
is to determine if the present request has the same row address as a previous

9 Affidavit Pursuant to 37 C.F.R. § 1.132 and MPEP 2616, dated September
25, 2012 (“Jantsch Aff.”).
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request” and “[i]f it does, the port need not incur the time penalty.” Lentz
13:51–53. In other words, Lentz discloses scheduling a request to access a
memory based on a combination of, at least, an intrinsic priority of the
requesting device (e.g., a “thread result”) and a row match within the
memory (i.e., a “resource result”). While the Examiner and Patent Owner
indicate that Lentz fails to disclose the “combining,” as recited in claim 1,
neither the Examiner nor Patent Owner demonstrate a sufficient difference
between scheduling access to a memory based on the combination of a
thread result and resource result, as recited in claim 1, and scheduling access
to a memory based on the combination of the priority of the requesting
device and a row match within the memory that receives the access
request(s). In both cases, scheduling of access requests is performed based
on a combination of factors.
The Examiner also states that Lentz fails to “disclose the limitation
‘processing in the system on the chip a combined scheduled result of the at
least two threads,’ as recited in claim 1, and ‘the requests originate from at
least two threads, which come from the at least one initiator on the system
on the chip,’” as recited in claim 18. RAN 53–54. Patent Owner concurs
with the Examiner. PO Resp. Br. 11.
We are not persuaded by Patent Owner’s arguments for at least the
reasons set forth by Requester. 3PR App. Br. 19, 21. For example, even if
Lentz fails to disclose the precise phrase “system on a chip,” “if a technique
has been used to improve one device, and a person of ordinary skill in the art
would recognize that it would improve similar devices in the same way,
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using the technique is obvious unless its actual application is beyond his or
her skill.” KSR, 550 U.S. at 417.
In the present case, as Patent Owner implies, Lentz discloses a
technique that is used to improve a system that may not be disclosed
explicitly as being entirely contained on one chip. However, Patent Owner
does not assert or demonstrate sufficiently that a person of ordinary skill in
the art would not have recognized that the technique of Lentz somehow
would have improved a similar known system (on a chip) in the same way.
Nor does Patent Owner provide evidence to show that effecting such a
modification was “uniquely challenging or difficult for one of ordinary skill
in the art.” See Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157,
1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 418).
Patent Owner does not provide additional arguments with respect to
Lentz or Lamport. PO Resp. Br. 13.
The Examiner erred in refusing to adopt the rejection of claims 1–9
and 18–20 as unpatentable over Lentz, either alone or in combination with
Lamport.
Strongin - obviousness
Claim 1 recites combining “a thread result of scheduling the requests
between the threads . . . based on thread state” and “a resource result of
scheduling of initiator access to the target resource for the requests in order
to maximize target resource performance.” The Examiner states that
Strongin discloses “[u]tilizing [a] two stage mechanism,” but fails to
disclose “combining,” as recited in claim 1. RAN 57–60 (citing Strongin
13:51 – 14:5). Patent Owner concurs with the Examiner. PO Resp. Br. 13–
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14. We are not persuaded by Patent Owner’s arguments for at least the
reasons set forth by Requester. 3PR App. Br. 23–25.
For example, Strongin discloses performing a “first stage which uses
information . . . regarding . . . qualitative aspects of each memory request”
and a “second stage which utilizes . . . the state of system memory” in order
to “ultimately determine the order in which memory access will be carried
out” and that these two phases are performed “in conjunction” with each
other. Strongin 13:54–67, 13:67 – 14:1, 14:33. Neither the Examiner nor
Patent Owner asserts or demonstrates sufficiently a difference between
(1) two elements that are “combined” for use and (2) using the two elements
“in conjunction” with each other. In both cases, both elements are utilized
together to determine the order of memory access.
Claim 1 recites a “process for scheduling requests to access a target
resource on a system on a chip.” Patent Owner also argues that Strongin
fails to disclose or suggest “the ‘system on a chip’ limitations.” PO Resp.
Br. 7, 13. Requester argues that Strongin discloses this feature. 3PR Reb.
Br. 3–4.10 This issue was previously discussed above with respect to Lentz.
We are not persuaded by Patent Owner’s arguments.
Patent Owner argues that “Strongin cannot be combined with Lamport
to process requests in order because to make such a combination would
change the principle of operation of Strongin and would result in Strongin
being unfit for its intended purpose” and
would impermissibly render the memory system of Strongin
unsatisfactory for its intended purpose [because] . . . the memory

10 Rebuttal Brief On Appeal By Appellant Requestor, filed April 20, 2015
(“3PR Reb. Br.”).
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system of Strongin relies on the ability to reorder memory access,
even memory access[] from the same thread . . . [and] [r]emoving
this capability of Strongin . . . would render Strongin incapable
of its intended purpose.
PO Resp. Br. 8, 14–15. This issue was previously addressed above. We are
not persuaded by Patent Owner’s arguments.
Patent Owner does not provide additional arguments with respect to
Strongin or Lamport. The Examiner erred in refusing to adopt the rejection
of claims 1–9 and 18–20 as unpatentable over Strongin, alone or in
combination with Lamport.
In view of the above, we need not consider the propriety of the
Examiner’s adoption or non-adoption of the rejection of claims 1–20 based
on other grounds, such as anticipation or obviousness grounds based on
Sreenan, Huang, or Sudo; anticipation grounds based on either Strongin or
Lentz with respect to claims 1–9 and 18–20, or obviousness grounds
regarding claim 14 based on Strongin. Cf. In re Gleave, 560 F.3d 1331,
1338 (Fed. Cir. 2009).
DECISION
We affirm the Examiner’s rejection of claims 10–17 under 35 U.S.C.
§ 102(b) as anticipated by Lentz or under 35 U.S.C. § 103(a) as unpatentable
over Lentz and Lamport; claims 10–13 and 15–17 under 35 U.S.C. § 102(e)
as anticipated by Strongin or under 35 U.S.C. § 103(a) as unpatentable over
Strongin and Lamport. We also affirm the Examiner’s non-adoption of the
rejection of claims 1–9 under 35 U.S.C. § 112, second paragraph, and of
claim 2 under 35 U.S.C. § 112, fourth paragraph.
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We reverse the Examiner’s non-adoption of the rejection under
35 U.S.C. § 112, first paragraph, of claims 1–9 and 18–20 and the
Examiner’s non-adoption of the rejection of claims 1–9 and 18–20 under
35 U.S.C. § 103(a) as unpatentable over any one of Lentz or Strongin or any
one of Lentz or Strongin in combination with Lamport.
Pursuant to 37 C.F.R. § 41.77(a), the above-noted reversal constitutes
a new ground of rejection. Section 41.77(b) provides that “[a] new ground
of rejection . . . shall not be considered final for judicial review.” That
section also provides that Patent Owner, WITHIN ONE MONTH FROM
THE DATE OF THE DECISION, must exercise one of the following two
options with respect to the new grounds of rejection to avoid termination of
the appeal proceeding as to the rejected claims:
(1) Reopen prosecution. The owner may file a response
requesting reopening of prosecution before the examiner. Such
a response must be either an amendment of the claims so
rejected or new evidence relating to the claims so rejected, or
both.

(2) Request rehearing. The owner may request that the
proceeding be reheard under § 41.79 by the Board upon the
same record. The request for rehearing must address any new
ground of rejection and state with particularity the points
believed to have been misapprehended or overlooked in
entering the new ground of rejection and also state all other
grounds upon which rehearing is sought.

In accordance with 37 C.F.R. § 41.79(a)(1), the “[p]arties to the
appeal may file a request for rehearing of the decision within one month of
the date of: . . . [t]he original decision of the Board under § 41.77(a).” A
request for rehearing must be in compliance with 37 C.F.R. § 41.79(b).
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Comments in opposition to the request and additional requests for rehearing
must be in accordance with 37 C.F.R. § 41.79(c)–(d), respectively. Under
37 C.F.R. § 41.79(e), the times for requesting rehearing under paragraph (a)
of this section, for requesting further rehearing under paragraph (c) of this
section, and for submitting comments under paragraph (b) of this section
may not be extended.
An appeal to the United States Court of Appeals for the Federal
Circuit under 35 U.S.C. §§ 141–144 and 315 and 37 C.F.R. § 1.983 for an
inter partes reexamination proceeding “commenced” on or after November
2, 2002, may not be taken “until all parties’ rights to request rehearing have
been exhausted, at which time the decision of the Board is final and
appealable by any party to the appeal to the Board.” 37 C.F.R. § 41.81. See
also MPEP § 2682 (8th ed., Rev. 8, July 2010).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.
In the event neither party files a request for rehearing within the time
provided in 37 C.F.R. § 41.79, and this decision becomes final and
appealable under 37 C.F.R. § 41.81, a party seeking judicial review must
timely serve notice on the Director of the United States Patent and
Trademark Office. See 37 C.F.R. §§ 90.1 and 1.983.

AFFIRMED-IN-PART
37 C.F.R. § 41.77(b)

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Patent Owner:

MORRISON & FOERSTER LLP
755 PAGE MILL RD
PALO ALTO, CA 94304-1018

Third Party Requester:

PATENT GROUP
C/O DLA PIPER US LLP
203 N. LaSALLE ST., SUITE 1900
CHICAGO, IL 60601