Ex Parte 6,856,540 et al

Patent Trials and Appeals BoardAug 27, 2014

95001474 - (D) (P.T.A.B. Aug. 27, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/001,474 10/25/2010 6,856,540 028489-000400US 1578 25096 7590 08/28/2014 PERKINS COIE LLP - SEA General PATENT-SEA P.O. BOX 1247 SEATTLE, WA 98111-1247 EXAMINER ANDUJAR, LEONARDO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 08/28/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ SIDENSE CORPORATION Requester and Respondent v. KILOPASS TECHNOLOGIES, INC. Patent Owner and Appellant ____________________ Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. US 6,856,540 B2 Technology Center 3900 ____________________ Before MARC S. HOFF, ANDREW J. DILLON, and JENNIFER L. McKEOWN, Administrative Patent Judges. HOFF, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Patent Owner Kilopass Technologies, Inc. appeals under 35 U.S.C. §§ 134(b) and 315(a) (2002) from the rejection of claims 1, 3-9 and 11-24 1 as 1 Claim 10 has been cancelled. The Examiner did not adopt the proposed rejections of claim 2 set forth in the Request for Reexamination. Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 2 set forth in the Right of Appeal Notice (“RAN”) mailed September 6, 2012. Patent Owner filed a brief (“PO App. Br.”) on November 21, 2012 and a rebuttal brief (“PO Reb. Br.”) on October 31, 2013. Third Party Requester Sidense Corp. filed a Respondent’s Brief on December 21, 2012 and a Supplemental Respondent’s Brief (“Resp. Br.”) on March 18, 2013. The Examiner mailed an Examiner’s Answer (“Ans.”) on October 2, 2013, which incorporated the RAN by reference. We have jurisdiction under 35 U.S.C. §§ 134 and 315. We reverse. United States Patent 6,856,540 B2 (hereinafter “’540 Patent”) issued to Peng on February 15, 2005, and is assigned to Kilopass Technologies, Inc. The ’540 Patent concerns a programmable memory cell located at the crosspoint of a column bitline and a row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor (Abstract). Claim 1 is exemplary of the claims on appeal: A programmable memory cell useful in a memory array having column bitlines and row wordlines, the memory cell comprising: a transistor having a gate, a gate dielectric between the gate and over a substrate such that there is a stack comprising said gate, gate dielectric, and substrate, without any intervening conductive material, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region there between and under said gate, the gate being formed from one of said column bitlines; a row wordline segment coupled to the second doped semiconductor region of the transistor, said row wordline segment connected to one of said row wordlines; and Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 3 a programmed doped region formed in said substrate in said channel region when said memory cell has been programmed. The Examiner relies upon the following prior art in rejecting the claims on appeal: 1. Mohsen et al., US Patent 4,876,220 date filed November 13, 1987; date published October 24, 1989 (hereafter “Mohsen”). 2. Rasras et al., Substrate Hole Current Origin after Oxide Breakdown, pp. 537-540 IEEE 2000 (hereafter “Rasras”). 3. Bertin et al., US Patent 6,531,410 date filed February 27, 2001; date published March 11, 2003 (hereafter “Bertin ’410”). 4. Bertin et al., US Patent 6,396,120 date filed March 17, 2000; date published May 28, 2002 (hereafter “Bertin ’120”). 5. Au et al., US Patent 5,672,994 date filed December 21, 1995; date published September 30, 1997 (hereafter “Au”). 6. Keeney et al., US Patent 5,801,991 date filed March 31, 1997; date published September 1, 1998 (hereafter “Keeney”). 7. Ogura et al., A Half Micron MOSFET Using Double Implanted LDD; International Electron Devices Meeting; pp. 718-721 IEEE 1982 (hereafter “Ogura”). The claims stand rejected over various combinations of prior art references (see RAN 2-3): References Claims Basis (§) Mohsen 1, 3-7, 9, and 11 102(b) Mohsen and Keeney 8 103(a) Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 4 Mohsen and Bertin ’410 1-5, 7, 9, and 12 103(a) Mohsen, Bertin ’410, and Ogura 6 and 11 103(a) Mohsen, Bertin ’410, and Keeney 8 103(a) Mohsen and Bertin ’120 1-5, 7, 9, and 12-24 103(a) Mohsen, Bertin ’120, and Ogura 6 and 11 103(a) Mohsen, Bertin ’120, and Keeney 8 103(a) Mohsen and Rasras 1, 3-5, 7, 9, and 12-24 103(a) Mohsen, Rasras, and Ogura 6 and 11 103(a) Mohsen, Rasras, and Keeney 8 103(a) Mohsen and Au 1-4, 7, and 12 103(a) Mohsen, Au, and Ogura 6 and 11 103(a) Mohsen, Au, and Keeney 8 103(a) Mohsen 12 103(a) Mohsen, Rasras, and Bertin ’410 13-24 103(a) Mohsen, Bertin ’120, and Bertin ’410 13-24 103(a) Mohsen, Rasras, and Au 13-24 103(a) Mohsen, Bertin ’120, and Au 13-24 103(a) ISSUE Patent Owner argues, inter alia, that Mohsen does not disclose a stack comprising a gate, gate dielectric, and substrate, without any intervening conductive material, as each of the claims requires (PO App. Br. 11). Patent Owner asserts that the bottom conducting electrode (“PLIDE region 218”) of Mohsen amounts to intervening conductive material positioned between the gate dielectric and substrate (PO App. Br. 11-12). Patent Owner contends that “the term substrate is commonly understood to refer to the bulk semiconductor that carries or supports other components. Once an element has been formed in the substrate, that element is no longer considered ‘substrate’” (PO App. Br. 12). Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 5 Requester agrees with the Examiner’s finding that the bottom conducting electrode of Mohsen is incorporated or formed in an appropriate area on or in the substrate (Resp. Br. 6). Requester contends that “a substrate that includes an element is still a substrate” (id.). The arguments made by Patent Owner and Requester present us with the following issue: Does Mohsen disclose a programmable memory cell or memory array comprising a plurality of such cells, each cell including a stack comprising a gate, gate dielectric, and substrate, without any intervening conductive material? PRINCIPLES OF LAW “A rejection for anticipation under section 102 requires that each and every limitation of the claimed invention be disclosed in a single prior art reference.” See In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007) (quoting In re Paulsen, 30 F.3d 1475, 1478-79 (Fed. Cir. 1994)). Section 103(a) forbids issuance of a patent when ‘the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains.’ KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398, 406 (2007). The question of obviousness is resolved on the basis of underlying factual determinations including (1) the scope and content of the prior art, (2) any differences between the claimed subject matter and the prior art, (3) the level of skill in Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 6 the art, and (4) where in evidence, so-called secondary considerations. Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966). See also KSR, 550 U.S. at 407, (“While the sequence of these questions might be reordered in any particular case, the [Graham] factors continue to define the inquiry that controls.”) ANALYSIS Each of the claims under reexamination shares a common set of limitations whose treatment we find to be dispositive of this appeal. Claim 1 recites a programmable memory cell comprising a transistor having a gate, a gate dielectric between the gate and over a substrate such that there is a stack comprising said gate, gate dielectric, and substrate, without any intervening conductive material. Claim 7 recites a method of operating a programmable memory array comprising a plurality of memory cells, said memory cells comprising a transistor having a gate, a gate dielectric between the gate and over a substrate such that there is a stack comprising said gate, gate dielectric, and substrate, without any intervening conductive material. Newly added claims 13, 18, 23, and 24 recite a programmable memory cell comprising a transistor including a gate of a first conductivity type positioned over a substrate of a different conductivity type, and a gate dielectric between the gate and the substrate such that there is a stack comprising said gate, the gate dielectric, and the substrate, without any intervening conductive material between the gate and the substrate. The Examiner finds that Mohsen discloses such a stack structure, including gate 226, gate dielectric 228 and substrate 200 (RAN 10-11; Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 7 Mohsen Figs. 9a, 9d, 9e and col. 7, l. 59 – col. 8, l. 51). Figure 9d is reproduced below. Figure 9d of Mohsen illustrates a step in the process for incorporating a PLIDE into a standard CMOS process. The Examiner finds that “the channel region is included in the substrate” (RAN 11) and that Mohsen makes clear that “source/drain regions 232 and channel region 218 of the PLIDE element are all formed in substrate 200. Because channel region 218 is formed inside and is part of substrate 200, it cannot be said that channel region 218 intervenes substrate 200 and gate dielectric 228” (RAN 62-63). Requester agrees with the Examiner, arguing that “a substrate that includes an element is still a substrate” (Resp. Br. 6). Requester cites Mohsen’s disclosure that a PLIDE element “can be incorporated in an appropriate area on a substrate 200” (Resp. Br. 6; Mohsen col. 7, l. 63 – col. 8, l. 7). Requester repeats the Examiner’s finding that source/drain regions 232 and channel region 218 of Mohsen are all formed “in the substrate” (Resp. Br. 6). Requester therefore reasons that because channel region 218 is inside of and part of substrate 200, there is no intervening conductive material in the Mohsen device (id.). We do not agree with the Examiner’s finding. Rather, we are persuaded by Patent Owner’s arguments. Patent Owner begins with the Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 8 uncontested statement that “the term substrate is commonly understood to refer to the bulk semiconductor that carries or supports other components” (PO App. Br. 12). We further agree with Patent Owner that “[o]nce an element has been formed in the substrate, that element is no longer considered ‘substrate’” (id.). We agree with Patent Owner that “[t]aking the Examiner’s position would result in common semiconductor elements such as source, drain, wells, emitters, collectors, and any vertical semiconductor device being considered ‘substrate’” (id.). With respect to Mohsen, we find, in agreement with Patent Owner’s position, that while PLIDE region 218 was part of substrate 200 before processing, the region is then “doped with a medium dose of boron” (col. 8, ll. 8-9). This changes the conductivity profile of region 218 (to p-type), so that it is electrically distinct from underlying substrate 200. It is in fact the intended result of the semiconductor processing disclosed in Mohsen that region 218 should be electrically distinct from the substrate; if it were not distinct, the device of Mohsen would not operate as it is meant to operate. We find that PLIDE region 218 of Mohsen, and analogous regions in other figures such as electrode 12 (Figures 1 and 2) and electrode 44 (Figure 3), constitutes conductive material that intervenes between gate (226 in Fig. 9) and substrate (200 in Fig. 9). As a result, we find that Mohsen cannot anticipate the invention recited in claims 1, 3-7, 9, and 11. Further, because Mohsen is relied upon to teach the “stack” recited in each of the other independent claims, and by incorporation each of the dependent claims as well, and forms part of every ground of rejection now present in the record, we find that the Examiner erred in rejecting the claims under § 103 over Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 9 Mohsen in view of the various combinations of references set forth in the Right of Appeal Notice. We do not sustain the rejections of claims 1, 3-9, and 11-24. CONCLUSION Mohsen does not disclose a programmable memory cell or memory array comprising a plurality of such cells, each cell including a stack comprising a gate, gate dielectric, and substrate, without any intervening conductive material. ORDER The Examiner’s rejection of claims 1, 3-9, and 11-24 is reversed. REVERSED Appeal 2014-006008 Reexamination Control 95/001,474 Patent No. 6,856,540 B2 10 alw Patent Owner: Perkins Coie LLP – SEA General Patent – SEA P.O. Box 1247 Seattle, WA 98111-1247 Third Party Requester: Barmak Sani Kilpatrick, Townsend & Stockton LLP Two Embarcadero Center, Eighth Floor San Francisco, CA 94111-3834