Ex Parte 6825683 et al

Patent Trial and Appeal Board

Nov 12, 2015

95001665 (P.T.A.B. Nov. 12, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,665 06/17/2011 6825683 42299.21 9958
13992 7590 11/12/2015
NDQ Special Reexam Group
1000 Louisiana Street, Fifty-Third Floor
Houston, TX 77002
EXAMINER
DEB, ANJAN K
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/12/2015 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

XILINX, INC.
Requester and Respondent

v.

INTELLECTUAL VENTURES MANAGEMENT
Patent Owner and Appellant
____________

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Patent 6,825,683 B1
Technology Center 3900
____________

Before ERIC B. CHEN, JEREMY J. CURCURI, and
JENNIFER L. MCKEOWN, Administrative Patent Judges.

CHEN, Administrative Patent Judge.

DECISION ON APPEAL

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Patent Owner Intellectual Ventures Management appeals under 35
U.S.C. § 134(b) and 35 U.S.C. § 315(a) (pre-AIA) the Examiner’s final
decision to reject claims 1–34. New claims 19–34 have been added during
the reexamination proceeding.
Third-Party Requester Xilinx, Inc. filed a notice of withdrawal from
the inter partes reexamination proceeding, dated May 8, 2014.
An oral hearing scheduled for September 15, 2015 has been waived.
We affirm-in-part.

STATEMENT OF THE CASE
U.S. Patent No. 6,825,683 B1 (“’683 patent”), entitled “System and
Method for Testing Multiple Integrated Circuits that are in the Same
Package,” issued November 30, 2004, to Paul D. Berndt, Jarie G. Bolander,
and Leah S. Clark, based on Application No. 10/125,117, filed April 18,
2002.
A request for inter partes reexamination of ’683 patent, assigned
Reexamination Control No. 95/001,665, was filed on June 17, 2011, by
Requester Xilinx, Inc.

The Claims
Independent claims 1 and 17 are exemplary, with disputed limitations
in italics:
1. A system for testing integrated circuits comprising:
a signal generator generating a plurality of test signals; and
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a device under test coupled to receive the plurality of test
signals in parallel, the device under test including a first integrated
circuit and a second integrated circuit that are in a single package,
the second integrated circuit including a plurality of input
terminals not directly accessible from external terminals of the device
under test,
the first integrated circuit including a test circuit configured to
allow routing of the plurality of test signals to the plurality of input
terminals of the second integrated circuit in parallel.

17. A multi-chip module comprising:
means for decoding and executing command signals in the first
integrated circuit; and
means for accessing a plurality of terminals of a second
integrated circuit based at least on a signal in the command signals,
the means for accessing being in the second integrated circuit, the first
integrated circuit and the second integrated circuit being in the same
multi-chip module.

The Rejections
Patent Owner appeals the Examiner’s decision to reject all the
pending claims as follows:
1. Claims 17 and 18 stand rejected under 35 U.S.C. § 102(b) as
anticipated by System-Chip Test Strategies (SCTS) (Yervant Zorian,
System-Chip Test Strategies, 35 PROC. ANN. DESIGN AUTOMATION CONF.
752–57 (1998).)
2. Claims 17 and 18 stand rejected under 35 U.S.C. § 102(b) as
anticipated by Rajski (Janusz Rajski & Jerzy Tyszer, Modular Logic Built-In
Self-Test for IP Cores, PROC. IEEE INT’L TEST CONF. 313–21 (1998)).
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3. Claim 17 stands rejected under 35 U.S.C. § 102(b) as
anticipated by Dervisoglu (US 6,687,865 B1; Feb. 3, 2004).
4. Claims 1–3 and 10 stand rejected under 35 U.S.C. § 103(a) as
obvious over Aerts (Joep Aerts & Erik Jan Marinissen, Scan Chain Design
for Test Time Reduction in Core-Based ICs, PROC. INT’L TEST CONF. 448–57
(1998)) and Zorian (Yervant Zorian et al., Testing Embedded-Core Based
System Chips, PROC. PROC. IEEE INT’L TEST CONF. 130–143 (1998)).
5. Claims 4–6 stand rejected under 35 U.S.C. § 103(a) as obvious
over Aerts, Zorian, and admitted prior art (APA).
6. Claims 1–3, 10, and 13–16 stand rejected under 35 U.S.C.
§ 103(a) as obvious over Mathewson (Bruce Mathewson, IEEE P1500 Core
Provider’s Test Experience 1–14) and Zorian.
7. Claims 4–9, 11, and 12 stand rejected under 35 U.S.C. § 103(a)
as obvious over Mathewson, Zorian, and APA.
8. Claims 1–3, 7, 8, 10, 15, and 16 stand rejected under
35 U.S.C. § 103(a) as obvious over Ishikawa (US 6,711,042 B2; Mar. 23,
2004) and Aerts.
9. Claims 4–6, 11, and 12 stand rejected under 35 U.S.C. § 103(a)
as obvious over Ishikawa, Aerts, and APA.
10. Claims 17 and 18 stand rejected under 35 U.S.C. § 103(a) as
obvious over SCTS and APA.
11. Claims 17 and 18 stand rejected under 35 U.S.C. § 103(a) as
obvious over Rajski and APA.
12. Claim 17 stands rejected under 35 U.S.C. § 103(a) as obvious
over Dervisoglu and APA.
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13. Claims 19–25, 27–29, and 31 stand rejected under 35 U.S.C.
§ 103(a) as obvious over Mathewson and Zorian.
14. Claims 19–25, 27–29, 31, and 33 stand rejected under
35 U.S.C. § 103(a) as obvious over Mathewson, Zorian, and APA.
15. Claims 26, 30, 32, and 34 stand rejected under 35 U.S.C.
§ 103(a) as obvious over Mathewson, Zorian, and Aerts.
16. Claims 26, 30, 32, and 34 stand rejected under 35 U.S.C.
§ 103(a) as obvious over Mathewson, Zorian, APA, and Aerts.
Patent Owner relied upon the following declarations in rebuttal to the
Examiner’s rejections:
Declaration under 37 C.F.R. § 1.132 of Ajay Khoche, Ph.D., dated
October 31, 2011.
Second Declaration under 37 C.F.R. § 1.132 of Ajay Khoche, Ph.D.,
dated July 25, 2012.
Declaration under 37 C.F.R. § 1.132 of Yervant Zorian, Ph.D., dated
July 25, 2012.
Requester relied upon the following declarations in support of the
Examiner’s rejections:
Declaration under 37 C.F.R. § 1.132 of M. Ray Mercer, Ph.D., dated
November 29, 2011 (“Mercer Declaration”).
Second Declaration under 37 C.F.R. § 1.132 of M. Ray Mercer, Ph.D.,
dated August 22, 2012.1

1 This opinion only addresses arguments made by Patent Owner and
Requester. Arguments not made are considered waived. See 37 C.F.R.
§ 41.37(c)(1)(iv). We have considered the declaration evidence to the extent
raised by Patent Owner’s and Requester’s arguments.
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ANALYSIS
Claim Interpretation
“multi-chip module”
The Examiner found that “the ’683 patent defines the claim term
multi-chip module as ‘a single package having multiple integrated circuits’”
and “there is no requirement in the ’683 patent that each of the cores must be
embodied in a separate die to be considered an integrated circuit” because
“[t]he ’683 patent describes . . . : “Each integrated circuit 120 is embodied
in a die; however, each integrated circuit 120 may also be [embodied] in
other forms.’” (RAN 65 (citations omitted).) We do not agree with the
Examiner’s interpretation of “multi-chip module.”
Independent claim 17 recites “[a] multi-chip module comprising . . .
the first integrated circuit and the second integrated circuit being in the same
multi-chip module” (emphases added). The ’683 patent states that “[a]
single package having multiple integrated circuits is also referred to as a
multi-chip module.” (Col. 1, ll. 20–21 (emphases added).) In reference to
Figure 1, the ’683 patent also discloses that “DUT 110 is a multi-chip
module having two or more integrated circuits 120 (i.e., 120A, 120B, . . . ,
120n) in a single package.” (Col. 2, ll. 40–42.) In the context of
microelectronics, one relevant definition of “multichip integrated circuit,” a
term similar to “multi-chip module,” is defined as “[a]n integrated circuit
whose elements are formed on or within two or more semiconductor chips
that are separately attached to a substrate.” IEEE STANDARD DICTIONARY OF
ELECTRICAL AND ELECTRONICS TERMS 601 (4th ed. 1988). Moreover, the
term “multi-chip” is shorthand for multiple chips or multiple integrated
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circuits. Thus, based on the ’683 patent, the common knowledge of a
similar term, and the plain meaning of “multi-chip,” we interpret “multi-chip
module” as a single package having multiple integrated circuits separately
attached to a substrate. Accordingly, we are persuaded by Patent Owner’s
argument that “[t]he specification of the ‘683 Patent unambiguously defines
a multi-chip module as a ‘single package having multiple integrated
circuits.’” (PO App. Br. 13; see also PO Reb. Br. 7.)
Requester argues “there is no requirement in the ’683 patent that each
of the cores must be embodied in a separate die to be considered an
integrated circuit” (Requester Resp. Br. 3) because of the disclosure from the
’683 patent that “[e]ach integrated circuit 120 is embodied in a die; however,
each integrated circuit 120 may also be embodied in other forms” (id. at 3–4
(quoting col. 2, ll. 42–44)). However, as discussed previously, Requester’s
proposed interpretation of “multi-chip module” is inconsistent with the
definition provided in the ’683 patent, the common knowledge of a similar
term (i.e., “multichip integrated circuit”), and the plain meaning of “multi-
chip.”
Requester further argues that “each of the cores is a circuit and is
integrated in a semiconductor chip” and points to paragraphs 15–16 of the
Mercer Declaration for support. (Id. at 4.) A relevant portion from
paragraph 15 of the Mercer Declaration is reproduced below:
The IEEE Standard Dictionary of Electrical and Electronics
Terms provides the following definitions for two highly
relevant terms:
multichip integrated circuit. An integrated circuit
whose elements are formed on or within two or more
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semiconductor chips that are separately attached to a
substrate . . . .
integrated circuit (solid state). A combination of
interconnected circuit elements inseparably associated on
or within a continuous substrate . . . .
A relevant portion from paragraph 16 of the Mercer Declaration is
reproduced below:
From the above definition of integrated circuit, one of
ordinary skill in the art would have understood that one
integrated circuit must be a combination of circuit elements that
exist on a single substrate. However, one of ordinary skill in
the art would have also understood that this definition does not
preclude the existence of multiple integrated circuits on the
same substrate.
However, Requester’s argument that one of ordinary skill in the art would
interpret “integrated circuit” to include “multiple integrated circuits on the
same substrate” is overly broad, because such “multiple integrated circuits
on the same substrate” describes a “system on chip” (or “SOC”).2 In other
words, one of ordinary skill having knowledge of the term “system on chip”
would refer to a component with multiple integrated circuits on the same
substrate as a “system on chip,” rather than an “integrated circuit.”
Thus, we do not agree with the Examiner’s interpretation of “multi-
chip module” as broad enough to encompass multiple cores on a single die.

2 A “system on chip” (or “SOC”) is defined as “[a] chip integrating
computer, microprocessors, and all necessary support components in a single
unit.” MICROSOFT® COMPUTER DICTIONARY 288 (5th ed. 2002).

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§ 102 Rejection—SCTS
The Examiner found that the system-chip of SCTS, as illustrated in
Figure 2, corresponds to the claimed “multi-chip module.” (RAN 10–11.)
The Examiner further found that the cores of SCTS (e.g., Digital Signal
Processor core or RISC core) correspond to the limitations “first integrated
circuit” and “second integrated circuit.” (Id. at. 11.) Requester agrees and
further argues that “SCTS shows integrated circuits or cores, such as DSP
core, MPEG core, etc. in Fig. 1 which satisfy the first means element of
claim 17” (Requester Resp. Br. 6–7) and “SCTS provides peripheral access
blocks, which are equivalent to the slave test circuit 231” of the ’683 patent
(id. at 7). We do not agree with the Examiner’s determination.
SCTS states that “this paper focuses on the current industrial practices
in test strategies for system-chips” and includes “System-on-Chip Test” as a
keyword. (Abstract.) Figure 1 of SCTS illustrates a system-chip having
hierarchical cores. (P. 752.) However, the system-chips or system-on-chip
described in SCTS refers to a single integrated circuit, which is
distinguishable over the claimed “multi-chip module,” which requires
multiple integrated circuits separately attached to a substrate. Thus, we are
persuaded by Patent Owner’s argument that “SCTS does not disclose a
multi-chip module having a first and a second integrated circuit, but instead
discloses testing methodologies for individual cores.” (PO App. Br. 15.)
Accordingly, we reverse the Examiner’s decision to reject claims 17
and 18 under 35 U.S.C. § 102(b) as anticipated by SCTS.

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§ 102 Rejection—Rajski
The Examiner found that the Application Specific Integrated Circuit
(ASIC) of Rajski having “Core A” and “Core B,” as illustrated in Figure 1,
corresponds to the claim “multi-chip module.” (RAN 13.) The Examiner
further found that the two build-in self-test (BIST) ready cores of Rajski
correspond to the claimed “first integrated circuit” and “second integrated
circuit.” (Id. at 13–14.) Requester agrees and further argues that “Rajski
shows integrated circuits or cores, including logic portions, in Fig. 1, which
satisfy the first means element of claim 17” (Requester Resp. Br. 8) and that
“Rajski provides an interface for each core, which are equivalent to the slave
test circuit 231 of the ’683 patent” (id. at 9). We do not agree with the
Examiner’s determination.
Rajski relates to modular logic BIST architecture for intellectual
property (IP) contained on an ASIC system. (Abstract; see also p. 314,
col. 2.) Rajski refers a system-on-silicon having built-in self-test ability
(p. 313, col. 1), particularly for testing of IP cores (p. 314, col. 2). However,
the system-on-silicon or “system-on-chip” described in Rajski refers to a
single integrated circuit, which is distinguishable over the claimed “multi-
chip module,” which requires multiple integrated circuits separately attached
to a substrate. Thus, we are persuaded by Patent Owner’s arguments that
“Rajski does not disclose a multi-chip module but instead discloses a Built-
In-Self-Test (‘BIST’) solution for ‘systems on silicon’ with IP cores
(‘systems designers build system ASICs using these cores’).” (PO App.
Br. 26.)
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Accordingly, we reverse the Examiner’s decision to reject claims 17
and 18 under 35 U.S.C. § 102(b) as anticipated by Rajski.

§ 102 Rejection—Dervisoglu
The Examiner found that integrated circuit (IC) 100 of Dervisoglu,
which includes Service Processor Unit (SPU) 101, test wrappers 102, and
blocks 106, corresponds to the claimed “multi-chip module.” (RAN 15.)
The Examiner further found that SPU 101 corresponds to the claimed “first
integrated circuit” (id.) and that the blocks 106 correspond to the claimed
“second integrated circuit” (id. at 16). Requester agrees and further argues
that “Dervisoglu shows a service processor unit (SPU) 101, which is a
processor and satisfies the first means element of claim 17” and “Dervisoglu
provides a test wrapper 102 for each core, which are equivalent to the slave
test circuit 231 of the ’683 patent specification.” (Requester Resp. Br. 10.)
We do not agree with the Examiner’s determination.
Dervisoglu relates to debugging of electronic systems, “in particular,
to on-chip circuits for the test and diagnosis of problems in an integrated
circuit.” (Col. 1, ll. 9–12.) Figure 1 of Dervisoglu illustrates “a high-level
diagram of an exemplary large and complex integrated circuit” (col. 3,
ll. 38–39), including IC 100, SPU 101, test wrappers 102, and blocks 106
(col. 6, ll. 11–16). However, IC 100 of Dervisoglu is a single integrated
circuit, which is distinguishable over the claimed “multi-chip module,”
which requires multiple integrated circuits separately attached to a substrate.
Thus, we are persuaded by Patent Owner’s arguments that “a multi-chip
module of the type disclosed in the ’683 patent, contains individual
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integrated circuits with passive components therebetween” (PO App. Br. 28)
and “Dervisoglu does not disclose or suggest a multi-chip module where the
multi-chip module includes multiple integrated circuits in a single package”
(id. at 28–29).
Accordingly, we reverse the Examiner’s decision to reject claim 17
under 35 U.S.C. § 102(b) as anticipated by Dervisoglu.

§ 103 Rejection—Mathewson and Zorian
The Examiner found that the Test Interface Controller (TIC) and the
External Bus Interface (EBI), as illustrated in a figure of Mathewson (page
10), corresponds to the claimed “first integrated circuit.” (RAN 26.) The
Examiner further found that the ARM processor and the Peripheral, as
illustrated in the figure of Mathewson, correspond to the claimed “second
integrated circuit.” (Id.) Requester agrees and further argues “[w]hen the
claim terms are construed under a broadest reasonable interpretation,
Mathewson teaches testing of first and second integrated circuits in a single
package.” (Requester Resp. Br. 14.) We do not agree with the Examiner’s
determination.
Mathewson is 14-page a slide presentation (see generally pp. 1–14)
relating to the testing of a central processing unit (CPU) core manufactured
by ARM, Limited (see p. 6.) The “Test Interface Controller” figure of
Mathewson illustrates a diagram that features the following: (i) “TIC” and
“External Bus Interface”; (ii) “ARM” processor”; and (iii) “Peripheral”
reside within a single rectangular block. (P. 10.) Mathewson provides no
further description of such figure.
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Although the Examiner cited to the figure on page 10 of Mathewson,
the Examiner has provided insufficient evidence to support a finding that the
“TIC” and “External Bus Interface” of Mathewson is an “integrated circuit”
as recited in claims 1 and 10, particularly when Mathewson does not provide
a sufficiently detailed explanation of such figure. Accordingly, we are
persuaded by Patent Owner’s argument that “[t]he supposition that an
external bus interface and a test interface controller (TIC) are themselves
separate integrated circuits finds absolutely no support in Mathewson.” (PO
App. Br. 38; see also PO Reb. Br. 17.)
Accordingly, we reverse the Examiner’s decision to reject claims 1–3,
10, 13–16, 19–25, 27–29, and 31 under 35 U.S.C. § 103(a) as obvious over
Mathewson and Zorian.

§ 103 Rejection—Mathewson, Zorian, and APA
Claims 4–9, 11, 12, 19–25, 27–29, 31, and 33 depend from claims 1
and 10. APA was cited by the Examiner for teaching the additional features
of claims 4–9, 11, 12, 19–25, 27–29, 31, and 33. (RAN 40–45.) However,
the Examiner’s application of APA does not cure the above noted
deficiencies of Mathewson and Zorian.
Accordingly, we reverse the Examiner’s decision to reject claims 4–9,
11, 12, 19–25, 27–29, 31, and 33 under 35 U.S.C. § 103(a) as obvious over
Mathewson, Zorian, and APA.

§ 103 Rejection—Ishikawa and Aerts
The Examiner acknowledged that Ishikawa does not disclose the
limitation “to receive the plurality of test signals in parallel,” as recited in
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independent claim 1 and, therefore, relied on Aerts for teaching the parallel
testing of three integrated circuit cores (e.g., A, B, and C). (RAN 51.) The
Examiner concluded that “it would have been obvious to modify the system
disclosed by Ishikawa for receiving test signals in parallel as disclosed by
Aerts to increase bandwidth and decreases test time.” (Id. at 52.) Requester
agrees and further argues that “[t]he rejections using Ishikawa and Aerts
proposes only to modify Ishikawa to receive test signals in parallel, and the
proposed modification has a rational underpinning and is not a redesign of
the Ishikawa system” (Requester Resp. Br. 15) and “the applied combination
does not propose to add scan chains to the memory device of Ishikawa” (id.
at 16). We agree with the Examiner’s determination.
Ishikawa relates a multi-chip module (MCM) semiconductor device
such that “it is possible to test the memory chip after accommodation in the
package.” (Col. 1, ll. 10–14.) Figure 2 of Ishikawa illustrates a
configuration device for a semiconductor device (col. 4, ll. 16–17), including
logic chip 2, memory chip 3, and memory chip testing circuit 4 (col. 4,
ll. 20–22), such that memory chip 2 is accessible from memory chip testing
circuit 4 (col. 4, ll. 26–27). Ishikawa explains that “during memory chip
testing, memory testing access signals from the memory chip testing circuit
[4] provided inside the logic chip [2] are sent to the memory chip [3] via the
selector-output circuit, and access operations from the logic chip to the
memory chip are tested.” (Col. 2, ll. 37–41.) Ishikawa further explains that
“[d]uring memory chip testing . . . the selector input/output circuit 2C
selectively outputs a control signal CNT, address signal Add, and write data
DATA from the memory chip testing circuit 4, and sends read data DATA
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from the memory chip 3 to the memory chip testing circuit 4.” (Col. 4,
ll. 42–45.)
As discussed previously, Aerts relates to “design of scan chains as
transport mechanism for test patterns from IC pins to embedded cores.”
(Abstract.) Figure 3 of Aerts illustrates a distribution architecture for testing
cores A, B, and C in parallel (p. 451, col. 2), such that “to use the available
bandwidth to transport the test data as efficient as possible” (p. 451, col. 2)
and “the total test time is determined by the maximum test time of the
individual cores” (p. 457, col. 1.)
A person of ordinary skill in the art would have recognized that
incorporating the parallel scans of Aerts with the MCM semiconductor
device of Ishikawa would have improved Ishikawa by providing the ability
to test the memory chip of Ishikawa by more efficiently maximizing
bandwidth or minimizing scan time. See KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 417 (2007) (“[I]f a technique has been used to improve one device,
and a person of ordinary skill in the art would recognize that it would
improve similar devices in the same way, using the technique is obvious
unless its actual application is beyond his or her skill.”). Thus, we agree
with the Examiner (RAN 52) that modifying Ishikawa to receive test signals
in parallel, as taught by Aerts, would have been obvious.
Patent Owner argues
One of ordinary skill in the art would not look to Aerts, which
is a system-on-chip device that receives a test pattern from an
outside source for distribution to a series of embedded cores
within a single integrated circuit, for testing methodologies to
be applied to a device such as the one described in Ishikawa,
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which is a memory testing semiconductor device that is not
designed to receive test patterns
and points to paragraph 40 of the First Khoche Declaration for support. (PO
App. Br. 40.) Similarly, Patent Owner argues that “[t]he semiconductor
device described in Ishikawa is not designed to receive a test pattern in
parallel from an outside source,” pointing to paragraph 41 of the First
Khoche Declaration for support (PO App. Br. 40) and argues that “[m]emory
testing devices do not use scan chains” pointing to paragraph 40 of the First
Khoche Declaration for support (id. at 41). Moreover, Patent Owner argues
that
It is common knowledge in the industry that memory testing
circuits for at-speed testing (testing at normal operating speed)
use on-chip circuits as also described by Ishikawa to meet the
test performance requirements and do not use scan chains for
such testing as scan chains by their serial nature cannot provide
the means for continuous at-speed operation
and points to paragraph 26 of the Second Khoche Declaration for support.
(PO App. Br. 41.) However, the Examiner cited to Aerts for the general
teaching that parallel scans are well-known, rather than applying the test
pattern or scan chains of Aerts from an outside source to memory chip 2 of
Ishikawa. (RAN 51.) Accordingly, Patent Owner’s arguments do not
directly address the Examiner’s articulated reasoning for combining
Ishikawa and Aerts. Furthermore, the statements in the Second Khoche
Declaration relied upon by Patent Owner lack persuasive factual support
because the Second Khoche Declaration does not cite to sufficient
corroborating evidence. See In re Beattie, 974 F.2d 1309, 1313 (Fed. Cir.
1992) (“[D]eclarations themselves offer only opinion evidence which has
little value without factual support.”).
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Accordingly, we affirm the Examiner’s decision to reject claims 1–3,
7, 8, 10, 15, and 16 under 35 U.S.C. § 103(a) as obvious over Ishikawa and
Aerts.

§ 103 Rejection—Ishikawa, Aerts, and APA
Although Patent Owner nominally argues the rejection of dependent
claims 4–6, 11, and 12 separately (PO App. Br. 41–42), the arguments
presented do not point out with particularity or explain why the limitations
of these dependent claims are separately patentable. Instead, Patent Owner
summarily allege that “[c]laims 4–6, and 11–12 are allowable at least by
virtue of their dependence upon claim 1 or claim 10 and further in view of
their own respective features” and “APA does not supply the features
missing from Ishikawa or Aerts.” (Id. at 41.) We are not persuaded by these
arguments for the reasons discussed with respect to claims 1 and 10, from
which claims 4–6, 11, and 12 depend. Accordingly, we sustain this
rejection.

§ 103 Rejection—Mathewson, Zorian, and Aerts
Claims 26, 30, 32, and 34 depend from claim 1. Aerts was cited by
the Examiner for teaching the additional features of claims 26, 30, 32, and
34. (RAN 46–48.) However, the Examiner’s application of Aerts does not
cure the above noted deficiencies of Mathewson and Zorian.
Accordingly, we reverse the Examiner’s decision to reject claims 26,
30, 32, and 34 under 35 U.S.C. § 103(a) as obvious over Mathewson,
Zorian, and Aerts.
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§ 103 Rejection—Mathewson, Zorian, APA, and Aerts
Claims 26, 30, 32, and 34 depend from claim 1. Aerts was cited by
the Examiner for teaching the additional features of claims 26, 30, 32, and
34. (RAN 48–49.) However, the Examiner’s application of Aerts does not
cure the above noted deficiencies of Mathewson, Zorian, and APA.
Accordingly, we reverse the Examiner’s decision to reject claims 26,
30, 32, and 34 under 35 U.S.C. § 103(a) as obvious over Mathewson,
Zorian, APA, and Aerts.

§ 103 Rejection—Aerts and Zorian
We do not reach the rejection of claims 1–3 and 10 under 35 U.S.C.
§ 103(a) as obvious over Aerts and Zorian. Affirmance of the rejections
discussed previously renders it unnecessary to reach the remaining
rejections, as all of pending claims have been addressed and found
unpatentable. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not
reaching additional obviousness rejections).

§ 103 Rejection—Aerts, Zorian, and APA
We do not reach the rejection of claims 4–6 under 35 U.S.C. § 103(a)
as obvious over Aerts, Zorian, and APA. Affirmance of the rejections
discussed previously renders it unnecessary to reach the remaining
rejections, as all of pending claims have been addressed and found
unpatentable. Cf. Gleave, 560 F.3d at 1338.
.
Appeal 2015-004678
Reexamination Control 95/001,665
Patent 6,825,683 B1

19
DECISION
The Examiner’s decision to reject claims 1–8, 10–12, 15, and 16
under 35 U.S.C. § 103(a) is affirmed.
The Examiner’s decision to reject claims 9, 13, 14, and 17–34 under
35 U.S.C. § 103(a) is reversed.
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

AFFIRMED-IN-PART

cdc

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