Ex Parte 6751696 et al

Patent Trial and Appeal Board

Dec 7, 2012

95001133 (P.T.A.B. Dec. 7, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,133 12/31/2008 6751696 8963.002.285 1711
22852 7590 12/07/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
12/07/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,105 11/06/2008 6751696 38512.12 4093
22852 7590 12/07/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
12/07/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

MICRON TECHNOLOGY, INC.
Requester, Appellant

v.

RAMBUS INC.
Patent Owner, Respondent
____________

Appeal 2012-002081
Inter Partes Reexamination Control No. 95/001,105 & 95/001,133
United States Patent 6,751,696 B2
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2012-002081
Reexamination Control Nos. 95/001,105 & 95/001,133
Patent 6,751,696 B2

2

This merged proceeding arose out of separate requests by Micron
(95/001,133) and Samsung Electronics Ltd. (95/001,105) for inter partes
reexaminations of U.S. patent 6,751,796 B2 to Farmwald et al., Memory
Device Having A Programmable Register (issued June 15, 2004, and
claiming priority to April 18, 1990 based on a series of continuation
applications starting with application number 07/510,898) assigned to
Rambus.
Samsung has not filed a Brief in this proceeding. Appellant,
Requester Micron, appeals from the Examiner’s decision in the Right of
Appeal Notice (RAN) confirming claims 1 and 4. The Examiner’s Answer
relies on the RAN, incorporating it by reference.
We have jurisdiction under 35 U.S.C. §§ 134(b) and 315.
We REVERSE the Examiner’s decision to confirm claims 1 and 4
based on certain rejections and AFFIRM the Examiner’s decision not to
reject the claims based on other rejections.

STATEMENT OF THE CASE
Rambus and Micron refer to several related judicial and other
proceedings including inter partes and ex parte reexaminations,
International Trade Commission proceedings, and Federal District Court and
Circuit Court proceedings in their briefs, inter partes requests, and various
notices. An oral hearing of this appeal and a related appeal (BTAP 2012-
001976) occurred on September 12, 2012 before the (formerly-named)
Board of Patent Appeals and Interferences and was subsequently transcribed
and made of record. That concurrent decision is hereby incorporated and
adopted by reference.
Appeal 2012-002081
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Patent 6,751,696 B2

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Appellant, Requester Micron, appeals the Examiner’s refusal to
maintain the rejections of claims 1 and 4 as obvious based on Bennett,
1
and
either Inagaki,
2
Deering,
3
or Novak.
4
Requester also appeals the refusal to
maintain the rejections of claims 1 and 4 as anticipated by JEDEC
5
or as
obvious based on JEDEC and Park.
6
The JEDEC and Park rejections turn
on priority.
The appealed claims follow:
1. A synchronous memory device including an array of memory cells,
the synchronous memory device comprises:
clock receiver circuitry to receive an external clock signal;
input receiver circuitry to sample a first operation code in response to
a rising edge transition of the external clock signal;
a programmable register to store a value which is representative of an
amount of time to transpire before the memory device outputs data, wherein
the memory device stores the value in the programmable register in response
to the first operation code; and
output driver circuitry to output data in response to a second operation
code, wherein the data is output after the amount of time transpires, and
wherein:

1
Bennett et al., U.S. 4,734,909 (Mar. 29, 1988).
2
Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an
English language translation of record).
3
Deering, The Triangle Processor and Normal Vector Shader (1988).
4
Novak et al., U.S. 4,663,735 (May 5, 1987).
5
Joint Electronic Device Engineering Counsel (JEDEC) Standard No. 21-C,
Rev. 9 (1999).
6
Park et al., US 5,590,086 (Dec. 31, 1996, effective filing Oct. 1993).
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the output driver circuitry outputs a first portion of the data
synchronously with respect to a rising edge transition of the external clock
signal and outputs a second portion of the data synchronously with respect to
a falling edge transition of the external clock signal.
4. The memory device of claim 1 wherein the memory device is a
synchronous dynamic random access memory.
ANALYSIS
Standing
Rambus contends that Micron lacks standing to appeal rejections
originally proposed only by Requester Samsung, and not by Requester
Micron, in this merged proceeding. (Resp. Br. 1-2.) Rambus refers to the
anticipation rejection based on the JEDEC Standard, and the obviousness
rejections based on 1) Bennett and Inagaki, and 2) Park and the JEDEC
Standard. (Id.)
Micron points out correctly that Rambus’s standing argument was
addressed and dismissed previously in several prior BPAI petition decisions
in related reexamination proceedings involving Rambus. (Reb. Br. 1.)
Fundamentally, 35 U.S.C. § 315(b) allows for appeals in reexaminations
from any final decision favorable to patentability. Secondly, the Board has
authority to consider appeals from decisions by the Examiner. See 37 C.F.R.
41.77 (a) (“The Board ... may affirm or reverse each decision of the
examiner on all issues raised on each appealed claim ....”). Finally, the
Board has discretion to enter new grounds of rejection regardless of the
initial source for the new grounds. See 37 C.F.R. § 41.77(b).
Rambus fails to provide a legislative history analysis showing that
35 U.S.C. § 315(b) means something other than what it plainly states and
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precludes a “third party requestor [from] . . . appeal[ing] . . . , with respect
to any final decision favorable to the patentability of any original or
proposed amended or new claim.” Based on the foregoing discussion,
Rambus’s standing argument is not persuasive.

Bennett with Inagaki, Deering, or Novak
According to Micron, the Examiner confirmed claim 1 because
Bennett does not teach a representative delay value; i.e., the “value which is
representative of an amount of time to transpire before the memory device
outputs data;” and also, because the combined teachings do not render
obvious outputting data on both the rising and falling clock edges; i.e.,
“output[ting] data synchronously with respect to a rising edge transition of
the external clock signal and output[ting] a second portion of the data
synchronously with respect to a falling edge transition of the external clock
signal.” (See App. Br. 7.) Rambus argues that the Examiner correctly
confirmed the claims based on the rationale above and for other reasons.
For example, Rambus argues that claim 1 requires a single chip memory
device and Bennett fails to disclose or render obvious such a device.
These issues or similar issues have been decided in previous Board
decisions. Based on our prior decisions and this record, including the
respective positions of the parties and the Examiner, Micron persuasively
shows that the Examiner erred in confirming the claims as discussed below.

Appeal 2012-002081
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Patent 6,751,696 B2

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Bennett’s Teachings
B1. Bennett’s “paramount object” is to provide communication
between “very large scale integrated VLSI (circuit) elements” (col. 12,
ll. 14-18) – i.e., “VLSIC chips” (col. 9, ll. 35-40). Bennett discloses
combining Versatile Bus Interfaces (VBI) and VLSIC “upon the same chip
substrate as the VLSI User Device” (col. 12, ll. 29-32 (emphasis added))
with such a user device including “interfaces intended to be built with a
CPU, IOC or Memory, or similar User device for signal or data exchange”
(col. 35, ll. 59-61 (emphasis added)). (See also col. 14, ll. 19-24 (describing
“interface to the user devices (usually upon the same chip substrate)”.)
As another example demonstrating a preference for a single chip,
Bennett states that “[e]ach Versatile Bus Interface Logics, for example
Versatile Bus Interface Logics 102a [of Fig. 1], interfaces a User module, for
example VLSI Circuit User Device 106a which is pictorially represented in
shadow line within FIG. 1 as existing on the same VLSIC chip substrate as
Versatile Bus Interface Logics 102a.” (Col. 36, ll. 19-24 (emphasis added).)
Bennett’s chips have up to 120 pins as a practical limit. (Col. 9,
ll. 60-61.) Bennett also discloses different memory types as “Fast Memory”
or “Large Memory” with the memory having address widths of 16, 24, or
32, and one fast memory embodiment having 37 pins (col. 92, ll. 15-56;
Fig. 32). One large memory has at least 16 pins to access 2
32
addresses by
employing two 16-bit address words over successive clock cycles. (See col.
95, ll. 59-60; Fig. 36.)
B2. Figure 38 shows “memories device” 3802c and 3802d connected
to a “Versatile Bus.” (Col. 97, ll. 8-10.) In the next paragraph, Bennett
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refers to “VSLI chips hav[ing] access to all Versatile Bus lines and
therefore, the Versatile Bus protocols.” (Id. at ll. 20-22.)
Bennett elsewhere refers to “memory devices” including, but not
limited to, a ROM: “Not all memory devices can perform all operations; for
example, read only memory (ROM) cannot execute the write operations.”
(Col. 90, l. 66 to col. 91, l. 2.) Bennett then refers to “[s]ample memory
operations in the following paragraphs” (col. 91, ll. 4-5) and thereafter
describes “relatively small fast memories, and . . . larger and relatively
slower memories” (col. 92, ll. 13-14).
Bennett also refers to defining “VLSIC chip devices” (col. 90, ll. 38-
41) and in the next section, Section “4.1, Sample Memory Operations,”
states that “[m]any, if not most, applications of VLSIC technology are likely
to include memory devices.” (Col. 90, ll. 42-43.) Bennett generally
discusses these chip devices as employing the interconnection protocol
standards outlined generally in Section 3 and more specifically discusses
memory devices in Section 4, including embodiments or configurations
involved in Figures 31-36. (See id. at ll. 36-41.)
For example, as discussed in Section 4 of Bennett, Figures 32 and 33
represent fast memory write operations using data on 16 pins and 16 other
pins for arbitration and slave ID. (See col. 93, l.12 - col. 94, l. 56.)
Figure 36 represents pin and timing for a write operation to a large memory
device with a 4315335 protocol “configuration.” (See col. 26, ll. 54-57.)
Figures 25a-h, represent more generic slave device configurations as
discussed in Section 3 of Bennett. (Col. 25, l. 58 to col. 26, l; see generally
columns 81-88).
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B3. In addition to chips, Bennett also discusses memory cards in
Section 2, “Description of the Prior Art” (see col. 5, l.52 et seq.), and states
that “the functionality of VLSIC chips is often similar to cards today” but
that “VLSIC technology promises much higher performance than that of
cards,” even though cards hold more memory and chips have higher
development costs. (Col. 9, ll. 43-56.) In the next passage, Bennett
discusses creating larger chips to accommodate a greater numbers of pins.
(Col. 9, l. 66 to col. 10, l. 29.)
B4. Bennett describes a “third physical objective” – the VBI
(versatile bus interface) “should occupy a reasonable VLSI circuit substrate
area” using fast and efficient CMOS technology as the preferred
embodiment. (Col. 13, ll.18-23.) Typically, only about 20 VLSIC devices
will be interconnected. As a “first logical object,” the VBI logics “should
offer a fixed format, simply controlled, powerfully featured interface to the
user devices (usually upon the same chip substrate)” yet with certain options
for use. (Col. 14, ll. 20-30.)
Bennett contemplates simple devices with “as few as three pins”
(Bennett, col. 12, l. 61), or “pass[ing] but a single bit of data from a single
master device to a single slave device . . . [or more bits and devices]. The
versatility is from the trivial to the profound.” (Col. 15, ll. 26, 42-50.)
Figure 32, a “sample fast memory,” has “an address field arbitrarily sized at
four bits.” (Col. 93, ll. 13, 23.) Large memories are slower than, and have
more address pins, than fast memories. (Co. 94, ll. 26-33.) Bennett
mentions that for large memories, “[a]ddress width may be configured to 16,
24, or 32 bits to match requirements.” (Col. 94, ll. 35-36.) In another
section, Bennett describes a fast memory which may have 16 bit words, and
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if so, “at a 40 nanosecond pace may either have to be very wide or very fast
or both.” (Col. 89, ll. 30-32.) The inventors “anticipate serving User
devices which are quite compatible with high speed streamed data of a priori
indeterminate length.” (Col. 89, ll. 33-35.)
B5. Figures 25a-h, described in section 3 of Bennett, depict timing
diagrams for slave devices on the VLSIC bus which have eight
Configuration Parameters (e.g., 122123XX) for the devices. (See col. 86,
ll. 31-32.) Bennett refers to the Section 3 figures as representing chips:
“Section 3 provided for the electrical connection of many chips on one bus .
. . . Each chip recognizes the existence of the transactions . . . .” (Col. 90, ll.
27-30.)
Also, for these figures, and for preferred embodiments, Bennett
discloses only two choices (i.e., either digit 1 or 3) for the Configuration
Parameter VI which specifies the number of wait lines between chips
transferring data. (See col. 86, ll. 31-41; 55-58; col. 83, ll. 30-40; col. 76,
ll. 1-2 (preferred embodiments have zero or one wait line); col. 86, l. 31 –
col. 87, l.8 (only specifying configuration digits of either 1 or 3 for the
Configuration Parameter VI in Figures 25a-h); col. 86, ll. 55-67 (explaining
that wait nullity 2 “should not be used”); compare Figure 3 (generally
allowing for values 1, 2, 3, 4, or 5 for Configuration Parameter VI ). The
value 1 signifies that the wait function is pin multiplexed (Mpx) on data
lines while the value 3 signifies one designated wait line. (See Fig. 3; col.
86, ll. 31-48.)
These Configuration Parameter VI values of 1 and 3, indirectly dictate
a relative number of clock cycles which transpire after a function signal:
“Data transfers begin after Wait if multiplexed, or simultaneously with Wait
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if pipelined . . . .” (Col. 77, ll. 40-41.) (The “pipeline” refers to transferring
the wait signal to its own designated pin so that waiting, otherwise required
with multiplexing over the same lines, is not required.)
Thus, relative to the write command (i.e., the ID/FUNCTION of
Figs. 25a-h), the Configuration Parameter VI value of 1 corresponds to an
extra clock cycle, based on multiplexing, in comparison to the total clock
cycle number corresponding to the value 3. This extra clock cycle which
occurs every time Configuration Parameter VI is 1 in Figures 25a-h
(i.e., Figure 25a, c, e, and g), amounts to four total clock cycles –the DATA
transfers two clock cycles after a function command such as write (i.e., the
ID/FUNCTION command). On the other hand, every time the
Configuration Parameter VI is 3 in Figures 25a-h (i.e., Figures 25b, d, f,
and h), the delay amounts to three total clock cycles, or the DATA transfers
one clock cycle after the write command (i.e., ID/FUNCTION command).
(Compare Figure 25a, c, e, and g with Figures 25b, d, f, and h).
As indicated, Figures 25a-h, similar to Figures 35 and 36, show an
ID/FUNCTION command, which includes a read or a write (see e.g. Fig. 35,
36).
7
(See col. 85, l. 9 to col. 87, l. 6.). Figure 34 shows multiple functions
in a memory write code: i.e., a read-modify-write code signifying multiple
functions in a single code.

7
Bennett also refers to functions as operations, which include read or write
operations. (See col. 91, l. 62 to col. 92, l. 8; col. 91, ll. 43-53 (“functional
operations”); Figs. 31, 35, 36.) Address data and operation codes may be
sent as part of the “Slave Identification/Function information” cycle, “but
this need not be so. The sample memory may receive this ‘function’
information as data.” (Col. 90, ll. 54-58.)
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B6. Bennett discloses synchronous clocked communication between
bused VLSIC chips over 16 data lines at 25MHz, and notes that synchronous
communication is more efficient than asynchronous communication.
(Col. 13, ll. 3-17; col. 66, l. 9 – col 67, l. 18; col. 101, ll. 50-54 (“all
communication . . . is synchronously referenced”); col. 102, ll. 9-27.)
Bennett also states that the clock signals “are normally synchronous.”
(Col. 274, l. 62.)
B7. Bennett employs a dual-phase clocking scheme. (See Fig. 84.)
Bennett explains that the scheme employs a first phase to charge the
capacitance on the bus. (Abstract.) To further explain the system, Bennett
(col. 13, ll. 33-43; col. 105, ll. 50-61) points to, and incorporates by
reference, App. No. 0355,803, which corresponds to Bennett at al.,
U.S. 4,500,988 (Feb. 19, 1985.) Bennett ‘988, in reciprocal fashion,
mentions using its clocking scheme and corresponding driver circuitry in
Bennett. (See, e.g., Bennett ‘988, col. 7, ll. 47-51 (referring to Bennett’s
application number 356,051).)
B8. Bennett ‘988 (col. 7, ll. 62-67) and Bennett (col. 277, ll. 30-33)
each similarly explain that the dual-phases can have a 50% duty cycle and
can be symmetrical. Bennett ‘988 explains that the dual phase scheme
allows smaller interfacing transistors in separate devices to work together in
a wired-OR fashion to pre-charge the bus. (Bennett ‘988, col. 6, ll. 47-51;
col. 7, ll. 7-34; col. 8, ll. 57-63.) The bus is precharged to a high voltage
level of 3 volts (corresponding to a logical 0) at the leading edge of phase
(H) φ1, and then, if, and only if, any one of the data lines seek to represent a
logical 1 data bit, that line/lines is/or driven to a low voltage at the leading
edge of phase (H) φ2. (See Bennett’ 988, Fig. 5, col. 6, ll. 55-65; Bennett
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Fig. 84.) In other words, some data lines stay logical 0 as initiated by the
leading clock edge of (H) φ1, and others change to logical 1 as initiated by
the leading clock edge of (H) φ2.
B9. Bennett ‘988 discloses that the dual clocks are both “distributed
by a master clock.” (Bennett ‘988, col. 7, ll. 61-62.)
B10. Bennett explains that faster operations are possible by
“configured nonperformance of arbitration and slave identification/function
or both.” (Col. 107, ll. 61-63.) Bennett compares “[u]nsophisticated User
devices such as memories” to “sophisticated devices such as processors” –
the former do not know what other devices are on the network. (Col. 58,
ll. 58-65.) As noted supra, Bennett contemplates simple systems having “a
single slave memory.” (Col. 57, l. 57.) Bennett explains that “the number of
[device] locations strongly affects complexity.” (Col. 8, ll. 30-31.) Bennett
distinguishes between slaves and masters: slaves “only respond to
information on the interconnect,” masters “control the interconnect”; thus,
slaves are subordinate to masters. (Col. 8, ll. 30-41.)
B11. Bennett projects speed increases – e.g., systems projected to
“drive signals from chip to chip in 20 to 40 nanoseconds.” (Col. 9, ll. 58-
59.)
Single Chip
The Examiner finds that “Bennett discloses that the memory is a
chip.” (RAN 54 (quoting Bennett at col. 58, ll. 20-21 as disclosing a “‘code
ID indicative of the User chip type (i.e., CPU or memory).’”) As indicated
supra, Rambus maintains that Bennett does not disclose a synchronous
memory device. (Resp. Br. 2-7.) Bennett at least discloses a synchronous
single chip memory device (B1-B6) satisfying claim 1 and renders a
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synchronous DRAM chip as claim 4 requires obvious. For example, with
respect to claims 1 and 4, Wicklund describes DRAM chips as “the most
popular form of read/write memory” (col. 1, ll. 37-38).
8
The ‘696 patent
similarly admits that DRAM chips were “the most widely used” (col. 1, l.
51.) Bennett discloses read/write memory devices, while noting that ROM
chips do not perform writes (B4), thereby implying popular DRAM chips
which do perform reads and writes, as discussed further below.
The Board and a District Court (“Hynix II”)
9
have addressed similar
arguments by Rambus in related proceedings. The findings and rationale in
BPAI 2012-000168 and BPAI 2012-000169, including the rehearing
decisions there, are adopted and incorporated herein by reference.
10

As discussed in the rehearing decision in BPAI-000169, Judge Whyte
in Hynix II (supra note 9) made extensive factual findings and “concludes
that the Manufacturers [including Micron] have carried their burden of
producing evidence that Bennett discloses a memory device, and that
Rambus failed to rebut this showing.” Hynix II at 1131. Judge Whyte
found that the Bennett inventors “were aware of memory cards and referred
to them as such when they chose” and “disparaged the . . . ‘many cards [that]

8
Micron cites Wicklund, U.S. 5,159,676, as evidence of a skilled artisan’s
knowledge of a DRAM chip, and ties the DRAM description there to a
relatively slow, large memory chip to Bennett’s disclosure of relatively
large, slow memory devices. (See App. Br. 6; supra B4.)
9
Rambus, Inc. v. Hynix Semiconductor, Inc. 628 F.Supp.2d 1114, 1132-38
(N.D. Cal. 2008) (Judge R. H. Whyte ruling on anticipation by Bennett of
similar claims 27 and 43 in the 6,314,051 patent which was also involved in
the Board’s BPAI 2012-000169 original and rehearing decisions.
10
See BPAI 2012-000169 BPAI 2012-000168; BPAI 2011-000142; and
BPAI 2012-001638;
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can be placed on the bus.’” (Id. (quoting Bennett at col. 37, ll. 26-28).)
Judge Whyte also found that the Bennett inventors turned away from such
memory cards and toward “VSLIC devices, including memory devices”
which the court referred to as “such memory chips.” Hynix II at 1131.
As indicated in the description of Bennett supra, Bennett refers to
“VLSIC chip devices” and states that “[m]any, if not most, applications of
VLSIC technology are likely to include memory devices.” (Bennett, col. 90,
ll. 42-43; B4.)” Bennett’s “paramount object” is to provide flexible,
versatile, and configurable communication between “very large scale
integrated VLSI (circuit) elements” (col. 12, ll. 14-25) – i.e., “VLSIC chips”
(col. 9, ll. 35-40). (See B1.) The term VLSIC in Bennett and conventionally
(i.e., very large scale integrated circuit) signifies a single chip device. See
Rambus Inc. v. Infineon Tech. AG, 318 F.3d 1081, 1085-86, 1091 (Fed. Cir.
2003) (defining Rambus’s claim term, “integrated circuit device,” as a
“circuit constructed on a single monolithic substrate, commonly called a
‘chip’”) (relying on trade dictionaries, citations omitted). Bennett states that
a VLSIC chip “cannot currently provide for as much memory as can be
placed on a card” (col. 9, ll. 47-48), but “VLSIC technology promises much
higher performance than that of cards,” (col. 9, ll. 45-47), and “[t]he
[VLSIC] technology is projected to drive signals from chip to chip in 20 to
40 nanoseconds” (col. 9, ll. 58-60; B11).
In other words, as Hynix II finds, Bennett turns to memory chips in
place of memory cards. Addressing Rambus’s expert Murphy’s opinion that
Bennett’s 32 address and word bits would signify a room full of memory
cards at the time of Bennett (1982), and not a chip, Judge Whyte found that
“this ‘large memory’ is meant to illustrate the flexibility of the bus interface,
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not to suggest that Bennett contemplates that all memory devices designed
for use in its system should be so large.” Hynix II at 1130. The court also
recognized that Bennett teaches operating with as few as three VBI interface
pins and minimizing the number of node pins; hence, the court reasoned that
Murphy improperly focuses on the 32 bit example and other examples
involving a larger number of pins. See id. at 1130-1131.
Rambus and Murphy here do not assert that Bennett’s 32 address and
word bits signify a room full of memory cards as they did in Hynix II.
Rambus now asserts that Bennett’s large memory signifies “multiple
memory chips.” (Resp. Br. 6 (citing Murphy Decl. ¶ 124.) Murphy does not
set forth the basis for his new position or explain why it differs from his
earlier Hynix II position. In any event, similar to findings to Hynix II,
Bennett discloses “up to 2
32
addresses of 32 bit words.” (Bennett, col. 95, ll.
59-64 (emphasis added)) in disclosing single chip memory devices.
The record shows that Bennett contemplates a wide variety of pin
number[s] (i.e., address and word bits) to replace cards. (See B4.) Bennett
also discloses the option of passing “but a single bit of data from a single
master device to a single slave device.” (Bennett, col. 15, ll. 43-44.)
Bennett also discloses 16 bit words in a large memory slave device and notes
that faster memory devices are available having fewer pins. (See B4.)
Rambus’s argument that in Bennett’s time frame, the fast memory
embodiment also would have required multiple chips (see Resp. Br. 6 (citing
Murphy Decl. ¶ 125)), fails to address Bennett’s specific disclosure that the
Bennett inventors “anticipate” (B4) that “User-devices” (i.e. memory chips –
see B1) would handle the relatively fast speeds (20 to 40 nanoseconds) by
employing fewer data lines or faster chips (B4). Rambus similarly fails to
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address the corresponding Hynix II rationale that Bennett discloses a
versatile and flexible system not limited to any 32-bit memory embodiment.
Rambus’s also contradicts itself by arguing that “one of ordinary skill
in the art would understand a ‘memory device’ to be a chip” (Resp. Br. 6) –
if that is true, then Bennett’s “memory device” also would signify, to skilled
artisans, a single memory chip.
11
Bennett’s disclosure of the same term,
“memory device[]” (B2), references to “VLSIC upon the same chip
substrate,” “interfaces intended to be built with . . . Memory,” (B1) and
other similar references to VLSIC, chips or “same” substrates (B1-B4),
combined with a limited discussion of memory cards as prior art (B3), all
show that Bennett’s memory device includes a single chip embodiment
(even if the term also signifies other memory forms of memory as Rambus
argues). As Micron further explains, Bennett’s Figures 1 and 38 also
describe single chip memory devices. (See App. Br. 5; B1, B2.)
As discussed above, Bennett discloses ROM chips and implies other
chips for reading and writing data (i.e., the popular DRAM chips). (See
RAN 54.) Judge Whyte makes a similar finding:
Bennett discusses ROMs while explaining the limited number
of operations that can be done with a memory device, and it
does so to point out that memories like ROMs cannot receive
write operations. . . .Bennett’s discussion thus impliedly
discloses some type of memory device than can receive write
operations. The jury will have to determine at trial whether
that implied disclosure encompasses a dynamic random access
memory.

11
See In re Rambus, 694 F.3d 42 (Fed.Cir. 2012) (the Federal Circuit
holding that the claim term “memory device” includes, but is not limited to,
a single chip contrary to Rambus’s arguments otherwise).
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Hynix II at 1137 (emphasis added).)

Rambus fails to show error in the Examiner’s findings that Bennett
discloses a single chip memory having a VBI interface and satisfies claim 1.
The findings show that DRAM chips, as claim 4 requires, would have been
obvious. The Examiner maintains that DRAM “memories were well known
and it would have been obvious to use such memories,” that Novak and
Deering disclose DRAMs (RAN 56), and that Rambus “acknowledged that
DRAMs were commonplace” (Id.). Given the genus of memory chips as
disclosed in Bennett and the reference to large and fast VLSIC memory
devices (B2), skilled artisans would have interpreted Bennett’s disclosure as
pointing to the most popular memory chip: a DRAM.
In the hearing before the Board on September 12, 2012 (see hearing
transcript in BPAI 2012-002081 & 2012-001976 (argued together)), Rambus
raised a new argument premised on the Federal Circuit’s recent decision in
In re Rambus, supra note 11. At the Board hearing, Rambus argued that In
re Rambus precludes Bennett’s interface because it is akin to a complicated
processor such as a BIU which the Federal Circuit reasoned was not
included in the term “memory device.” To the contrary, Bennett’s memory
device is a slave (B5, B10) and Rambus itself distinguishes masters from
slaves, as the Federal Circuit’s reasoning points out. See In re Rambus at
49-50. In re Rambus only precludes “a global bus controller or CPU, not
from containing a component that interfaces with the computer system, even
when that component provides some additional functionality.” Id. at 50.
In other words, In re Rambus does not preclude Bennett’s single chip
slave devices which merely respond to master bus processor controllers.
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Bennett also teaches that any device functionality can be disabled to increase
speed and distinguishes such “unsophisticated” slave memory devices from
“sophisticated” processor master controller devices. (See B4, B10.) As
such, assuming arguendo Bennett’s chip interface has too much control, it
would have been obvious to eliminate unneeded functions in the chip
interface for the simple single memory chip at issue here. See In re Sovish,
769 F.2d 738, 743 (Fed. Cir. 1985) (“This argument presumes stupidity
rather than skill.”).
Delay Value
Micron contends that Bennett’s Configuration Parameter VI satisfies
the delay element in claim 1. (App. Br. 9-13.) Rambus contends that
Parameter VI is not “representative” because “Figures 25b, 35, and 36 show
that even when Configuration Parameter VI is set to the same value, data is
transferred at different times.” (Resp. Br. 3.) While the Examiner agrees
that Bennett’s Parameter VI is not a “representative” value as claim 1
requires, findings by the Examiner contradict this claim interpretation. For
example, the Examiner finds that “[i]t is clear that when looking at
[Figures] 25a and 25b, the time period of when a request is received and
when data is sampled changes by at least one bus cycle. This change is
caused by a changing the value in the configuration record.” (RAN 64
(emphasis added).)
In other words, Bennett’s Figures 25a and b (and other preferred
configurations or embodiments) employ only two choices for a
corresponding delay, either two clock cycles or one clock cycle (after the
ID/FUNCTION/ID, i.e., write command), with the two choices determined
respectively by the register programmed numbers 1 (signifying
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multiplexing) or 3 (signifying one wait line). (See B5; RAN 64 (describing
relative total data transmission times of four and three clock cycles).) For
example, within multiple configurations pertaining to the embodiment in
Figures 25a-h, only two choices for programmable digits exist for each
configuration there, either 1 or 3. (B5.)
The separate configurations in the Figure 25 embodiment(s) which
use a 1 or 3 satisfy claim 1 despite what any other configuration may show.
As the Examiner finds, changing the Configuration Parameter VI value from
1 (for multiplexed) to 3 for (1 wait line) “changes the timing of when data is
sampled . . . by one clock cycle.” (RAN 67.)
Rambus does not dispute this underlying factual finding. The
Examiner’s findings show that the independent embodiment in Figure 25,
e.g., the two separately configured Figures 25a and 25b, anticipate claim 1.
The Examiner’s findings, in light of Micron’s explanations, may at most
show that the same number of wait lines across different embodiments does
not always correspond to a set number of total clock cycles, but for any
single embodiment (i.e., species), knowing the configuration for that
embodiment tells the number of delayed clock cycles relative to the
FUNCTIION/WRITE command for that specific configuration and
embodiment.
Moreover, in each of the embodiments, including Figure 36, Bennett
discloses that the data either occurs with the wait signal (for pipelined
systems) or after the wait signal (for multiplex systems). (See B5; Bennett
Figure 36.) Micron persuasively shows that, for example, with respect to
Figure 36, the memory address data transmits on the data lines with the wait
signal (WT) or on the next clock cycle thereafter – with data following the
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two address clock cycles. (See App. Br. 12-13.) As Micron argues, “within
a configured system [i.e. Figure 36], changing [the] configuration parameter
from 3 to 1 explicitly defines, and therefore is representative of, the
sampling delay.” (App. Br. 13.)
The Examiner appears to reason, in line with Rambus’s arguments,
that because different Bennett embodiments (i.e., Figures 25, 33, 35 and 36)
purportedly show a lack of correlation across the different embodiments
between the number of wait lines and the number of clock cycles, Bennett
fails to satisfy the disputed claim limitation. Fundamentally, as Micron
argues, the Examiner erred when comparing the timing of two differently
configured embodiments. The relevant inquiry is examining how changing
Configuration Parameter VI within a specific embodiment will change the
delay before data is sampled.
In other words, Bennett discloses a distinct correlation between the
only programmable (wait line) numbers 1 and 3 for the Figure 25a-h
configurations, that the parameter 1 always results in a two clock cycle delay
for “DATA” after a write request, and the programmable number 3 always
results in a one clock delay for “DATA” after a write request. (See B5.)
Micron makes a similar showing for Figure 33, incorporating the pin names
from Figure 32 which includes the wait pin, into a modified version of
Figure 33. (See App. Br. 10.) With the Configuration Parameter of 2, the
pin and its associated line are not used or do not exist. Micron explains that
changing that parameter to from 3 (or 2) to 1 inserts an additional clock
cycle. (See Bennett Figs. 3, 33; App. Br.10.)
Contrary to Rambus’s arguments (Resp. Br. 4), Bennett only uses
programmable numbers 1 and 3 and specifically excludes other
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programmable wait line numbers (which Figure 3 generally discloses such
as 2, 4, 5) for the specific configurations detailed in Figures 25a-h which
represent individual single chip memories. (See B5.) Bennett also describes
a general preference for using programmable numbers 1 and 3 (even though
the null set 2 is disclosed for the Figure 33 configurations – i.e., no wait
lines). (See B5.) But even if all possible Parameter VI values (i.e., 1-5) are
used, Judge Whyte finds that the values 2-5 create the same write latency –
i.e., zero, while the value 1 creates a one clock cycle latency (because
multiplexing adds another clock cycle). (See Hynix II at 1133-34.) Rambus
agrees that changing the values from 2-5 “does not change the number of
clock cycles that transpire before sampling within a given system.” (Resp.
Br. 4.) Therefore, a value of 1 always has an extra clock cycle in
comparison to the values of 2-5 which always represent the same delay (i.e.,
as a 3). In other words, the values 2-5 represent a one clock cycle delay
(relative to the FUNCTION write) and the value 1 represents a two clock
cycle delay (relative to the FUNCTION write).
12

Figure 36 represents a special case allowing for multiple word
transfers and does not refute what Figures 25a and 25b disclose, contrary to
Rambus’s assertions. It shows address and data information following the
Wait signal. Rambus maintains that Micron does not explain how Figure 36
shows the delay value. (See Resp. Br. 4.) But Micron does explain this –
changing the configuration parameter of 1 to 3 “indisputably delays the
sampling of data by one clock cycle.” (App. Br. 12-13.) In Figure 36, the
two address words come first, before the two data words. As indicated

12
The term “delay” does not appear in claim 1, but is used here to refer to
the recited phrase in claim 1 of “an amount of time to transfer.”
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supra, Figure 36 corresponds to a large memory system of up to 2
32

addresses of 32 bit words. But to the VBI system, 32 bit address and data bit
words look like “4 sixteen bit words.” (See Bennett, col. 95, ll. 59-68.) And
Bennett’s system knows exactly which two groups of these sixteen bit
groups constitutes the two address groups and their timing relation to the
two following data groups – the whole purpose of Bennett’s system is to
transfer data. As Micron explains, Bennett’s protocol knows “when (in what
relationship and/or sequence)” (App. Br. 13 (quoting Bennett at col. 39,
ll. 31-34).) Essentially calling the first address word a generic first data
word (while recognizing that it is an address word) in Figure 36 as Bennett
implies shows that it occurs at the same time relative to the Function
command as the data word does in Figure 25b – i.e., concurrent with the
Wait signal and immediately after the Function command – as the
Configuration Parameter value of 3 predicts for both.
13

“In FIG. 36 a Versatile Bus of 43153355 configuration has handled a
block of 4 sixteen bit data words.” (Bennett, col. 96, ll.40-42.) Bennett
makes clear that with respect to the large memory configured species
represented in Figure 36, “the configuration that four total cycles should be
utilized requires naught but some associated control between the Versatile
Bus Interface Logic(s) and User(s).” (Bennett, col. 96, ll. 33-36.) And even
if claim 1 preclude such minimal (“naught”) “associated control,” which it
does not, in any given system contemplated by Bennett wherein such

13
Figure 35 deals with arbitration and reads. Even if Figure 35 is relevant to
the inquiry, it shows, after winning arbitration, the same data to function
delay as other memory devices using a 3 for Parameter VI (e.g.,
Figures 25b). (See Bennett, col. 95, ll. 18-27.)
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minimal control sets the total number of clock cycles for the block data
transfer, the specific (e.g., 43153355 for Fig. 36) configuration ultimately
dictates both the word length and time delay within that configured species,
thereby satisfying the claims. Stated differently, each Figure 36 configured
species may include different subspecies wherein each subspecies may have
different “associated control,” for example, 4 total clock cycles, 8 total clock
cycles, etc., but within each subspecies, the configuration parameter VI
dictates the delay (and other parameters VII and VIII dictate the block size).
(See PTAB 2012-1638 rehearing decision (further discussing the
“representative” block size recited in claim 26 there).) Moreover, such
“associated control” does not alter the initial fixed delay value relative to the
first address word which configuration parameter VI controls - it only alters
the total clock cycles or number of “words” (address and data) transmitted.
Therefore, contrary to Rambus’s related assertions (Resp. Br. 3),
Tehrani v. Hamilton Med. Inc., 331 F.3d 1355, 1361 (Fed. Cir. 2003) does
not support Rambus’s position that the Board’s interpretation of
“representative” is too broad. Bennett’s configuration parameter VI not only
represents the delay time as discussed, it dictates that time in a direct
manner. As such, contrary to Rambus’s assertion, Bennett’s parameters do
not constitute “any [non-representative] case in which the two items are
[merely] related in some way.” See id. Rather, Bennett’s configuration
parameter value VI represents, “‘symbolize[s]’” or “‘stand[s] for’,” see id.,
the delay time and block size - since it dictates that delay time. Skilled
artisans, given the parameter values and specifically configured embodiment
(including any associated control if a large memory subspecies of Figure 36
is implemented) as described in Bennett, would be able to directly determine
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the delay time from the configuration parameter VI – and changing that
parameter within a configured species or subspecies would change the delay
time.
Most importantly, this interpretation comports with the ‘696 patent.
In the ‘696 patent, users must know which code of several “other block size
encoding schemes” will be used to determine the block size. (See ‘696
patent, col. 11, ll. 59-60.) Even in the preferred embodiment, skilled artisans
must know the value of the initial block code bit. (See id. at ll. 39-45.) In
other words, without knowing the encoding scheme and the first coding bit
in the preferred encoding scheme, skilled artisans could not determine an
analogous block size “representative” value recited in other Rambus patents.
(See PTAB 2012-001638 at 20-22 (rehearing decision analyzing a similar
“representative” block size information in 6,426,916 claim 26).) It follows
that the term “representative” as employed in the ‘696 patent does not
preclude dependency on other information.
Based on the discussion supra, and notwithstanding that Figures 25a-h
and Figure 36 each separately satisfies the claimed delay value, even if
Figure 36 is compared to Figure 25 as Rambus urges, changing the
Parameter VI from 3 to 1still satisfies the claimed “representative”
relationship.
Synchronous Memory Device and External Clock Signal
Rambus argues that Bennett does not disclose a synchronous memory
device because “one of ordinary skill would not understand the many chips
and circuitry that make up the VBI and ‘memory’ to be this claimed
feature.” (Resp. Br. 4.) Appellant similarly argues that Bennett’s memory
does not receive an external clock signal because “Bennett’s memory
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includes multiple memory chips” and “any clock signal . . . is only provided
to the separate VBI. “ (Resp. Br. 7.) These arguments, and similar
arguments (App.Br. 5-6), constitute various forms of the single chip
argument addressed above as Micron points out. (Reb. Br. 7.) Contrary to
Rambus’s arguments, Bennett discloses sending synchronous clock signals
to its memory devices. (See B6; accord Reb. Br. 7 (relying inter alia on
Bennett’s Figure 52a and other synchronous teachings).)
Operation Code
Rambus argues that Bennett’s “three signal lines” which must be
“maintained [as voltages] during the entire time data is serially shifted in
proves there is no operation code.” (Resp. Br. 8.) Rambus fails to explain
why voltages on signal lines cannot constitute a first operation code as set
forth in claim 1.
Micron points to Bennett as disclosing respective logical 1s or 0s
(high or low values) to “SET DATA” and gating a bit pattern in the
configuration register using a clock. (App. Br. 8.) While Rambus indicates
that the operation code must be “‘one or more bits in a request packet’”
based on a proposed definition by Micron in related litigation (App. Br. 8),
nothing in claims 1 or 4 require a request packet or bits. Moreover, Murphy
agrees that “operation codes . . . need not be transmitted in a packet.”
(Murphy Decl. ¶ 37.)
Further, Bennett’s logical low and high values reasonably correspond
to bits. And the ‘696 patent allows for registers “which can be
preprogrammed or even hard wired.” (‘696 patent, col. 10, ll. 11.) Rambus
does not direct attention to how the ‘696 patent defines a “first operation
code” which distinguishes over Bennett’s logical levels used to store values
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in Bennett’s configuration register. Also, claim 1 requires a first and second
operation code, and Rambus does not direct attention to a definition in
the‘696 patent for these two codes which would limit claim 1 and
distinguish over Bennett.

Transferring Data on Both Clock Edges
Claim 1 requires outputting data synchronously with respect to rising
and falling edges of a clock pulse. The Examiner maintains that the record
does not render obvious using both clock edges because modifying
Bennett’s clocking scheme would render it inoperable for its intended
purpose. (See RAN 73.) Despite Rambus’s contentions, Micron’s
responses, which rely on the secondary teachings of Inagaki, Deering, or
Novak, show the obviousness of employing rising and falling edges to input
or output data, as discussed further below. (See App. Br. 14-17.)
Inagaki’s Teachings
I1. Inagaki discloses a method for increasing data rates in block
access memory. As background, Inagaki teaches that conventional methods
to increase data transfer rates in RAMs involved increasing the data bus
width, which adds cost of packaging and pin count, or to increase the clock
rate. (Inagaki 2.) Inagaki’s solution is to use dual edges of a clock as
quoted as follows.
I2. “The rise and fall of external clock φ are detected, and clocks φ1
and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the shift
register. . . . In this way, since one bit is output on each half-cycle, the
operating speed is twice that of the conventional speed.” (Id. at 4.)
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I3. “[T]he present invention presents block access memory that
transfers data with a speed that is twice the conventional speed, by
performing I/O [input/output] of data on every half-cycle of the external
clock that drives the I/O shift register.” (Id. at 3.)

Discussion
Rambus maintains that using Inagaki’s clocking scheme in Bennett
would not have been obvious for various reasons. The Examiner
maintains that the cited prior art shows that outputting data on
both edges of a clock signal have known benefits and that one
of ordinary skill in the art would seek to apply this teaching to
various systems. However, as argued by the Patent Owner the
combination would render Bennett inoperable for its intended
purpose.
(RAN 73.)
The Examiner reasons that “the second driving corresponding to the
falling edge of H φ2 would corrupt or destroy any signal driving based on
the rising edge of H φ2.” (RAN 73.) Rambus makes similar arguments.
(See Resp. Br. 9.)
Rambus also maintains that Inagaki uses pulses and not a periodic
clock. (Resp. Br. 9.) Rambus also asserts that Novak’s clock is not periodic
and that Deering does not employ a clock with a memory device. (See Resp.
Br. 10-12.) Based on the issues of record and the arguments presented,
Deering and Novak appear to be largely cumulative to Inagaki and disclose a
clock with signals on rising and falling edges.
Inagaki refers to an “external clock” repeatedly and the clock is
periodic at least while it operates: “The rise and fall of external clock φ are
detected, and clocks φ1 and φ2 are generated. . . . . In this way, since one bit
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is output on each half-cycle, the operating speed is twice that of the
conventional speed.” (Inagaki at 4 (emphasis added.) Inagaki’s system
performs “data input or output every half-cycle based on an external clock.”
(Id. at 2.) Inagaki’s numerous computer clock references point skilled
artisans to and embrace the well-known computer clock – in other words,
the same type of external computer clock generically claimed in the
‘696 patent.
14
See In re Paulson, 30 F.3d 1475, 1480-81 (Fed. Cir. 1994) (“a
prior art reference must be ‘considered together with the knowledge of one
of ordinary skill in the pertinent art’,” and where the skill level was “‘quite
advanced’ . . . ‘one of ordinary skill certainly was capable of providing the
circuitry necessary to make the device operable for use as a computer’”)
(citations omitted).
Also, Bennett employs different periodic external clocks (see B6;
Bennett Fig. 84; Abstract) and Rambus’s arguments amount to an
unpersuasive separate attack on the references. Micron relies on the
combination to suggest using the rising and falling edges of a clock. Micron
adds that Inagaki teaches using dual edges of a single clock in order to
increase speed or reduce the number of data pins or paths in a memory
device. Micron relies on similar teachings in Novak and Deering. (See App.
Br. 14; I1-I3; Novak, col. 6, ll. 34-35; 4f, 4d (“[f]or read operations it takes

14
clock . . . A source of accurately timed pulses, used for synchronization in
a digital computer . . . .” McGraw-Hill Dictionary of Scientific and
Technical Terms 387 (Fifth Ed. 1994). This reference indicates that clock
signals and clock pulses are the same: i.e., “clock signals. See Clock
pulses.” Id. “[C]lock pulses. . . . Electronic pulses which are emitted
periodically, usually by a crystal device, to synchronize the operation of
circuits in a computer. Also known as clock signals.” Id.

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only 128 cycles of the clock φ to output 256 bits”; Deering at 23-24
(describing a “factor of two reduction in pin count . . . by double clocking
the I/O pins” and note at 24 stating that “[d]ata is transferred on both rising
and falling phases of the clock, using each pin twice per clock cycle.”)
15

Rambus also maintains that Bennett discloses an “intricate clocking
system” and a “complex system” which precludes the proposed modification
of employing leading and falling clocking edges because such a
modification would destroy Bennett’s principle of operation and would lack
any reasonable expectation of success. (See Resp. Br. 9.) The Federal
Circuit recently rejected a similar argument under analogous circumstances
based on the observation that an asserted “difference does not affect the
operability of Mouttet’s [i.e., the applicant’s] broadly claimed device—a
programmable arithmetic processor.” In re Mouttet, 686 F.3d 1322, 1332
(Fed. Cir. 2012) (citations omitted) (also reasoning that physical
incorporation is not required to support obviousness).
The principle of operation of the broadly claimed memory device here
involves synchronously outputting data from a memory device on both clock
edges of the clock. Bennett’s principle involves “its high level ability to,”
see Mouttet at 1332, transfer data synchronously (B6) to and from a single
memory device or a group of such devices, using a “simply controlled,” yet
versatile, system (B4, accord B10 (“single slave device”)). For example,
Bennett’s system is

15
Several previous Board decisions reasoned that Inagaki discloses a clock
and using dual edges therefore. See, e.g. BPAI 2012-000171 (finding
obviousness with respect to combining Inagaki with a prior art reference
using a dual clocking scheme). The findings and rationale involving Inagaki
are adopted and incorporated by reference.
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configured so simply as to pass but a single bit of data from a
single master device to a single slave device, or with ten deep
pipelining of eight phases of time-based arbitration (between
256 devices) time overlapped with slave identification/function
. . . . The versatility is from the trivial to the profound
(Col. 15, ll. 42-50 (emphasis added); accord B4.)
Using one or two external clocks does not undermine this broad
principle of versatile data transfer and coalesces with the broad principle
underlying claims 1 and 4. Moreover, Bennett’s dual clocking scheme
mainly uses the leading edge of (H) φ1 to precharge the bus lines. (B8;
accord RAN 68.) Such a scheme is not required to read data from a single
device as Inagaki, Deering and Novak show, and is not required to satisfy
claims 1 and 4. Bennett points out that the precharging scheme allows for
reduced interface transistor sizes to precharge the bus in a wired-OR fashion
– i.e., used to with multiple slave devices. (See B8.) As such, skilled
artisans would have recognized the pre-charging scheme would not be
required for “trivial” or simpler systems such as Bennett’s single slave
memory chip - i.e., since a large interface transistor and a known single
clock scheme could be employed to drive from one to a handful of chips - as
Inagaki and Bennett suggest.
Therefore, while Rambus and the Examiner maintain that any
modification of Bennett’s precharging system would result in corrupted data.
(see Resp. Br. 9 (citing Murphy Decl. ¶¶ 141-144), this argument ignores the
simple substitution rationale for trivial systems which Bennett envisions as
discussed supra. But even if Bennett suggests that precharging is required
or advantageous as implemented on the leading edge of phase (H) φ1, data
corruption would not occur contrary to Rambus’s arguments. For example,
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the second falling transition of phase (H) φ1 could be employed to change
selected portions of the data to a low voltage value as Inagaki suggests -
instead of using the leading edge of phase (H) φ2 to drive the selected data
voltages low. (See B8.) Moreover, Bennett’s system further suggests, if not
discloses, such a modification because Bennett discloses that the trailing
(H) φ1 edge coincides with the leading (H) φ2 edge in Bennett’s 50% duty
cycle option. (See B7, B8.) Therefore, it would have been obvious to
provide high voltage data on the leading edge of (H) φ1and then drive
selected lines low on the trailing edges of (H) φ1. Notwithstanding
Rambus’s arguments, such a simple modification would not corrupt the data
on different lines of the bus and it would satisfy outputting first and second
portions of the data –i.e., first portions corresponding to high voltage data
outputted at the first leading edge of (H) φ1, and second portions (on
different data lines of the same bus) corresponding to low voltage data
outputted the second leading edge of (H) φ1. Changing the data on the bus,
albeit on different data lines within the bus, does not corrupt the data.
Rambus, Murphy, and the Examiner do not address the above-
described scenario involving Bennett’s disclosed 50 % duty cycle option.
16

Rather, Murphy bases his opinion on the faulty factual premise that “Bennett
specifically contemplates that the ‘clock signals’ will not have a 50 percent

16
In a supplemental declaration in the related PTAB ‘1976 case, Murphy re-
phrases and states that Bennett “may have a 50% duty cycle” but Murphy
merely repeats the unsupported assertion that the clock edges in Bennett “do
not overlap” without addressing the 50% duty cycle option further or in
more than a conclusory fashion. (See PTAB ‘1976 Supp. Murphy
Decl. ¶¶23, 25.)

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duty cycle” (Murphy Decl. ¶ 142) such that the signals “do not overlap” (id.
at ¶ 143.) Rambus’s arguments, based on that faulty premise, also strike
down a straw man in which Rambus suggests using both edges of (H) φ1 to
pull the data lines to a high voltage. (See Resp. Br. 9.) Rambus does not
explain why one would use both edges to drive the same data lines high
when they would already be high pursuant to the first edge. In any event, as
indicated, Rambus’s arguments are based on the false premise that Bennett
does not contemplate symmetrical (50 % duty cycle) (H) φ1 and (H) φ2 wave
forms. As discussed above, Bennett’s 50 % duty cycle option essentially
teaches or at least suggests that the leading edge of one clock phase
coincides with the falling edge of the other – Inagaki’s internal clocks
overlap in the same fashion. (Compare B7, B8 and Bennett’s Figure 84 with
Inagaki Fig. 4.)
17

In other words, Bennett’s principle of transferring data “is not unique
to its . . . [specific dual clocking] operation” as depicted in Figure 84. See
Mouttet at 1332. As also noted, Bennett’s scheme envisions “trivial”

17
Rambus (citing Murphy Decl. at ¶¶ 141-44) implies, albeit, not clearly,
that “driving” data and capturing data corresponds to outputting data onto
the bus and then taking the data of the bus lines – and that this somehow
causes data corruption in a modification of Bennett. (See Resp. Br. 9.)
Bennett’s system does not corrupt data under the modification and claim
interpretation described - one data line does not corrupt another data line on
the same bus. Also, Rambus fails to explain how the ‘696 patent system
functions without corrupting data - Rambus does not explain how the
disclosed system drives data on the bus at a leading clock edge and then
drives other data at the trailing clock edge without somehow first removing
the data driven on the leading edge. Apparently, as in Inagaki, the same
clock edge triggers data output from one device and data input to another
device (perhaps due to clock edge propagation delay), or, the claim refers to
different data lines as noted.
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33
schemes, including those embraced by the broad reach of claims 1 and 4,
which require reading data synchronously from a single memory chip using
the dual edges of a clock as Inagaki, Deering, or Novak suggest. Bennett
also describes the clocking scheme as merely a “preferred embodiment of
the invention,” and indicates that “the electrical timing is capable of being
altered.” (See Bennett, col. 277, ll. 24-26.)
18

Rambus has not demonstrated that skilled artisans, motivated by
Inagaki’s, Deering’s, or Novak’s teachings of using rising and falling clock
edges for increasing data transfer speed from known DRAM memory
devices, would have been unable to modify Bennett’s system to arrive at the
broadly claimed invention. Inagaki’s, Deering’s, or Novak’s dual clocking
scheme provides the fastest possible signal transfer on a bus without
increasing the pin count or data path width, thereby providing the motivation
for the modification. (See I1-I3; Novak, col. 6, ll. 34-35 Fig. 4f, 4d.)
Inagaki, Deering, and Novak also provide evidence of a reasonable
expectation of success in using dual clock edges on data for increased speed,
especially for “trivial” systems using a single or a handful of memory
devices, as Bennett teaches. Increased speed and compactness by reducing
bus width and corresponding pin number while saving cost (see I1)
constitute universal motivators. Dystar Textilfarben GmBH & Co.
Dutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006)
(“[A]n implicit motivation to combine exists … when the ‘improvement’ is

18
While the full passage implies altering the duty cycle of both clocks,
skilled artisans would have recognized that simple single memory device
systems as claimed would not require two clocks as Inagaki, Deering and
Novak make clear and as discussed supra.
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34
technology-independent and the combination of references results in a
product or process that is more desirable, for example because it is stronger,
cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.”)
Also, “if a technique has been used to improve one device, and a person of
ordinary skill would recognize that it would improve similar devices in the
same way, using the technique is obvious unless its application is beyond his
or her skill.’” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417
(2007)(citation omitted).
Despite Rambus’s related arguments that Micron has not shown how
to modify Bennett’s two phase system (see Resp. Br. 8-9), Rambus has not
shown that the proposed modification would have been beyond the skill of
an ordinary artisan, and the Court has also recognized that “the interaction of
multiple components means that changing one component often requires the
others to be modified as well.” KSR, 550 U.S. at 424. In other words, as
KSR implies, making other required modifications to increase the data speed
by using both clock edges, as Inagaki, Deering, or Novak suggest, does not
defeat obviousness or show inoperability.
Further, Mr. Murphy states that the clocking scheme was “often
referred to as ‘dual edge clocking’ and allows for data transfer at twice the
rate of the external clock signal.” (Murphy Dec ¶ 26) (filed May 13, 2009 in
the 95/001109 reexamination proceeding – i.e., involving BTAP ‘1976).)
Mr. Murphy also explains that “[o]ne of ordinary skill in the art would
understand a synchronous bus, by its very nature, relies on a clock, but the
way that clock is distributed in the system need not be limited to any
particular distribution scheme.” (Id. at ¶ 41.) Mr. Murphy’s testimony
indicates that skilled artisans knew how to implement what was often
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35
referred to as “dual edge clocking” to double the data rate and knew how to
apply different clocking schemes to clocked systems like Bennett’s
synchronous clocking scheme.
Given the claim breadth and high level of ability involved, skilled
artisans easily could have modified Bennett’s system in view of Inagaki’s,
Deering’s, or Novak’s clocking scheme to create a cleaner system, dropping
any unneeded functions in a single device memory system (e.g., arbitration
signals, etc.), where Bennett’s system provides broad flexibility and
versatility and includes trivial systems with only one slave. Such a “cleaner”
memory device to handle single direction data transfers as embraced by
broad claims 1 and 4 constitutes a universal motivator under Dystar.
Also, Rambus’s reliance on Bennett’s Figure 84 to show that Bennett
requires a two phase intricate clocking system (see Resp. Br. 9) improperly
assumes that any structure implied by the example of Figure 84 must be
physically combinable with a known dual clocking structure – a proposition
Mouttet and other cases refute. See also In re Sneed, 710 F.2d 1544, 1550
(Fed. Cir. 1983)(citations omitted) (“[I]t is not necessary that the inventions
of the references be physically combinable to render obvious the invention
under review.”); In re Nievelt, 482 F.2d 965, 968 (CCPA 1973)
(“Combining the teachings of references does not involve an ability to
combine their specific structures”). As indicated supra, Bennett’s pre-
charging system and dual clocks are not required to satisfy the broad claims.
Assuming for the sake of argument that such a physical combination
is required to show obviousness, skilled artisans would have recognized that
Bennett’s Figure 84 system could have been modified as discussed above, or
under still another alternative, to include the dual edges of slower external
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36
Inagaki clock as triggers for the leading edge of the faster clock (H) φ1 and
falling edge of clock (H) φ2 represented in Figure 84. That is, in Inagaki
(see Fig. 4), a slower external clock φ has rising and falling dual edges
corresponding to and triggering single leading edges of faster clock φ1 (and
falling edges of clock φ2), suggesting a similar external clock to trigger the
(H) φ1 and (H) φ2 clocks in Bennett. (See e.g. Inagaki Fig. 4; I3.)
19
Bennett
employs multiple clocks, as does Inagaki, rendering such a combination
obvious. Still further, Bennett ‘988 discloses that Bennett’s dual clocks are
both “distributed by a master clock.” (Bennett ‘988, col. 7, ll. 60-61.) The
‘696 patent similarly discloses “clocking at half the bus cycle data rate.”
(See ‘696 patent, col. 19, ll. 39-40 (describing the 500 MHz bus as using a
250 MHz clock).)
Also, the thrust of Rambus’s arguments are not commensurate in
scope with claims 1 and 4, which do not require the “intricate clocking
system” (Resp. Br. 9) of Bennett. As discussed, claims 1 and 4 broadly
embrace a memory device which outputs one-way data synchronously. The
record indicates the structural features of claims 1 and 4, including sense
amplifiers, input receivers, and output drivers, constitute well-known
components of typical DRAM memory devices at the time of the invention.
(See e.g., ‘696 patent, Fig. 15; col. 23, ll. 43-65 (describing a “conventional
4 Mbit DRAM” and explaining that “[m]any of these details have been
implemented selectively in certain fast memory devices”); accord Micron’s
Request 33 (pointing to Bennett as disclosing known the circuitry in

19
Bennett also discloses varying the duty cycles of the two clocks as noted
above so that the clock edges would coincide just as Inagaki’s clock edges
do.
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37
claim 1.) Rambus has not demonstrated that skilled artisans, motivated by
the known use of rising and falling clock edges to increase data output speed
from known generic or DRAM memory devices on a single bus, would not
have been able to arrive at the broadly claimed invention.
Based on the foregoing discussion and the discussion below involving
secondary considerations, Micron has shown that the Examiner erred in not
maintaining the rejection of claims 1 and 4 based on Bennett, and Inagaki,
Deering or Novak.
Secondary Considerations
Rambus contends that substantial secondary evidence supports
unobviousness. (Resp. Br. 15.) But the evidence fails to establish a nexus
because any success likely flows from a variety of several unclaimed
features touted here or in other Rambus proceedings or patents. Such
unclaimed, but disclosed features, include eight data lines, small DRAM
sizes with minimal bus loading, multiplexed bus architecture and device
interfaces, packetized control, unique device identifiers, time access and
arbitration schemes, a 500 MHz data rate, controlled-impedance, double
terminated lines, and memory devices having all the functionality of prior art
circuit boards. (See ‘696 patent, Abstract, col. 3, ll. 22-47; col. 4, ll. 20-55;
col. 7, ll. 8-25; col. 9, ll. 39-65; col. 12, ll. 45-58; col. 14, ll. 48-50; Murphy
Decl. ¶¶ 33-37.) See also Rambus Inc. v. Infineon Technologies AG, 318
F.3d 1081, 1094-95 (Fed. Cir. 2003) (“The present invention is designed to
provide a high speed, multiplexed bus’” (quoting Rambus’s related ‘918
patent, col. 5, ll. 36-46), but “the prosecution history shows that a
multiplexing bus is only one of many inventions disclosed in the
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‘898 application.”)
20
Rambus agrees that “the original disclosure includes
many different inventions.” (Resp. Br. 13.) Similarly, Murphy argues that
“[t]he original disclosure includes a number of different inventions.”
(Murphy Decl. ¶ 34.)
As Micron points out, Rambus presents the same evidence it provided
“in every one of the 10 pending inter partes reexaminations.” (Reb. Br. 18.)
Different claims in the different proceedings have varying scope. As Micron
also points out, Rambus’s proffered evidence is short on objectivity and
relies on interested witnesses. (See id.)
Rambus’s evidence does not demonstrate that any success was due
solely to the claimed features, or to claimed features that were not already
known in the prior art. For example, Rambus’s contention “that the
Farmwald family, which includes the ‘696 patent, has numerous licensees”
is a vague statement which lacks a specific nexus to the claims. (See Resp.
Br. 15.) Rambus does not provide a copy of any licenses (even if one does
pertain to the ‘696 patent) or provide evidence showing what other
unclaimed features any of the licenses involve. Also, it is well known and
settled law that competitors often take licenses for commercial or other
reasons having nothing to do with unobviousness.
Single chip synchronous memory devices were known as Bennett
discloses, as were DRAMs, and operation codes, as the prior art discussed
supra discloses. For example, “the most popular form of read/write memory

20
See Infineon, 318 F.3d at 1084-86 (finding that the written descriptions of
each of four related Rambus patents, 5,954,804; 5,953,263; 6,034,918; and
6,032,214, are substantially identical to the written description of the
07/510,898 application to which they, and the ‘446 patent here, all claim
continuity).
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is the semiconductor DRAM.” (Wicklund, col. 1, ll. 36-39.) Hence, the
record suggests that at least part of any commercial success would have been
due to “the most popular” memory chip, a DRAM chip, in general (or to
Bennett’s known synchronous chip in general). Cf. In re DBC, 545 F.3d
1373, 1384 (Fed. Cir. 2008) (Board’s conclusion of nonobviousness
supported, the Board finding, inter alia, that “evidence in the record
suggested that the success of XanGo™ juice may be due to other factors-for
example, the increasing popularity of the mangosteen fruit in general” ).
The Federal Circuit further reasoned in DBC that
. . . DBC has done little more than submit evidence of sales.
However substantial those sales, that evidence does not reveal
in any way that the driving force behind those sales was the
claimed combination of mangosteen fruit, mangosteen rind
extract, and fruit or vegetable juice. Nor is there any evidence
that sales of XanGo™ juice were not merely attributable to the
increasing popularity of mangosteen fruit or the effectiveness of
the marketing efforts employed.

Id. at 1384. See also Ormco Corp. v. Align Technology, Inc., 463 F.3d 1299,
1312, 1313 (Fed. Cir. 2006) (“[I]f the feature that creates the commercial
success was known in the prior art, the success is not pertinent.” Reasoning
that success that is due “‘partially’ to claimed features” and to unclaimed
features and/or other features already in the art lacks the requisite nexus to
show unobviousness.) (Citations omitted).
While Rambus argues that the claims solve a memory bottleneck
problem and obtain high-speed performance (Resp. Br. 15), the claims read
on slow memory devices, since the claims do not recite any speed (as a
functional limitation) and do not recite other sufficient and necessary
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40
circuitry to obtain such speed.
21
Moreover, Dr. Farmwald testified that
“even up into the early part of the ‘90s, it [speed] wasn’t going to be a
problem.” (See Farmwald Trial Dep. 276 (attached as Resp. Br. Evidence
Ex. E-5).) In other words, Dr. Farmwald may have solved a problem
predicted to occur in the future, but not a long-standing problem.
Rambus’s allegations of recognition and praise for the “‘high
bandwidth memory-interface technology’” and bandwidth advances “‘as a
result of the ideas [Dr. Horowitz] pioneered’” (Resp. Br. 15) point to a lack
of nexus as to any success or praise. The devices claimed here have no
bandwidth limitation, let alone limitations directed to the myriad other
“ideas [Dr. Horowitz] pioneered” – whatever they may have been.
Based on the foregoing discussion, the record suggests that the
proffered evidence is not commensurate with the claim scope and lacks a
nexus thereto. Rambus has not demonstrated that any success is not due to
popular DRAMs in general, synchronous memory chips in general, or, to a
whole host of unclaimed features, including the unclaimed but touted
multiplexed bus interface, high bandwidth and/or speed, and other
unclaimed circuit features, such as the identification feature, arbitration
control features, low capacitance and power, precharging circuitry, and

21
In another reexamination proceeding, similar to the proceeding here
(Resp. Br. 15), Rambus alleges “disbelief” and pervasive skepticism “‘over a
500 megabit per second DRAM data rate’” and “about many of the specific
features of the technology” as showing “‘strong evidence of
nonobviousness.’” (See Rambus Resp. Br. 19 (citations omitted) in the
BPAI 2012-000142 reexamination proceeding.) Assuming for the sake of
argument that uncorroborated statements by the inventors show skepticism
by others, as noted, claims 1 and 4 do not require the 500 MHz speed touted
or “many of the other specific features” – whatever they may be.
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41
block data transfer circuitry. The record indicates that such features (and
other pioneering ideas) would have been required to obtain the touted high
speed from a single DRAM upon which any alleged success appears to be
based. See Infineon, 318 F.3d at 1095 (quoted supra, mentioning Rambus’s
high speed multiplexed system).
After careful consideration of the record, the obviousness of
combining known clocking systems with Bennett’s synchronous memory
device and DRAMs outweighs the proffer of secondary considerations.

Priority (relative to the JEDEC and Park references)
Micron asserts that since claims 1 and 4 do not recite a multiplexed
bus so that the claims are not originally supported back to the (first-filed)
‘898 application having a filing date of April, 1990. In other words, Micron
contends that the claims are too broad; i.e., too broad absent a recitation to a
multiplexed bus chip interface which the ‘696 patent touts as important.
Based on these contentions, Micron asserts that the claims are not
entitled to a filing date prior to the ‘696 patent’s application filing date of
April 13, 2001, and are therefore anticipated by the JEDEC and Park
references which antedate the 2001 date. (See App. Br. 26.) Rambus’s
procedural attack, asserting that Micron does not have standing to argue
rejections raised by requester Samsung, has been addressed in prior petition
and Board decisions as noted above.
Rambus generally agrees with the Examiner but asserts that the
Examiner should not even address the priority issue because the Examiner
has no authority to determine the specific written description issue
underlying the priority analysis involved in this reexamination proceeding.
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(See Resp. Br. 13.) Notwithstanding Rambus’s assertion, Rambus fails to
even allege that the prosecuting examiner considered the specific issue of
support for a generic memory device (i.e., one lacking a multiplex bus
interface) which might otherwise preclude determining priority here.
Rambus relies, inter alia, on Rambus Inc. v. Infineon Technologies
AG, 318 F.3d 1081, 1094-95 (Fed. Cir. 2003) to show that the claims do
not require a multiplex bus and are therefore originally supported. (Resp.
Br. 13.) As Rambus notes, the Examiner agrees with Rambus that the
claims are originally supported. (See id. (citing prior office actions).)
Several of the Board’s related decisions, for example, BPAI 2012-
000142, 2012-000168, and 2012-000169, address the same or similar issue
between the same parties. Our decisions, analysis and findings there are
adopted and incorporated by reference herein.
As discussed in our prior decisions, Infineon held that the ordinary
term “bus” could not be read restrictively as a “multiplexed bus” even
though the patentee described the “present invention” in terms of a
“multiplexed bus” in isolated portions of the specification because “the
remainder of the specification and the prosecution history shows that
Rambus did not clearly disclaim or disavow such claim scope in this case.”
Infineon, 318 F.3d at 1094-95.
Micron maintains that the claims violate the written description
requirement since the ‘898 patent application, to which the ‘696 patent
claims priority, touts the importance of a multiplexed bus and distinguishes
prior art generic bus inventions. (See App. Br. 21-25.) Micron supports the
theory, which in essence, amounts to a scope of enablement attack on the
claims, by relying, inter alia, on LizardTech, Inc. v. Earth Resource
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Mapping, Inc., 424 F.3d 1336, 1344 (Fed. Cir. 2005) (generic seamless
DWT claim too broad absent an updated sums limitation). (App. Br. 20.)
Micron relies on a “key factor” in LizardTech as embodied in an analogy
there to an inventor who describes a fuel-efficient engine in such detail that
it would not necessarily support “a broad claim to every possible type of
fuel-efficient engine.” (App. Br. 20 (quoting LizardTech, 424 F.3d at
1346).) As another example, Micron reasons that the claims here are
analogous to the “‘spikeless’” valve claims addressed in ICU Medical.
(App. Br. 20-21 (quoting ICU Medical, Inc. v. Alaris Medical Systems, Inc.,
558 F.3d 1368, 1377 (Fed. Cir. 2009)).
But the gravamen of these arguments is that the ‘696 patent inventors
were not in possession of broad claims directed to generic memory devices
lacking specifically recited multiplexing interfaces. The ‘696 patent refers
to “a preferred implementation” as using only bus connections of the
invention –signifying more generic bus connections or no bus connections.
(See ‘696 patent, col. 5, ll. 50-51.) Moreover, Infineon’s claim construction
analysis, at the minimum, implies that skilled artisans were in possession of
generic memory device claims. See Infineon, 318 F.3d at 1094-95 (noting
that “multiplexing is not a requirement in all of Rambus’s claims” and that
the PTO issued a restriction to a multiplexing group and a latency group,
that “the PTO demonstrated an understanding of “bus” that is not limited to
a multiplexing bus”).
Original claims 73 and 91 in the first-filed ‘898 application recite a
generic bus, showing the possession of generic bus claims – i.e., implying
generic memory devices to respond to the bus. Also, as Rambus points out,
“the original disclosure describes many inventions.” (Resp. Br. 13.) Based
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44
on the original disclosure, skilled artisans would have understood that other
important touted features in the ‘898 disclosure, including clocking schemes
and writing blocks of data, could have been practiced on generic buses
without a multiplexing interface. Accord Infineon, 318 F.3d at 1095 (“a
multiplexing bus is only one of many inventions disclosed in the ‘898
application”); cf. Crown Packaging Tech. Inc. v. Ball Metal Beverage
Container Corp., 635 F.3d 1373, 1382-84 (Fed. Cir. 2011) (district court
erred in finding lack of written description in generic claims where the
application discloses separate solutions to related problems).
The claims at issue require synchronous reading of data. Skilled
artisans would have recognized that these elements could have been
practiced on known buses, whether multiplexed or not. The lack of
multiplexing would have been much simpler than a multiplexing scheme.
Cf. Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336, 1351-53
(2011) (holding that evidence supported jury verdict of written description
for similar Rambus claims where “the supposed genus consists of only two
species, a multiplexed bus and a non-multiplexed bus”).
Also, Micron’s spikeless valve analogy is not entirely apt here
because valves were recited in the ICU Medical claims, but in the
‘696 patent claims, neither a bus nor an interface for attaching to a bus is
recited, so ICU Medical does not dictate that the claims must support any
type of bus or bus interface. But even if the claims implicitly require such a
bus scheme, Rambus, the Examiner, the Infineon claim construction, and the
Hynix Semiconductor written description analysis, show that on this record,
the inventors originally possessed inventions directed to a generic bus
scheme.
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45
Based on the foregoing discussion, Micron has not shown error in the
Examiner’s finding that claims 1 and 4 have original written description
support as necessary to antedate Park or JEDEC as prior art references.

CONCLUSION
Micron has not demonstrated that the Examiner erred in deciding not
to reject claims 1 and 4 based on anticipation by JEDEC or as obvious based
on Park and JEDEC since the references do not antedate the effective filing
date of claims 1 and 4. Micron has demonstrated that the rejections claims 1
and 4 as obvious based on Bennett, and Inagaki, Novak, or Deering, are
warranted. Therefore, the Examiner’s decision not to reject claims 1 and 4 is
reversed.
22

This decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.77(b), which provides that “[a]ny decision which includes a
new ground of rejection pursuant to this paragraph shall not be considered
final for judicial review.” Correspondingly, no portion of the decision is
final for purposes of judicial review. A requester may also request rehearing
under 37 C.F.R. § 41.79, if appropriate; however, the Board may elect to
defer issuing any decision on such request for rehearing until such time that
a final decision on appeal has been issued by the Board.
For further guidance on new grounds of rejection, see 37 C.F.R.
§ 41.77(b)-(g). The decision may become final after it has returned to the
Board. 37 C.F.R. § 41.77(f).

22
See 37 C.F.R. § 41.77(b) (denominating a reversal of a refusal to reject as
a new ground of rejection).
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46
37 C.F.R. § 41.77(b) also provides that the Patent Owner, WITHIN
ONE MONTH FROM THE DATE OF THE DECISION, must exercise one
of the following two options with respect to the new grounds of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. The owner may file a response requesting
reopening of prosecution before the examiner. Such a response must be
either an amendment of the claims so rejected or new evidence relating to
the claims so rejected, or both.
(2) Request rehearing. The owner may request that the proceeding be
reheard under § 41.79 by the Board upon the same record.
Any request to reopen prosecution before the examiner under
37 C.F.R. § 41.77(b)(1) shall be limited in scope to the “claims so rejected.”
Accordingly, a request to reopen prosecution is limited to issues raised by
the new ground(s) of rejection entered by the Board. A request to reopen
prosecution that includes issues other than those raised by the new ground(s)
is unlikely to be granted. Furthermore, should the patent owner seek to
substitute claims, there is a presumption that only one substitute claim would
be needed to replace a cancelled claim.
A requester may file comments in reply to a patent owner response.
37 C.F.R. § 41.77(c). Requester comments under 37 C.F.R. § 41.77(c) shall
be limited in scope to the issues raised by the Board’s opinion reflecting its
decision to reject the claims and the patent owner’s response under
paragraph 37 C.F.R. § 41.77(b)(1). A newly proposed rejection is not
permitted as a matter of right. A newly proposed rejection may be
appropriate if it is presented to address an amendment and/or new evidence
properly submitted by the patent owner, and is presented with a brief
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47
explanation as to why the newly proposed rejection is now necessary and
why it could not have been presented earlier.
Compliance with the page limits pursuant to 37 C.F.R. § 1.943(b), for
all patent owner responses and requester comments, is required.
The examiner, after the Board’s entry of a patent owner response and
requester comments, will issue a determination under 37 C.F.R. § 41.77(d)
as to whether the Board’s rejection is maintained or has been overcome.
The proceeding will then be returned to the Board together with any
comments and reply submitted by the owner and/or requester under
37 C.F.R. § 41.77(e) for reconsideration and issuance of a new decision by
the Board as provided by 37 C.F.R. § 41.77(f).
Extensions of time for taking action under 37 C.F.R. § 41.77(b) are
governed by 37 C.F.R. § 41.77(g). See also 37 C.F.R. § 41.77 regarding
extensions of time for requesting rehearing.
REVERSED

ak

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Finnegan, Henderson, Farabow,
Garrett & Dunner, LLP
901 New York Avenue, NW
Washington, DC 20001-4413

Third Party Requesters:

Novak Druce & Quigg, LLP
(NDQ Reexamination Group)
1000 Louisiana Street
Fifty-third Floor
Houston, TX 77002

David M. O’Dell, Esq.
Haynes & Boone, LLP
IP Section
2323 Victory Avenue
Suite 700
Dallas, TX 75219