Ex Parte 6546446 et alDownload PDFPatent Trial and Appeal BoardSep 26, 201295001109 (P.T.A.B. Sep. 26, 2012) Copy Citation UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/001,109 11/11/2008 6546446 38512.20 9305 22852 7590 09/27/2012 FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 EXAMINER ESCALANTE, OVIDIO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 09/27/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ MICRON TECHNOLOGY, INC. Requester, Appellant v. RAMBUS INC. Patent Owner, Respondent ____________ Appeal 2012-001639 Inter Partes Reexamination Control No. 95/001,109 & 95/001,155 United States Patent 6,426,916 B2 Technology Center 3900 ____________ Before HOWARD B LANKENSHIP, KARL D. EASTHOM, and STEPHEN C. SIU, Administrative Patent Judges. EASTHOM, Administrative Patent Judge. DECISION ON APPEAL Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 2 This merged proceeding arose out of separate requests by Micron (95/001,155) and Samsung Electronics Ltd. (95/001,109) for inter partes reexaminations of U.S. patent 6,546,446 B2 to Farmwald et al., Synchronous Memory Device Having Automatic Precharge (issued April 8, 2003, which claims priority to April 18, 1990 based on a series of continuation applications starting with application number 07/510,898 assigned to Rambus. Samsung has not filed a Brief in this proceeding. Appellant, Requestor Micron, appeals from the Examiner’s decision in the Right of Appeal Notice (RAN) confirming claims 1-4. The Examiner’s Answer relies on the RAN, incorporating it by reference. We have jurisdiction under 35 U.S.C. §§ 134(b) and 315. We REVERSE the Examiner’s decision to confirm claims 1-4 based on certain rejections and AFFIRM the Examiner’s decision not to reject the claims based on other rejections. STATEMENT OF THE CASE Rambus and Micron refer to several related judicial and other proceedings including inter partes and ex parte reexaminations, International Trade Commission proceedings, and Federal District Court and Circuit Court proceedings in their briefs and inter partes requests. An oral hearing of this appeal transpired on June 6, 2012 and was subsequently transcribed. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 3 Appellant, Requester Micron, appeals the Examiner’s refusal to maintain the rejections of claims 1 and 2 as obvious based on Bennett,1 and either Wicklund2 or Bowater3; claim 3 as obvious based on Bennett, either Wicklund or Bowater, and either Schanke,4 Inagaki,5 or Novak;6 claim 4 as obvious based on Bennett, either Wicklund or Bowater, and either Bazes7 or Lofgren;8 claims 1-2 as obvious based on Moussouris,9 Gustavson (“SCI-A”) ,10 and either Wicklund or Bowater; claims 3-4 as obvious based on Moussouris, Gustavson, either Wicklund or Bowater, and Schanke (“SCI-B”). Requester also relies on admitted prior art (“APA”) for most of the rejections and appeals the refusal to maintain the rejections of claims 1-4 as anticipated by JEDEC11 or as obvious based on Park12 and JEDEC. The JEDEC and Park rejections turn on priority. The appealed claims follow: 1 Bennett et al., U.S. 4,734,009 (Mar. 29, 1988). 2 Wicklund et al., U.S. 5,159,676 (Oct. 27, 1992). 3 Bowater et al., U.S. 5,301,278 (Apr. 5, 1994). 4 Schanke, Proposal for Clock Distribution in SCI (May 5, 1989). 5 Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an English language translation of record) (attached as Exhibit 2 to NVIDIA’s Respondent Brief). 6 Novak et al., U.S. 4,663,735 (May 5, 1987). 7 Bazes, U.S. 4,496,861 (Jan. 29, 1985). 8 Lofgren et al., G.B. 2,197,553 A (May 18, 1988). 9 Moussouris, Life Beyond RISC: The Next 30 Years in High-Performance Computing, Technologic Comp. Let. V. 5, No. 5 (July 31, 1989). 10 Gustavson et al., The Scalable Coherent Interface Project (Aug. 22, 1988). 11 Joint Electronic Device Engineering Counsel (JEDEC) Standard No. 21-C, Revision 9 (1999). 12 Park et al., US 5,590,086 (Dec. 31, 1996, effective filing Oct. 1993). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 4 1. A synchronous integrated circuit device having a memory array which includes dynamic random access memory cells, wherein the integrated circuit device comprises: a clock receiver to receive an external clock signal; a plurality of sense amplifiers, coupled to the memory array, to sense data from the dynamic random access memory cells; and a plurality of input receivers to sample an operation code synchronously with respect to the external clock signal, the operation code including precharge information, wherein, in response to the precharge information, the plurality of sense amplifiers is automatically precharged after the data is sensed. 2. The integrated circuit device of claim 1 wherein the operation code specifies a read operation, and wherein the integrated circuit device further includes a plurality of output drivers to output first and second portions of the data in response to the operation code specifying a read operation. 3. The integrated circuit device of claim 2 wherein: the plurality of output drivers output the first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and the plurality of output drivers output a second portion of the data synchronously with respect to a falling edge transition of the external clock signal. 4. The integrated circuit device of claim 2 further including a delay lock loop, coupled to the plurality of output drivers, to synchronize the output of the first and second portions of the data with the external clock signal. ANALYSIS I. Obviousness – Bennett with Wicklund or Bowater, and Prior Art Admissions (APA) in the ‘446 Patent The Examiner determined that claims 1 and 2 are not obvious over Bennett and either Wicklund or Bowater. One central dispute on appeal Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 5 involves the recitation in claim 1 of a “synchronous integrated circuit device having . . . dynamic random access memory cells;” i.e., a DRAM chip, and the ability of the device to synchronously sample an operation code which includes precharge information. Claim 2 further includes a read request in the operation code. Bennett’s Teachings B1. Bennett’s “paramount object” is to provide communication between “very large scale integrated VLSI (circuit) elements” (col. 12, ll. 14-18) – i.e., “VLSIC chips” (col. 9, ll.35-40). Bennett discloses combining Versatile Bus Interfaces (VBI) and VLSIC “upon the same chip substrate as the VLSI User Device” (col. 12, ll. 29-32 (emphasis added)) with such a user device including “interfaces intended to be built with a CPU, IOC or Memory, or similar User device for signal or data exchange” (col. 35, ll. 59-61 (emphasis added)). (See also col. 14, ll. 19-24 (describing “interface to the user devices (usually upon the same chip substrate)”.) As another example demonstrating a preference for a single chip, Bennett states that “[e]ach Versatile Bus Interface Logics, for example Versatile Bus Interface Logics 102a [of Fig. 1], interfaces a User module, for example VLSI Circuit User Device 106a which is pictorially represented in shadow line within FIG. 1 as existing on the same VLSIC chip substrate as Versatile Bus Interface Logics 102a.” (Col. 36, ll. 19-24 (emphasis added).) Bennett’s chips have up to 120 pins as a practical limit. (Col. 9, ll. 60-61.) Bennett also discloses different memory types as “Fast Memory” or “Large Memory” with the memory having address widths of 16, 24, or Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 6 32, and one fast memory embodiment having 37 pins (col. 92, ll. 15-56; Fig. 32). One large memory has at least 16 pins to access 232 addresses by employing two 16-bit address words over successive clock cycles. (See col. 95, ll. 59-60; Fig. 36.) B2. Figure 38 shows “memories device” 3802c and 3802d connected to a “Versatile Bus.” (Col. 97, ll. 8-10.) In the next paragraph, Bennett refers to “VSLI chips hav[ing] access to all Versatile Bus lines and therefore, the Versatile Bus protocols.” (Id. at ll. 20-22.) Bennett elsewhere refers to “memory devices” including, but not limited to, a ROM: “Not all memory devices can perform all operations; for example, read only memory (ROM) cannot execute the write operations.” (Col. 90, l. 66 to col. 91, l. 2.) Bennett then refers to “[s]ample memory operations in the following paragraphs” (col. 90, ll. 4-5) and thereafter describes “relatively small fast memories, and . . . larger and relatively slower memories” (col. 92, ll. 13-14). Bennett also refers to “VLSIC chip devices” and in the next full sentence (under the “Section 4.1” heading) states that “[m]any, if not most, applications of VLSIC technology are likely to include memory devices.” (Col. 90, ll. 42-43.) Bennett generally discusses these chip devices as employing the interconnection protocol standards outlined generally in Section 3 and more specifically discusses memory devices in Section 4 of the ‘051 patent. (See id. at ll. 36-41.) For example, as discussed in Section 4 of Bennett, Figures 32 and 33 represent fast memory write operations using data on 16 pins and 16 other pins for arbitration and slave ID. (See col. 93, l.12 - col. 94, l. 56.) Figure 36 represents pin and timing for a write operation to a large memory Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 7 device with a 4315335 protocol “configuration.” (See col. 26, ll. 54-57.) Figures 25a-h, represent more generic slave device configurations as discussed in Section 3 of Bennett. (Col. 25, l. 58 to col. 26, l; see generally columns 81-88). B3. In addition to chips, Bennett also discusses memory cards in Section 2, “Description of the Prior Art” (see col. 5, l. 52 et seq.), and states that “the functionality of VLSIC chips is often similar to cards today” but that “VLSIC technology promises much higher performance than that of cards,” even though cards hold more memory and chips have higher development costs. (Col. 9, ll. 43-56.) In the following passage, Bennett discusses creating larger chips to accommodate a greater numbers of pins. (Col. 9, l. 66 to col. 10, l. 29.) B4. Bennett describes a “third physical objective” – the VBI (versatile bus interface) “should occupy a reasonable VLSI circuit substrate area” using fast and efficient CMOS technology as the preferred embodiment. (Col. 13, ll.18-23.) Typically, only about 20 VLSIC devices will be interconnected. As a “first logical object,” the VBI logics “should offer a fixed format, simply controlled, powerfully featured interface to the user devices (usually upon the same chip substrate)” yet with certain options for use. (Col. 14, ll. 20-30.) Bennett contemplates simple devices with “as few as three pins” (Bennett, col. 12, l. 61), or “pass[ing] but a single bit of data from a single master device to a single slave device . . . [or more bits and devices]. The versatility is from the trivial to the profound.” (Col. 15, ll. 26, 42-50.) Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 8 B5. Figures 25a-h show an ID/FUNCTION command, which includes a read or a write (see e.g. Fig. 35, 36).13 (See col. 85, l. 9 to col. 87, l. 6.). Figure 34 shows multiple functions in a memory write code: i.e., a read-modify-write code signifying multiple functions in a single code. B6. Bennett discloses synchronous clocked communication between bused VLSIC chips over 16 data lines at 25MHz, and notes that synchronous communication is more efficient than asynchronous communication. (Col. 13, ll. 3-17; col. 66, l. 9 – col 67, l.18; col. 101, ll. 50-54 (“all communication . . . is synchronously referenced”); col. 102, ll. 9-27.) Bennett also states that the clock signals “are normally synchronous.” (Col. 274, l. 62.) B7. Bennett employs a dual-phase clocking scheme. (See Fig. 84.) Bennett explains that the scheme employs a first phase to charge the capacitance on the bus. (Abstract.) To further explain the system, Bennett (col. 13, ll. 33-43; col. 105, ll. 50-61) points to, and incorporates by reference, App. No. 0355,803, which corresponds to Bennett at al., U.S. 4,500,988 (Feb. 19, 1985.) Bennett ‘988, in reciprocal fashion, mentions using its clocking scheme and corresponding driver circuitry in Bennett. (See, e.g., Bennett ‘988, col. 7, ll. 47-51 (referring to Bennett’s application number 356,051).) B8. Bennett ‘988 (col. 7, ll. 62-67) and Bennett (col. 277, ll. 30-33) each similarly explain that the dual-phases can have a 50% duty cycle and can be symmetrical. Bennett ‘988 explains that the dual phase scheme 13 Bennett also refers to functions as operations, which include read or write operations. (See col. 91, l. 62 to col. 92, l. 8; col. 91, ll. 43-53 (“functional operations”); Figs. 31, 35, 36.) Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 9 allows smaller interfacing transistors in separate devices to work together in a wired-OR fashion to pre-charge the bus. (Bennett ‘988, col. 6, ll. 47-51; col. 7, ll. 7-34; col. 8, ll. 57-63.) The bus is precharged to a high voltage level of 3 volts (corresponding to a logical 0) at the leading edge of phase (H) φ1, and then, if, and only if, any one of the data lines seek to represent a logical 1 data bit, that line/lines is/or driven to a low voltage at the leading edge of phase (H) φ2. (See Bennett’ 988, Fig. 5, col. 6, ll. 55-65; Bennett Fig. 84.) In other words, some data lines stay logical 0 as initiated by the leading clock edge of (H) φ1, and others change to logical 1 as initiated by the leading clock edge of (H) φ2. B9. Bennett ‘988 discloses that the dual clocks are both “distributed by a master clock.” (Bennett ‘988, col. 7, ll. 61-62.) B10. Bennett explains that faster operations are possible by “configured nonperformance of arbitration and slave identification/function or both.” (Col. 107, ll. 61-63.) Bennett compares “[u]nsophisticated User devices such as memories” to “sophisticated devices such as processors” – the latter do not know what other devices are on the network. (Col. 58, ll. 64-65.) As noted supra, Bennett contemplates simple systems having “a single slave memory.” (Col. 57, l. 57.) Bennett explains that “the number of [device] locations strongly affects complexity.” (Col. 8, ll. 30-31.) Bennett distinguishes between slaves and masters: slaves “only respond to information on the interconnect,” masters “control the interconnect”; thus, slaves are subordinate to masters. (Col. 8, ll. 30-41.) B11. Bennett projects speed increases – e.g., systems projected to “drive signals from chip to chip in 20 to 40 nanoseconds.” (Col. 9, ll. 58- 59.) Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 10 Discussion Rambus maintains that the Board should confirm the claims for the same reasons that the Examiner does. (Resp. Br. 2.)14 Micron shows (App. Br. 12-14; Reb. Br. 2-4) that the Examiner’s articulated reason; i.e., that the prior art teaches a precharge signal, but fails to suggest modifying Bennett’s operation code to include a precharge signal, is in error. (See RAN 70-76.) The ‘446 patent admits, and other portions of the record corroborate (see e.g., App. Br. 8, n.5 and discussion below), that in a normal read mode, a precharge signal normally follows a DRAM read signal. For example, the ‘446 patent describes known precharge operations as follows: In normal mode (in conventional DRAMS and in this invention), the DRAM column sense amps or latches have been precharged to a value intermediate between logical 0 and 1. This precharging allows access to a row in the RAM to begin as soon as the access request for either inputs (writes) or outputs (reads) is received and allows the column sense amps to sense data quickly. (‘446 patent, col. 10, ll. 18-24.) The patent further describes “typical;” i.e., known settings: “Typical settings are ‘precharge after normal access’ and ‘save after page mode 14 Rambus’s contention that Micron’s incorporation by reference to earlier reexamination documents is improper lacks merit. (See Resp. Br. 1-2.) Rambus similarly incorporates other documents, the record is large, and the briefs are limited by page size. (See Resp. Br. 1 n. 4; Resp. Br. 8 (relying on the Examiner’s findings in related proceedings but only citing Micron’s Brief); Reb. Br. 1.) As Micron points out, Micron need not raise arguments or present detailed findings listing claim elements, etc. or other issues and findings with which Micron and the Examiner agree. (See Reb. Br. 1.) Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 11 access’ but ‘precharge after page mode access’ or save after normal access’ are allowed.” (’446 patent, col. 10, ll. 43-46.)15 As to the operation code, Micron relies on Bennett’s “synchronous operation (FUNCTION) code of Figs. 31, 34),” and notes that the Examiner initially adopted the proposed rejection and did not alter the operation code finding. (See App. Br. 7 (citing the Examiner’s “8/7/09 OA at 98-99); accord B5, B7).)16 Hence, while the Examiner and Micron agree that Bennett discloses an operation code, the Examiner reasons that modifying it to include a precharge signal would not have been obvious: While the primary reference [Bennett] disclose[s] . . . an operation code that is sent synchronously with respect to an external clock signal, the rejection to the claims does not support a reason to include the precharge information with the same operation code. (RAN 69.) Contrary to the Examiner’s quoted rationale, Micron does provide persuasive reasons, for example, based on the above-quoted admissions in the ‘446 patent – i.e., that precharging “‘allows the column sense amps to sense data quickly.’” (App. Br. 8 (quoting the ‘446 patent).) Micron also points out that the “‘446 patent admits that 15 The Board addressed a similar issue in a related case: BPAI 2012-000142 (see original decision and rehearing decision). The findings and rationale there related to Bennett, Bowater and Wicklund are adopted and incorporated by reference. 16 The merged Office Action (OA) appears in the 95/001109 reexamination file and refers to Micron’s supplemental inter partes reexamination request (March 11, 2009) which appears in the 95/001155 reexamination file. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 12 both page mode and normal mode were known separately in the … art.” (App. Br. 8.) As Micron further reasons, “instead of leaving the row (page) of data in the sense amplifiers for a subsequent access as is done in page mode, a normal mode operation is followed by a precharge.” (App. Br. 8.) Rambus similarly describes the known operations, noting that “[p]recharging occurs when a row in the DRAM is closed” and that “[i]n asynchronous DRAMS, precharging is performed in response to a further instruction—when the /RAS signal is [deasserted] . . . at the end of a sequence of one or more accesses to data in a particular row.” (Resp. Br. 4; accord id. n.7 (“Once all accesses in a row are complete, the row is closed and precharging in preparation for the next access occurs.”).) As Micron also points out, Mr. Murphy, Rambus’s expert in this and other litigation, testified that “‘[t]he normal mode read is essentially equal to, or similar to a read with auto precharge.’” (App. Br. 8 (emphasis by Micron, quoting Hynix Trial Tr. at 434:2-11).) Hence, since it was well-known that a signal to precharge follows the normal mode read in prior art systems, it would have been obvious to include it with a normal mode read signal, as a modification to Bennett’s (FUNCTION) operation code, in order to eliminate sending another or redundant signal. Moreover, Bennett further suggests the modification by disclosing more than one function in a single operation code. (See B5 (read-modify-write function).) Since there is no reasonable dispute that a DRAM row in the prior art typically closes pursuant to a Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 13 precharge signal after the normal mode read signal, and Bennett discloses multiple signals in a single op code, closing the row automatically after performing the read in response to a single operation code would have been obvious so that the row would be ready for another normal mode read. Micron also relies on teachings in Wicklund and Bowater. (See App. Br. 9-11.) The teachings there are largely duplicative to what is known in the art. For example, Micron points out that “Wicklund describes the same goal identified in the ‘446 patent.” (App. Br. 9.) Rambus’s assertions, and the Examiner’s findings, directed to Wicklund’s and Bowater’s teachings, fail to account adequately for the rationale advanced by Micron based on the totality of the teachings including the ‘446 patent admissions. Micron buttresses its rationale by pointing out that Wicklund provides further reasons for closing a row and automatically precharging – to avoid the penalty of a page miss by accurately predicting page or normal mode accesses. (See App. Br. 9-11.) Micron reasons that Wicklund’s predictive system renders obvious automatically closing a DRAM row (i.e., precharging) after a previous read access. (See App. Br. 9-11.) Micron’s rationale, buttressed by the ‘446 patent admissions, is persuasive and supports the obviousness of sending a signal as part of Bennett’s synchronous op code. The modified system would have been more efficient by accurately predicting that the data would be on a different row on a subsequent access, thereby suggesting a row close (i.e., a precharge) on the current row prior to accessing the different row. (See App. Br. 11-12.) Rambus also maintains that Bennett does not disclose a synchronous memory device. (Resp. Br. 2-3.) Rambus similarly argues that Bennett's Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 14 operation codes “are provided to the VBI, not the DRAMs that Micron alleges.” (Id. at 4.) These related arguments reduce to the assertion that Bennett does not disclose a single chip memory device, because Bennett discloses memory boards, and Bennett does not disclose a DRAM. Bennett at least discloses a synchronous single chip memory device (B1-B6) and renders a synchronous DRAM chip obvious, where, for example, Wicklund describes DRAMs as “the most popular form of read/write memory” (col. 1, ll. 37-38) and Bennett discloses read/write memory devices, while noting that ROM chips do not perform writes (B4). Finally, the Board, and a District Court, has separately addressed similar arguments in related proceedings, and the findings and rationale there are adopted and incorporated herein by reference.17 Moreover, Rambus’s argument that Bennett’s memory device does not signify, to skilled artisans, a single memory chip, but rather, only 17 For example, see BPAI 2011-000142) (2012) (finding that “Bennett discloses synchronous memory chips” and concluding that employing a notoriously well-known DRAM memory chip in place of Bennett’s generic memory chip would have been obvious); BPAI 2011-009664 at 14-18 (2012) (finding that Bennett discloses a synchronous memory device chip concluding obviousness with respect to a similar issue involving claims directed to a read operation based, inter alia, on Bennett, Wicklund or Bowater); BPAI 2012-001638 at 3-22 (2012) (relying, in part, on a District Court December 15, 2008 Order Granting in Part and Denying in Part Rambus’s Motion to Strike; Denying Motion for Summary Judgment No. 1 of Invalidity; and Striking Motion for Summary Judgment No. 2 of Invalidity, Hynix Semiconductor Inc. v. Rambus Inc., No. 00-2905, Rambus Inc. v. Hynix Semiconductor Inc., No. 05-334, Rambus Inc. v. Samsung Electronics Co., Ltd., No 05-2298 RMW, and Rambus Inc. V. Micron Technology, Inc., No. 06-244 (N.D. Cal.) (stayed, Judge R. Whyte) (attached as Ex. O-3 to the Rambus’s respondent brief in the 2012-001638 reexamination). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 15 signifies a memory board (see Resp. Br. 4), contradicts other arguments made elsewhere before the PTO and related proceedings.18 Bennett’s disclosure of the same term, “memory device” (B2), references to “VLSIC upon the same chip substrate,” “interfaces intended to be built with . . . Memory,” (B1) and other similar references to VLSIC, chips or “same” substrates (B1-B4), combined with a limited discussion of memory cards as prior art (B3), all show that Bennett’s memory device includes a single chip embodiment (even if the term also signifies other memory forms of memory as Rambus argues). Micron’s similar reliance on the memory chip of Bennett’s Figure 1 and memory devices in Figure 38 bolsters the Examiner’s findings. (See Reb. Br. 3; accord B1, B2.) Rambus facially presents arguments with respect to claim 2, but the arguments do not differentiate in a meaningful manner from arguments regarding claim 1. (See Resp. Br. 7-8; accord Resp. Br. 1 (grouping claims 1 and 2 together).) For example, Rambus’s observation that “in addition to including precharge information, the operation code [in claim 2] specifies a read operation” facially requests the Board to decide that the combination does not disclose or suggest a read operation. (See Resp. Br. 7.) But Bennett’s system sends a read op code to memory devices as Micron points out. (See App. Br. 7, 12 (relying on the Bennett’s FUNCTION code as including a read and further relying on output drivers cited in Micron’s Request); B5.) 18 See In re Rambus, App. No. 2011-1247 (Fed. Cir. Aug. 17, 2012) (involving an appeal of BPAI 2010-0011178- the Board and the Federal Circuit holding that the term “memory device” includes, but is not limited to, a single chip contrary to Rambus’s arguments otherwise). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 16 Based on this record, Micron persuasively demonstrates that the Examiner erred in failing to maintain the rejection of claims 1 and 2 based on Bennett, APA, and Wicklund or Bowater. II. Obviousness – Bennett, APA, Wicklund, and Inagaki or Novak Claim 3 depends from claim 2, and requires outputting data synchronously with respect to rising and falling edges of a clock pulse. The Examiner relies on reasons for confirming claims 1 and 2. (See RAN 70, 77.) Rambus presents additional reasons for supporting the Examiner’s decision to confirm claim 3. (See Resp. Br. 8-9.) For example, Rambus points to the Examiner’s reasoning about Bennett’s clock system in a related reexamination proceeding in which the (same) Examiner confirms a claim which is similar to claim 3 here. (See Resp. Br. 8.) Micron’s responses, which rely on the secondary teachings of Inagaki or Novak, show the obviousness of employing rising and falling edges to input or output data, as discussed further below. (See App. Br. 12-15.) Inagaki’s Teachings I1. Inagaki discloses a method for increasing data rates in block access memory. As background, Inagaki teaches that conventional methods to increase data transfer rates in RAMs involved increasing the data bus width, which adds cost of packaging and pin count, or to increase the clock rate. (Inagaki 2.) Inagaki’s solution is to use dual edges of a clock as quoted as follows. I2. “The rise and fall of external clock φ are detected, and clocks φ1 and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the shift Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 17 register. . . . In this way, since one bit is output on each half-cycle, the operating speed is twice that of the conventional speed.” (Id. at 4.) I3 “[T]he present invention presents block access memory that transfers data with a speed that is twice the conventional speed, by performing I/O [input/output] of data on every half-cycle of the external clock that drives the I/O shift register.” (Id. at 3.) Discussion Rambus maintains that using Inagaki’s clocking scheme in Bennett would not have been obvious for various reasons. Rambus initially maintains that Inagaki uses pulses and not a periodic clock. (Resp. Br. 9.) Rambus makes a similar contention about Novak, asserting that an asynchronous device does not have an external clock. (See id.) But Inagaki refers to an “external clock” repeatedly and the clock is periodic at least while it operates: “The rise and fall of external clock φ are detected, and clocks φ1 and φ2 are generated. . . . . In this way, since one bit is output on each half-cycle, the operating speed is twice that of the conventional speed.” (Inagaki at 4 (emphasis added.) Inagaki’s system performs “data input or output every half-cycle based on an external clock.” (Id. at 2.) Inagaki’s numerous computer clock references point skilled artisans to and embrace the well-known computer clock – in other words, the same type of external computer clock generically claimed in the ‘446 patent.19 See In re Paulson, 30 F.3d 1475, 1480-81 (Fed. Cir. 1994) 19 clock . . . A source of accurately timed pulses, used for synchronization in a digital computer . . . .” McGraw-Hill Dictionary of Scientific and Technical Terms 387 (Fifth Ed. 1994). This reference indicates that clock signals and clock pulses are the same: i.e., “clock signals. See Clock Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 18 (“a prior art reference must be ‘considered together with the knowledge of one of ordinary skill in the pertinent art’,” and where the skill level was “‘quite advanced’ . . . ‘one of ordinary skill certainly was capable of providing the circuitry necessary to make the device operable for use as a computer’”) (citations omitted). Also, Bennett employs different periodic external clocks (see B6; Bennett Fig. 84; Abstract) and Rambus’s arguments amount to an unpersuasive separate attack on the references. Micron relies on the combination to suggest using the rising and falling edges of a clock. Micron adds that Inagaki teaches using dual edges of a single clock in order to increase speed or reduce the number of data pins or paths in a memory device. Micron relies on similar teachings in Novak. (See App. Br. 12; I1- I3; Novak, col. 6, ll. 34-35; 4f, 4d (“for read operations it takes only 128 cycles of the clock φ to output 256 bits”.)20 Rambus also maintains that Bennett discloses an “intricate clocking scheme” (Resp. Br. 9) which precludes the proposed modification of employing leading and falling clocking edges because such a modification would destroy Bennett’s principle of operation and would lack any reasonable expectation of success. (Id. at 8-9.) The Federal Circuit recently pulses.” Id. “[C]lock pulses. . . . Electronic pulses which are emitted periodically, usually by a crystal device, to synchronize the operation of circuits in a computer. Also known as clock signals.” Id. 20 Several previous Board decisions reasoned that Inagaki discloses a clock and using dual edges therefore. See, e.g. BPAI 2012-000171 (finding obviousness with respect to combining Inagaki with a prior art reference using a dual clocking scheme). The findings and rationale involving Inagaki are adopted and incorporated by reference. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 19 rejected a similar argument under analogous circumstances based on the observation that an asserted “difference does not affect the operability of Mouttet’s [i.e., the applicant’s] broadly claimed device—a programmable arithmetic processor.” In re Mouttet, 686 F.3d 1322,1332 (Fed. Cir. 2012) (citations omitted) (also reasoning that physical incorporation is not required to support obviousness). The principle of operation of the broadly claimed memory device here involves synchronously outputting data from a memory device on both clock edges of the clock. Bennett’s principle involves “its high level ability to,” see Mouttet at 1332, transfer data synchronously (B6) to and from a single memory device or a group of such devices, using a “simply controlled,” yet versatile, system (B4, accord B10 (“single slave device”)). For example, Bennett’s system is “configured so simply as to pass but a single bit of data from a single master device to a single slave device, or with ten deep pipelining of eight phases of time-based arbitration (between 256 devices) time overlapped with slave identification/function . . . . The versatility is from the trivial to the profound.” (Col. 15, ll. 42-50 (emphasis added); accord B4.) Using one or two external clocks does not undermine this broad principle of versatile data transfer and coalesces with the broad principle underlying claim 3. Moreover, Bennett’s dual clocking scheme mainly serves to precharge the bus lines. (B8.) Such a scheme is not required to read data from a single device and is not required to satisfy claim 3. For example, Bennett points out that the precharging scheme allows for reduced interface transistor sizes which are used to drive the bus in a wired-OR fashion – i.e., used to with multiple slave devices. (See B8.) As such, Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 20 skilled artisans would have recognized the pre-charging scheme would not be required for simpler systems such as Bennett’s single slave memory chip (see B11) since a large interface transistor and a single clock scheme could be employed to drive a handful of chips - as Inagaki teaches and Bennett suggests. Even if Bennett suggests that precharging is required or advantageous as implemented on the leading edge of phase (H) φ1, the second falling transition of phase (H) φ1 could be employed to change other portions of the data to a low voltage value as Inagaki suggests - instead of the leading edge of phase (H) φ2 as Bennett discloses in the Figure 84 embodiment. (See B8.) Bennett’s system further suggests, if not discloses, changing other portions of data on the trailing (H) φ1 edge because the trailing (H) φ1 edge coincides with the leading (H) φ2 edge in Bennett’s 50% duty cycle option. (See B7, B8.) Rambus’s arguments vaguely refer to corrupted data, but the arguments strike down a straw man and address another hypothetical modification in which both edges of H (φ1) are used to pull the data lines to a high voltage. Such arguments do not explain how the simple modifications described here would render Bennett inoperable. (See Resp. Br. 8.) Rambus’s arguments appear to be based on the false premise that Bennett does not contemplate symmetrical (50 % duty cycle) (H) φ1 and (H) φ2 wave forms. Bennett’s 50 % duty cycle option essentially teaches or at least suggests that the leading edge of one clock phase coincides with the falling edge of the other – Inagaki’s internal clocks overlap in the same fashion. (Compare B7, B8 and Bennett’s Figure 84 with Inagaki Fig. 4.) Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 21 In other words, Bennett’s principle of transferring data “is not unique to its . . . [specific dual clocking] operation” as disclosed in the Figure 84 embodiment. See Mouttet at 1332. As also noted, Bennett’s scheme envisions “trivial” schemes, including those embraced by the broad reach of claim 3, which requires reading data synchronously from a single memory chip using the dual edges of a clock as Inagaki or Novak suggest. (See B4, B10.) Bennett also describes the clocking scheme as merely “a preferred embodiment of the invention,” and indicates that “the electrical timing is capable of being altered.” (See Bennett, col. 277, ll. 24-26.)21 Rambus has not demonstrated that skilled artisans, motivated by Inagaki’s or Novak’s teaching of using rising and falling clock edges for increasing data transfer speed from known DRAM memory devices, would have been unable to modify Bennett’s system to arrive at the broadly claimed invention. Inagaki’s or Novak’s dual clocking scheme provides the fastest possible signal transfer on a bus without increasing the pin count or data path width, thereby providing the motivation for the modification. (See I1-I3; Novak, col. 6, ll. 34-35 Fig. 4f, 4d.) Inagaki and Novak provide evidence of a reasonable expectation of success in using dual clock edges on data for increased speed, especially for “trivial” systems using a single or a handful of memory devices, as Bennett teaches. Increased speed and compactness by reducing bus width and corresponding pin number while saving cost (see I1) constitute universal 21 While the full passage implies altering the duty cycle of both clocks, skilled artisans would have recognized that simple single memory device systems as claimed would not require two clocks as Inagaki and Novak make clear and as discussed supra. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 22 motivators. Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) (“[A]n implicit motivation to combine exists … when the ‘improvement’ is technology- independent and the combination of references results in a product or process that is more desirable, for example because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.”) Also, “if a technique has been used to improve one device, and a person of ordinary skill would recognize that it would improve similar devices in the same way, using the technique is obvious unless its application is beyond his or her skill.’” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007)(citation omitted). Despite Rambus’s related arguments that Micron has not shown how to modify Bennett’s two phase system (see Resp. Br. 8-9), Rambus has not shown that the proposed modification would have been beyond the skill of an ordinary artisan, and the Court has also recognized that “the interaction of multiple components means that changing one component often requires the others to be modified as well.” KSR, 550 U.S. at 424. In other words, as KSR implies, making other required modifications to increase the data speed by using both clock edges, as Inagaki or Novak, does not defeat obviousness or show inoperability. Further, Mr. Murphy states that the clocking scheme was “often referred to as ‘dual edge clocking’ and allows for data transfer at twice the rate of the external clock signal.” (Murphy Dec ¶ 26) (filed May 13, 2009 in the 95/001109 reexamination proceeding).) Mr. Murphy also explains that “[o]ne of ordinary skill in the art would understand a synchronous bus, by its very nature, relies on a clock, but the way that clock is distributed in the Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 23 system need not be limited to any particular distribution scheme.” (Id. at ¶ 39.) Mr. Murphy’s testimony indicates that skilled artisans knew how to implement what was often referred to as “dual edge clocking” to double the data rate and knew how to apply different clocking schemes to clocked systems like Bennett’s synchronous clocking scheme. Given the claim breadth and high level of ability involved, skilled artisans easily could have modified Bennett’s system in view of Inagaki’s or Novak’s clocking scheme to create a cleaner system, dropping any unneeded functions in a single device memory system (e.g., arbitration signals, etc.), where Bennett’s system provides broad flexibility and versatility. Such a “cleaner” memory device to handle single direction data transfers as embraced by broad claim 3 constitutes a universal motivator under Dystar. Also, Rambus’s reliance on Bennett’s Figure 84 to show that Bennett requires a two phase intricate clocking system (see Resp. Br. 8) improperly assumes that any structure implied by the example of Figure 84 must be physically combinable with a known dual clocking structure – a proposition Mouttet and other cases refute. See also In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983) (“[I]t is not necessary that the inventions of the references be physically combinable to render obvious the invention under review.”); In re Nievelt, 482 F.2d 965, 968 (CCPA 1973) (“Combining the teachings of references does not involve an ability to combine their specific structures”). Assuming for the sake of argument that such a physical combination is required to show obviousness, skilled artisans would have recognized that Bennett’s Figure 84 system could have been modified as discussed above, or under another alternative, to include the dual edges of slower external Inagaki or Novak clocks as triggers for the leading edges of the faster clocks Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 24 φ1 and φ2 represented in Figure 84. That is, in Inagaki (see Fig. 4), a slower external clock φ has rising and falling dual edges corresponding to and triggering single leading edges of faster clocks φ1 and φ2 , suggesting a similar external clock to trigger the fast clocks in Bennett. (See e.g. Inagaki Fig. 4; I3.)22 Bennett employs multiple clocks, as does Inagaki, rendering such a combination obvious. Still further, Bennett ‘988 discloses that Bennett’s dual clocks are both “distributed by a master clock.” (Bennett‘988, col. 7, ll. 60-61.) The ‘446 patent similarly discloses “clocking at half the bus cycle data rate.” (See col. 19, ll. 33-45 (describing the 500 MHz bus as using a 250MHz clock).) Also, the thrust of Rambus’s arguments are not commensurate in scope with claim 3, which does not require the “intricate clocking system” (Resp. Br. 8) of Bennett. As discussed, claim 3 broadly embraces a memory device which outputs one-way data synchronously. The record indicates the structural features of claim 3, including sense amplifiers, input receivers, and output drivers, constitute well-known components of typical DRAM memory devices at the time of the invention. (See e.g., ‘446 patent, Fig. 15; col. 23, ll. 43-65 (describing a “conventional 4 Mbit DRAM” and explaining that “[m]any of these details have been implemented selectively in certain fast memory devices”); accord Micron’s Request 35 (relying on such known admitted DRAM features).) Rambus has not demonstrated that skilled artisans, motivated by the known use of rising and falling clock edges to 22 Bennett also discloses varying the duty cycles of the two clocks as noted above so that the clocks would coincide just as Inagaki’s clocks do. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 25 increase data output speed from known DRAM memory devices on a single bus, would not have been able to arrive at the broadly claimed invention.23 Based on the foregoing discussion, Micron has shown that the Examiner erred in not maintaining the rejection of claim 3 based on Bennett, APA, Wicklund, and Inagaki or Novak. III. Obviousness Based on Bennett, Wicklund, and Lofgren or Bazes With respect to claim 4, Rambus argues that Bazes and Lofgren do not cure asserted deficiencies in the rejection of claim 1. (Resp. Br. 9-10). The Examiner relies on reasons with respect to claim 1 for not rejecting the claims – primarily the asserted lack of a teaching or suggestion for an automatic precharge signal. (See RAN 71-72, 78-84.) 23 In a related hearing before the Board on September 12, 2012 (see hearing transcript in BPAI 2012-002081 & 2012-001976 (argued together)), Rambus raised a new argument premised on the Federal Circuit’s recent decision in In re Rambus, App. No. 2011-1247 (Fed. Cir. Aug. 17, 2012) (cited supra). Rambus argued that In re Rambus precludes Bennett’s interface because it is akin to a complicated processor such as a BIU which the Federal Circuit reasoned was not included in the term “memory device.” To the contrary, Rambus itself distinguishes masters from slaves, as the Federal Circuit’s reasoning points out. See id. at 6. In re Rambus only precludes “a global bus controller or CPU,” id. at 7, but it does not preclude Bennett’s single chip slave devices which merely respond to master bus processor controllers. Bennett also teaches that any device functionality can be disabled to increase speed and distinguishes such “unsophisticated” slave memory devices from “sophisticated” processor master controller devices. (See B4, B10.) As such, assuming arguendo Bennett’s chip interface has too much control, it would have been obvious to eliminate unneeded functions in the chip interface for the simple single memory chip at issue here. See In re Sovish, 769 F.2d 738, 743 (Fed. Cir. 1985) (“This argument presumes stupidity rather than skill.”). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 26 For reasons explained supra, that contention is not persuasive. With respect to the added limitation in claim 4, Micron persuasively shows that delay lock loops (DLLs) were standard in the art prior to the invention. For example, Micron explains that Bazes teaches that for “‘integrated circuit memories.’” including “‘dynamic, random-access memories, many clock signals are required for each memory cycle to latch addresses, decode the addresses, access the array, precharge nodes, control refreshing, etc.’” (App. Br. 15 (quoting Bazes at col. 1, ll. 11-16).) Micron points out that Bazes also teaches “‘generating these signals ‘on-chip’” using a “‘precision synchronous delay line.’” (App. Br.15 (quoting and citing Bazes at col. 1, ll. 17-19; col. 2, ll. 21-23.) Bazes also teaches that such a “synchronized delay line” is “insensitive to voltage changes, temperature changes and wafer processing variations. It is ideally suited for providing on-chip timing signals derived from a reference clock for MOS integrated circuits.” (Abstract.) As Micron also reasons, Bazes states that providing a DLL on- chip obviates the need for high precision external clocks. (See App. Br. 15- 16; (citing Baze at col. 1, ll. 17-19).) Rambus disputes Micron’s statement that “‘as demonstrated in Micron’s reexamination request, it was known in the prior art to utilize a DLL on a memory chip.’” (Resp. Br. 10 (citing and relying on “03/26/10 OA [office action] in [related] control no. 90/010,420 at 29-36”).) The examiner in that ‘420 case finds, inter alia, that Lofgren does not disclose an external clock signal for controlling the DLL and that Lofgren and the iAPX Manual only suggests that “precise delays are for controlling data to the memory” – i.e., controlling data from the iAPX MCU controller module to Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 27 DRAM chips and involving control of RAS and CAS control signals to memory arrays. (See the ‘420 OA at 32 (emphasis added).) But here, Bennett involves a single chip memory so that any distinctions between control to and from a memory device do not flow from the examiner’s logic in the ‘420 case. Thus, Rambus’s reliance on the ‘420 reexamination is misplaced. Here, more importantly, the Examiner initially adopted the proposed rejections but subsequently refused to maintain them based on asserted deficiencies in claim 1 with respect to Wicklund’s precharge teachings. (See App. Br. 16 (relying on the Examiner’s ‘155 “8/7/09 OA at 100.”) Further, the Examiner made a supportive finding in another reexamination that culminated in an appeal to the Board, whereas the Examiner’s findings in the ‘420 reexamination were not at issue in an appeal of that reexamination.24 As indicated, the Examiner recently found that combining Lofgren and the iAPX system would have been obvious with Lofgren essentially teaching an accurate timer using a delay line. The Board, relying on the Examiner’s findings, including the finding that Rambus essentially equated phase-locked loops and delay- locked loops, agreed with the examiner that combining Lofgren with the iAPX Manual (also at issue in the ‘420 reexamination) would have been obvious. (See BPAI 2011-008431 at 30-31.) The prior ‘8431 Board decision and reasoning related to Lofgren is adopted and incorporated herein by reference. 24 The ‘420 reexamination appeal culminated in In re Rambus Inc., 2011-1247, (Fed. Cir. Aug. 18, 2012) (holding that the claimed memory device is not limited to a single chip so that the iAPX Manual anticipates the sole claim at issue there). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 28 Micron’s Inter Partes Request further explains that Bennett receives external clock signals and generates internal clock signals “on the device including when the Driver/Receiver (output driver) circuitry elements output data.” (Micron’s Request 52 (citing Bennett, col. 274, ll. 59-67; col. 267, ll. 13-16).) Micron also explains, inter alia, that Bazes teaches generating precision clocking as necessary for integrated memories and that a delay loop overcomes known problems in timing due to wafer processing, supply voltage variations, and operating temperature. (Micron’s Request 53.) Micron reasons that it would have been obvious to employ a delay lock loop “in order to address the known prior art timing problems.” (Id.) Micron presents similar rationale with respect to Lofgren. (See id. at 44, 54-55.) Micron also explains that Bennett discloses internal delays on the memory chip – i.e., “the internal clocks are distributed throughout the device.” (Id. at 44.) Rambus fails to rebut Micron’s contentions with persuasive evidence or reasoning. (See Resp. Br. 9-10.) While Rambus asserts that Micron does not explain how the DLL would be implemented with Bennett’s timing scheme, Micron’s explanation shows that, on this record, since Bennett discloses internal clock delays implemented with that scheme, providing a DLL to better control the internal timing synchronization and account for wafer process variations would have been obvious. Moreover, as explained above, contrary to Rambus’s arguments which attack the references separately and allege that Micron has not shown how to incorporate a DLL with Bennett’s dual clocking scheme (see Resp. Br. 10), under Mouttet and other cited cases supra, the prior art references need not be physically combined to support obviousness. Rambus’s assertions about complexity Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 29 and cost simply show that trade-offs existed in adding circuitry to chips, but Rambus does not show that skilled artisans, motivated by providing precision timing on wafers as the DLL teachings provide, would have been unable to overcome any cost or complexity as required to add the known DLL circuits to known DRAM devices. Based on this record, Micron has shown that the Examiner erred in failing to maintain the rejection based on Bennett, APA, Wicklund, and Lofgren or Bazes. IV. Obviousness Based on Moussouris, SCI-A, APA, SCI-B, and either Wicklund, Bowater, or Olson Public Dissemination The record supports the Examiner’s finding that SCI-A (by Gustavson et al., see note 10 supra) was probably publicly disseminated and that SCI-B (by Schanke et al., see note 5 supra) was not. (See RAN 60-62.) As to SCI-A, it appears that a previous district court judge found the document to have been publicly disseminated based partially on at least one witness who participated as one of the authors of the document. (See Hynix Trial Tr. 1254:12-13.)25 As the Examiner also finds, SCI-A was also listed on another SCI document which was published by a group of authors at a European Conference, further corroborating its dissemination. (RAN 60 25 Hynix et al. v. Rambus, Inc., C-00-20905 RMW (Cal. D. Ct. Mar. 27, 2006) (Transcript of Proceedings before Judge R. Whyte) (10 page partial submission in the 95/001,109 reexamination proceeding, filed June 12, 2009 as document 238, Ex. D, in the PTO EDAN computer system). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 30 (citing the Kristiansen et al. publication).)26 It appears that another (unnamed) witness, apparently another author of SCI-A, testified that he was “quite certain” that some version of SCI-A was “sent out probably more than once to people on the mailing list.” (Hynix Trial Tr. 1297:6-10.) With respect to SCI-B, Micron contends that testimony regarding SCI-A shows standard operation practices and thereby shows that all SCI documents, including SCI-B, more likely than not were disseminated. But Micron’s evidence does not support this contention. (See App. Br. 19- 20.) The record indicates that one witness, Moussouris, an author listed on SCI-A, relied partly on the distribution mailing list which appeared to have been attached to the SCI-A document at some point in time after the date appearing on the document. Moussouris testifies to the effect that the mailing list (“I notice that the date on this . . . . [on] this mailing list at the end is November 23rd”) corroborates his understanding first that SCI-A “may have been” (Hynix Trial Tr. 1239:16-17) mailed, and later that he was “quite certain it was” mailed (id. at 1240:10) sometime after the listed August 1988 date. The other (unnamed) author discussed supra also testifies about the mailing list and responds to the effect that the August 22, 1989 date corresponds to about the time the witness participated in writing the document. (See Hynix Trial Tr. 1239:6-22.) But no such corroborating mailing list is asserted with respect to the SCI-B document as the Examiner finds. While Micron argues that the 26 As the Examiner finds, the Kristiansen article, i.e., Kristiansen et al., n.1, Scalable Coherent Interface, European Conf. Proc. (May 10, 1989), cites Gustavson et al., The Scalable Coherent Interface Project (SuperBus), Draft (Aug. 22, 1988); i.e., Kristiansen et al. cites the SCI-A document, see note 10 supra. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 31 evidence shows that the SCI committee was meeting “two or three times a month,” the citation to the Hynix trial transcript does not support the contention. (See App. Br. 19 (citing Hynix Trial Transcript at 1240:7-10).) Micron apparently relies on the testimony that “‘periodically there were meetings and there were mailings done at the time of the meetings.’” (See App. Br. 19 (quoting Hynix Trial Tr. at 1239:24-25).) But this statement, and other statements appearing in the proffered 10 page Hynix transcript record (supra note 23), do not specifically state how often meetings were held or which documents were mailed. No adequate explanation appears as to the standard procedure behind the date nomenclatures appearing on the SCI documents, e.g., the SCI-A document (“SCI-22Aug88-doc1”) or the SCI-B document (“SCI-5May89-doc77”). The testimony shows that the date does not necessarily correspond to a publication date because, according to Moussouris, the SCI-A document was probably mailed sometime after the listed August 1988 date. (See Hynix Trial Tr. 1239:18-19 (“there may have been a delay of some couple of months).) Micron does not establish what the date nomenclature typically signifies or otherwise show that the date signifies a mailing. In an attempt at corroboration, Micron argues that another article by Gustavson, an SCI member, corroborates the SCI-B dissemination. (See App. Br. 20.) But that article only shows that members of the project may have been aware of using dual edges of a clock and a phase locked loop in November 1988, but it does not show that any such awareness stemmed from reading the SCI-B document as Micron contends. (See App. Br. 20.) In other words, the Gustavson article, presented orally at a November 9-11, 1988 conference according to Micron (see id.), shows a Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 32 date prior to the May 1989 date associated with SCI-B. As a matter of simple timing and logic, the earlier (November 1988) Gustavson article cannot not show what the SCI members knew as a result of a later (May 1989) SCI-B document. As such, the evidence does not corroborate the dissemination of SCI-B. Based on the foregoing discussion, Micron’s reliance on Constant v. Advanced Micro-Devices, Inc., 848 F.2d 1560, 1568-69 (Fed. Cir. 1988) is misplaced. (See App. Br. 19-20.) In Constant, the court cited “extensive and uncontroverted evidence of business practice.” The evidence presented here is much more limited. Constant, 848 F.2d at 1569, relies on In re Hall, 781 F.2d 897 (CAFC 1986) for the proposition that evidence of routine business practice can show dissemination. But in Hall, the “affidavits give a rather general library procedure as to indexing, cataloging, and shelving theses.” Id. at 899. Micron’s evidence falls short of showing the general practice associated with the SCI dates, e.g., the “SCI-5May89-doc77” nomenclature appearing on the SCI-B document. See also in re Lister, 583 F.3d 1307, 1317 (Fed. Cir. 2009) (copyright date on manuscript in Copyright Office insufficient as prima facie evidence of public dissemination where Copyright Office’s automated catalog only allowed searching by author’s name or first word in title, and there was no evidence of when the document was listed in a keyword searchable data base). Rambus’s contention that “Micron did not establish that Moussouris is a printed publication” lacks merit. Rambus does not appear to contest the Examiner’s finding that at least one version of the document, relied upon by the Examiner, was part of a published “Computer Letter” having “Vol. 54, Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 33 No. 25” listed thereon. (Compare Reb. Br. 10 and RAN 61, n.1, with Resp. Br. 11.) Moussouris and SCI-A Teachings Moussouris describes how “standard interfaces provided by chip vendors have improved in bandwidth incredibly slowly relative to the underlying transistor improvements.” (Moussouris 2.) Moussouris explains that the market created a bandwidth gap in “DRAM density” versus DRAM bandwidth, and that “[t]here’s no technical reason for this.” (Id.) Moussouris then describes “a new standard . . . based on extremely fast signaling technology,” implemented by “an IEEE working group called P1596,” and notes that “if you . . . applied it to a 40-pin, surface mount RAM package, you would exactly close this [DRAM bandwidth] gap.” (Id. at 2.) Moussouris refers to the technology as “Scalable Coherent Interface”- i.e., SCI. (Id.)27 Moussouris further explains that “chip interfaces could be just the P1596 style interfaces, and with 32 megabytes of memory on each chip, there would be adequate bandwidth to connect together a few hundred like this. So nothing very exotic is required for this to happen.” (Moussouris 3.) Moussouris and lists a 500MHz speed and refers to “fast RAMS.” (Moussouris 3, slides.) SCI-A discloses packets for a typical SCI read operation from a memory. (SCI-A at 7.) “While the memory is looking for data, SCI is freed for other operations.” (Id.) SCI-A states that “[w]e are still working on error handling and initializations” but “block parity checking is currently assumed.” (Id. at 8, 14.) “SCI provides synchronization mechanisms . . . in 27 One set of presentation slides attached to the Moussouris article refers to “Scalable Coherent Interface (IEEE P1596)” and 500Mhz speeds. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 34 a multiprocessor system.” (Id.) Figures 14 and 15 show proposed node schemes and a corresponding packet data format. Figure 14 and an earlier discussion of “any real system,” indicates that a system clock and strobe perform synchronized communication, even though the “the phase of this clock with respect to data strobes will vary from place to place.” (See id. at 12.) Obviousness The Examiner reasons that the combination involving Moussouris, SCI-A, APA, and Wicklund, Bowater or Olson, does not support the rejection because “the Request . . . did not provide an obviousness type of support for this combination.” (See RAN 64.) Micron’s Inter Partes Request points out, inter alia, that Moussouris discloses the use of SCI signaling technology on a RAM to improve the DRAM bandwidth, and it relies on SCI-A to disclose using an external clock system and synchronous communication. (See Micron Request 22.) Micron’s Brief relies on this and similar rationale to support obviousness. (See App. Br. 20.) The Examiner appears to agree to a certain extent: “The Examiner agrees that one of ordinary skill in the art, after reading Moussouris, would look to Gustavson (SCI-A), however the Examiner was pointing out that SCI in Moussouris is not shown to be the same as SCI in Gustavson.” (RAN 64.) As Micron points out, skilled artisans would have looked to published SCI documents dealing with related technology based on the Moussouris reference to SCI (and the P1596 working group) and specifically, references to that scalable interface technology to improve DRAMs. (See App. Br. 20-21; Reb. Br. 11.) Further, Moussouris provides motivation for such DRAM interfaces in terms of increased speed – up to Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 35 “five hundred million transfers per second” – i.e., 500MHz. (Moussouris at 2.) Rambus maintains that SCI-A and Moussouris are non-enabling as lacking sufficient detail and as being general and forward-looking “works- in-progress.” (See Resp. Br. 11-12) But these references are presumptively enabling for what they teach and such references can be considered under obviousness independent of whether they are enabling or describe an operable device. See In re Antor Media Corporation, _F.3d__, WL 3055928, slip op. at *5, 6, 7-9 (Fed. Cir. July, 2012) (also stating that any “forward-looking language” does not address undue experimentation involved in the enablement query, addressing enablement in terms of the claim scope, and quoting Beckman Instruments, Inc. v. LKB Produkter AB, 892 F.2d 1547, 1551 (Fed.Cir.1989) (“Even if a reference discloses an inoperative device, it is prior art for all that it teaches.”)); see also In re Paulsen, 30 F.3d 1475, 1480-81 (Fed. Cir. 1994) (enabling references need not describe computer circuit details where highly skilled artisans could have provided such circuitry). As Micron contends, Rambus does not set forth which one of the claim elements are not enabled. Rambus has not demonstrated that any undue experimentation would have been required to modify a known DRAM to render it synchronous – according to the combined teachings of Moussouris, APA, and SCI-A. (See Reb. Br. 10-11.) As Micron also points out, Moussouris indicates that using a synchronous interface system in a DRAM would improve the bandwidth and speed. Bennett constitutes evidence that skilled artisans knew how to provide synchronous single chip memory devices. The record here, including expert opinion evidence, the Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 36 references, and other secondary evidence, shows that the skill level involved was quite advanced and the ‘446 patent itself is somewhat conceptual in detail as Micron notes. (See Reb. Br. 10.) As indicated supra, Moussouris describes what occurs in the SCI system, and the SCI-A document pertains to part of that description. Moussouris proposes a solution which involves putting SCI standard interfaces on standard memory chips, which includes DRAMs, to improve the bandwidth thereof as necessary to keep pace with the DRAM memory density. The SCI-A document shows that SCI standard interfaces operated synchronously. Because, according to Moussouris, “nothing very exotic is required for this to happen” and the DRAM bandwidth to density gap was not due to technical reasons, Rambus’s generic enablement contentions, lacking in specific detail as to specific claim elements, and lacking any showing of undue experimentation, are not supported. Rambus’s similarly general contention that Micron failed to identify how the “combination meets all the claim limitations and makes the combination obvious” lacks sufficient specificity. (See Resp. Br. 12.) The record reflects at the least, that Micron’s Request, including detailed claim charts, the Appeal Brief, the Rebuttal Brief, and the Examiner’s findings, constitute a prima facie case of obviousness. For example, contrary to Rambus’s assertions, Micron explains how Bennett, SCI-A, Wicklund, Bowater, or Olson, support the obviousness of a precharge signal in an operation code. SCI-A discloses operation codes and Wicklund’s system determines whether to switch between page-mode and non-page mode, which amounts to a decision to precharge or not. (See Request 16-18, 22- 34.) As is the case with the Bennett-based rejection, Micron also Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 37 persuasively relies on admissions in the ‘446 patent to show that precharging was known and followed normal read requests, thereby bolstering obviousness. (See, e.g., Micron Request 24.) Micron’s responses countering Rambus’s contentions are persuasive. The Examiner’s main reason for not maintaining the rejection appears to be that Micron did not propose a proper obviousness rejection and only attempted to “incorporate [the] SCI-A teaching into Moussouris.” (See RAN 63.) Based on the foregoing discussion, Micron shows error in the Examiner’s decision not to maintain Micron’s proposed obviousness rejection of claims 1-2 based on Moussouris as combined with the above- listed prior art. Micron does not show error in the Examiner’s decision not to maintain the obviousness rejection of claims 3-4 based on the added teachings of SCI-B. V. Priority (relative to the JEDEC and Park references) Micron asserts that since claims 1-4 do not recite a multiplexed bus and that claim 4 recites a delay lock loop (DLL), the claims are not originally supported back to the (first-filed) ‘898 application having a filing date of April, 1990. The first contention is that the claims are too broad; i.e., too broad absent a recitation to a multiplexed bus which the ‘446 patent touts as important. The second contention is that the original ‘898 application does not adequately describe a DLL. (See App. Br. 21-34.) Based on these contentions, Micron asserts that the claims are not entitled to a filing date prior to the ‘446 patent’s application filing date of December 21, 2001, and are therefore anticipated by the JEDEC and Park references which antedate the 2000 date. (See App. Br. 21, 34.) Rambus’s procedural attack, asserting that Micron does not have standing to argue Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 38 rejections raised by requester Samsung (Resp. Br. 11-12), has been addressed in repeated petition decisions, including one in this proceeding, which decided against Rambus as Micron and Rambus point out. (See Reb. Br. 11-12; Resp. Br. 13, n. 10; Pet. Dec. (June 17, 2011).) Prior decisions of the Board have relied upon one or more of these petition decisions. See, e.g., BPAI 2012-000168. Essentially, Micron’s appeal is an appeal of the Examiner’s decision and Micron has standing to argue rejections adverse to its position where the Examiner has addressed those rejections in the RAN. Rambus’s assertion that the Examiner improperly determined a written description instead of a priority issue lacks merit. (See App. Br. 13.) The Examiner determined priority and the Office has authority to determine such issues. A. The Multiplex Bus Rambus relies, inter alia, on Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1094-95 (Fed. Cir. 2003) to show that the claims do not require a multiplex bus and are therefore originally supported. (Resp. Br. 13.) The Examiner agrees with Rambus that the claims are originally supported. (See RAN 9-21 (incorporating by reference previous office actions).) The Board’s related decisions, BPAI App. Nos. 2012-000142, 2012-000168, and 2012-000169, address the same or similar issue between the same parties. Our decision, analysis and findings there are adopted and incorporated by reference herein. As discussed in our prior decisions, Infineon held that the ordinary term “bus” could not be read restrictively as a “multiplexed bus” even though the patentee described the “present invention” in terms of a Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 39 “multiplexed bus” in isolated portions of the specification because “the remainder of the specification and the prosecution history shows that Rambus did not clearly disclaim or disavow such claim scope in this case.” Infineon, 318 F.3d at 1094-95. Micron maintains that the claims violate the written description requirement since the ‘898 patent application touts the importance of a multiplexed bus and distinguishes prior art generic bus inventions. (See App. Br. 31-32.) Micron supports the theory, which in essence, amounts to a scope of enablement attack on the claims, by relying, inter alia, on LizardTech, Inc. v. Earth Resource Mapping, Inc., 424 F.3d 1336, 1344 (Fed. Cir. 2005) (generic seamless DWT claim too broad absent an updated sums limitation). (App. Br. 23-24, 34) Micron relies on a “key factor” in LizardTech as embodied in an analogy there to an inventor who describes a fuel-efficient engine in such detail that it would not necessarily support “a broad claim to every possible type of fuel-efficient engine.” (App. Br. 24 (quoting LizardTech, 424 F.3d at 1346).) As another example, Micron reasons that the claims here are analogous to the “‘spikeless’” valve claims addressed in ICU Medical. (App. Br. 24 (quoting ICU Medical, Inc. v. Alaris Medical Systems, Inc., 558 F.3d 1368, 1377 (Fed. Cir. 2009)). But the gravamen of these arguments is that the ‘446 patent inventors were not in possession of broad claims not requiring a multiplexed bus scheme including memory devices with interfaces for such multiplexing. The ‘446 patent refers to “a preferred implementation” as using only bus connections of the invention –signifying more generic bus connections or no bus connections. (See ‘446 patent, col. 5, ll. 62-68.) Moreover, Infineon’s claim construction analysis, at the minimum, implies that skilled artisans Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 40 were in possession of generic bus claims. See Infineon, 318 F.3d at 1094-95 (noting that “multiplexing is not a requirement in all of Rambus’s claims” and that the PTO issued a restriction to a multiplexing group and a latency group, that “the PTO demonstrated an understanding of “bus” that is not limited to a multiplexing bus”). Original claims 73 and 91 in the first-filed ‘898 application recite a generic bus, showing the possession of generic bus claims. Also, as Rambus points out, “the original disclosure describes many inventions.” (Resp. Br. 13.) Based on the original disclosure, skilled artisans would have understood that other important touted features in the ‘898 disclosure, including clocking schemes and writing blocks of data, could have been practiced on generic buses without a multiplexing interface. Accord Infineon, 318 F.3d at 1095 (“a multiplexing bus is only one of many inventions disclosed in the ‘898 application”); cf. Crown Packaging Tech. Inc. v. Ball Metal Beverage Container Corp., 635 F.3d 1373, 1382-84 (Fed. Cir. 2011) (district court erred in finding lack of written description in generic claims where the application discloses separate solutions to related problems). The claims at issue require synchronous reading of data. Skilled artisans would have recognized that these elements could have been practiced on known buses, whether multiplexed or not. The lack of multiplexing would have been much simpler than a multiplexing scheme. Cf. Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336, 1351-53 (2011) (holding that evidence supported jury verdict of written description for similar Rambus claims where “the supposed genus consists of only two species, a multiplexed bus and a non-multiplexed bus”). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 41 Also, Micron’s spikeless valve analogy is not entirely apt here because valves were recited in the ICU Medical claims, but in the ‘446 patent claims, neither a bus nor an interface for attaching to a bus is recited, so ICU Medical does not dictate that the claims must support any type of bus or bus interface. But even if the claims implicitly require such a bus scheme, Rambus, the Examiner, the Infineon claim construction, and the Hynix Semiconductor written description analysis, show that on this record, the inventors originally possessed inventions directed to a generic bus scheme. B.) The DLL Micron asserts that the Examiner improperly construed the delay lock loop (DLL) limitation in claim 4. Micron considers the avowed support for claim 4, i.e., Figure 12 of the ‘446 patent, to show a clock averaging circuit, and not a circuit that adjusts the delay of an internal clock with respect to an external clock. Micron also maintains that the internal clock is “not locked to either external clock signal.” (App. Br. 26.) Micron explains that that Figure 12 shows a clock that “synchronizes data output to a midpoint between two external clock signals” but does not “synchronize the output of . . . data with the external clock signal” as claim 4 requires. (App. Br. 27.) Micron’s argument does not show a lack of written description. Synchronizing an internal clock with the average of two external clock signals amounts to synchronizing not only with either of the two clock signals which define the average, but also with the clock generator which generates the two signals. (See Resp. Br. 13-14 (Rambus stating that Micron’s contentions do not show a distinction).) That is, Figure 12 signifies an early clock and a late clock, but there is only one clock Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 42 generator. For example, Figures 8A and 8B show one clock generator 50 creating an early clock1 and a late clock2, the latter due to delays on the bus. Thus, synchronizing to the average of the two clock signals in the ‘446 patent amounts synchronizing to the external clock generator 50. Micron also asserts that Rambus argued a distinction between a phase locked loop (PLL) and a delay lock loop (DLL) in other proceedings and that any argued distinction should be binding. (App. Br. 28.) However, the Board previously essentially bound Rambus and determined that Rambus’s experts had essentially equated PLL and DLL circuits in determining the meaning of DLL (see supra the DLL discussion involving Bazes and Lofgren). In other words, Rambus’s experts essentially generically grouped DLL’s and PLL’s. The Examiner also cites and quotes several experts who generally support the position that Figure 12 reasonably supports a DLL. (See RAN 11-12.) The Examiner also relies on prior art patents to Petrich and Bazes. (See RAN 14-18.) While Micron maintains both that the external clock and internal clock in a DLL must be locked together and that “the internal clock is aligned with the time of the external clock” (App. Br. 26), the expert testimony, for example Mr. Karp, and Mr. Murphy, indicate that delay with respect to the external clock and feedback is required, but not necessarily strict alignment of the internal clock with an external clock. The Examiner also points to a previous claim construction order showing a consistent definition. (See RAN 14.) The record supports the Examiner. Claim 4 recites a delay lock loop and Figure 12, in light of Figures 8A and 8B, supports the concept of a DLL as recognized by some of the experts relied upon by the Examiner. And Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 43 even if the term “delay lock loop” does not comport strictly with a definition presented by Micron, Figure 12 supports the general concept of a delay lock loop – especially where its meaning includes other characteristics, e.g., phase lock loop characteristics. See Application of Anderson, 471 F.2d 1237, 1244 (CCPA 1973) (“The question . . . is not whether ‘carrying’ was a word used in the specification as filed but whether there is support in the specification for employment of the term in a claim; is the concept of carrying present in the original disclosure?”) Skilled artisans would have recognized that the inventors of the ‘446 patent originally possessed a delay lock loop in light of Figures 8A, 8B and 12 and accompanying discussions in the ‘446 patent. Based on the foregoing discussion, Micron has not shown error in the Examiner’s finding that claims 1-4 have original written description support as necessary to antedate Park or JEDEC as prior art references. Secondary Considerations Rambus contends that substantial secondary evidence supports unobviousness. But the evidence fails to establish a nexus because any success likely flows from a variety of several unclaimed features touted here or in other Rambus proceedings or patents. Such unclaimed, but disclosed features, include eight data lines, small DRAM sizes with minimal bus loading, multiplexed bus architecture and device interfaces, packetized control, unique device identifiers, time access and arbitration schemes, a 500 MHz data rate, and memory devices having all the functionality of prior art circuit boards. (See ‘446 patent, col. 3, ll. 33-53; col. 4, ll. 5-9, 44-53; col. 7, ll. 11-23; col. 9, ll. 56-59; col. 12, ll. 45-58; col. 14, ll. 48-50.) See also Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1095 (Fed. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 44 Cir. 2003) (“The present invention is designed to provide a high speed, multiplexed bus’” (quoting Rambus’s related ‘918 patent, col. 5, ll. 36-46), but “the prosecution history shows that a multiplexing bus is only one of many inventions disclosed in the ‘898 application.”)28 Rambus agrees that “the original disclosure describes many inventions.” (Resp. Br. 13.) As Micron points out, Rambus presents the same evidence it provided “in every one of the 10 pending inter partes reexaminations.” (Reb. Br. 16.) Different claims in the different proceedings have varying scope. As Micron also points out, Rambus’s proffered evidence is short on objectivity and relies on interested witnesses. (See id.) Rambus’s evidence does not demonstrate that any success was due solely to the claimed features, or to claimed features that were not already known in the prior art. For example, Rambus’s contention “that the Farmwald family, which includes the ‘446 patent, has numerous licensees” is a vague statement which lacks a specific nexus to the claims. (See Resp. Br. 15.) Rambus does not provide a copy of any licenses (even if one does pertain to the ‘446 patent) or provide evidence showing what other unclaimed features any of the licenses involve. Also, it is well known and settled law that competitors often take licenses for commercial or other reasons having nothing to do with unobviousness. Single chip synchronous memory devices were known as Bennett discloses, as were DRAMs, precharging and DLL circuits, as the prior art 28 See Infineon, 318 F.3d at 1084-86 (finding that the written descriptions of each of four related Rambus patents, 5,954,804; 5,953,263; 6,034,918; and 6,032,214, are substantially identical to the written description of the 07/510,898 application to which they, and the ‘446 patent here, all claim continuity). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 45 discussed supra discloses. For example, “the most popular form of read/write memory is the semiconductor DRAM.” (Wicklund, col. 1, ll. 36- 39.) Hence, the record suggests that at least part of any commercial success would have been due to “the most popular” memory chip, a DRAM chip, in general (or to Bennett’s known synchronous chip in general). Cf. In re DBC, 545 F.3d 1373, 1384 (Fed. Cir. 2008) (Board’s conclusion of nonobviousness supported, the Board finding, inter alia, that “evidence in the record suggested that the success of XanGo™ juice may be due to other factors-for example, the increasing popularity of the mangosteen fruit in general” ). The Federal Circuit further reasoned in DBC that . . . DBC has done little more than submit evidence of sales. However substantial those sales, that evidence does not reveal in any way that the driving force behind those sales was the claimed combination of mangosteen fruit, mangosteen rind extract, and fruit or vegetable juice. Nor is there any evidence that sales of XanGo™ juice were not merely attributable to the increasing popularity of mangosteen fruit or the effectiveness of the marketing efforts employed. Id. at 1384. See also Ormco Corp. v. Align Technology, Inc., 463 F.3d 1299, 1312, 1313 (Fed. Cir. 2006) (“[I]f the feature that creates the commercial success was known in the prior art, the success is not pertinent.” Reasoning that success that is due “‘partially’ to claimed features” and to unclaimed features and/or other features already in the art lacks the requisite nexus to show unobviousness.) (citations omitted). While Rambus argues that the claims solve a memory bottleneck problem and obtain high-speed performance (Resp. Br. at 14), the claims read on slow memory devices, since the claims do not recite any speed (as a functional limitation) and do not recite other sufficient and necessary Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 46 circuitry to obtain such speed.29 Moreover, Dr. Farmwald testified that “even up into the early part of the ‘90s, it [speed] wasn’t going to be a problem.” (See Farmwald Trial Dep. 276 (attached as Resp. Br. Evidence Ex. E-5).) In other words, Dr. Farmwald may have solved a problem predicted to occur in the future, but not a long-standing problem. Rambus’s allegations of recognition and praise for the “‘high bandwidth memory-interface technology’” and bandwidth advances “‘as a result of the ideas [Dr. Horowitz] pioneered’” (Resp. Br. 15) point to a lack of nexus as to any success or praise. The devices claimed here have no bandwidth limitation, let alone limitations directed to the myriad other “ideas [Dr. Horowitz] pioneered” – whatever they may have been. Based on the foregoing discussion, the record suggests that the proffered evidence is not commensurate with the claim scope and lacks a nexus thereto. Rambus has not demonstrated that any success is not due to popular DRAMs in general, synchronous memory chips in general, or, to a whole host of unclaimed features, including the unclaimed but touted multiplexed bus interface, high bandwidth and/or speed, and other unclaimed circuit features, such as the identification feature, arbitration control features, low capacitance and power, etc. The record indicates that 29 In another reexamination proceeding, similar to the proceeding here (Resp. Br. 15), Rambus alleges “disbelief” and pervasive skepticism “‘over a 500 megabit per second DRAM data rate’” and “about many of the specific features of the technology” as showing “‘strong evidence of nonobviousness.’” (See Rambus Resp. Br. 19 (citations omitted) in the BPAI 2012-000142 reexamination proceeding.) Assuming for the sake of argument that uncorroborated statements by the inventors show skepticism by others, as noted, claims 1-4 do not require the 500 MHz speed touted or “many of the other specific features” – whatever they may be. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 47 such features (and other pioneering ideas) would have been required to obtain the touted high speed from a single DRAM. See Infineon, 318 F.3d at 1095 (quoted supra, mentioning Rambus’s high speed multiplexed system). After careful consideration of the record, the obviousness of combining known precharge, DRAM memory, and DLL, with Bennett’s synchronous memory device, and combining a known synchronizing SCI interface and precharge circuit with Moussouris’s DRAM, outweighs the proffer of secondary considerations. CONCLUSION Micron has demonstrated that the following rejections are warranted based on this record: claims 1 and 2 as obvious based on Bennett, APA, and either Wicklund or Bowater; claim 3 as obvious based on Bennett, Wicklund or Bowater, and either Inagaki or Novak; claim 4 as obvious based on Bennett, either Wicklund or Bowater, and either Bazes or Lofgren; and claims 1 and 2 and as obvious based on Moussouris, APA, SCI-A, and either Wicklund or Bowater. Micron has not demonstrated that the Examiner erred in deciding not to reject claims 3 and 4 based on the added teachings of SCI-B since Micron has not demonstrated that SCI-B is prior art. Micron also has not demonstrated that the Examiner erred in deciding not to reject claims 1-4 as anticipated by JEDEC or as obvious based on Park and JEDEC since the references do not antedate the effective filing date of claims 1-4. Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 48 DECISION The Examiner’s decision not to reject claims 1-4 is reversed.30 This decision contains a new ground of rejection pursuant to 37 C.F.R. § 41.77(b), which provides that “[a]ny decision which includes a new ground of rejection pursuant to this paragraph shall not be considered final for judicial review.” Correspondingly, no portion of the decision is final for purposes of judicial review. A requester may also request rehearing under 37 C.F.R. § 41.79, if appropriate; however, the Board may elect to defer issuing any decision on such request for rehearing until such time that a final decision on appeal has been issued by the Board. For further guidance on new grounds of rejection, see 37 C.F.R. § 41.77(b)-(g). The decision may become final after it has returned to the Board. 37 C.F.R. § 41.77(f). 37 C.F.R. § 41.77(b) also provides that the Patent Owner, WITHIN ONE MONTH FROM THE DATE OF THE DECISION, must exercise one of the following two options with respect to the new grounds of rejection to avoid termination of the appeal as to the rejected claims: (1) Reopen prosecution. The owner may file a response requesting reopening of prosecution before the examiner. Such a response must be either an amendment of the claims so rejected or new evidence relating to the claims so rejected, or both. (2) Request rehearing. The owner may request that the proceeding be reheard under § 41.79 by the Board upon the same record. 30 See 37 C.F.R. § 41.77(b) (denominating a reversal of a refusal to reject as a new ground of rejection). Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 49 Any request to reopen prosecution before the examiner under 37 C.F.R. § 41.77(b)(1) shall be limited in scope to the “claims so rejected.” Accordingly, a request to reopen prosecution is limited to issues raised by the new ground(s) of rejection entered by the Board. A request to reopen prosecution that includes issues other than those raised by the new ground(s) is unlikely to be granted. Furthermore, should the patent owner seek to substitute claims, there is a presumption that only one substitute claim would be needed to replace a cancelled claim. A requester may file comments in reply to a patent owner response. 37 C.F.R. § 41.77(c). Requester comments under 37 C.F.R. § 41.77(c) shall be limited in scope to the issues raised by the Board’s opinion reflecting its decision to reject the claims and the patent owner’s response under paragraph 37 C.F.R. § 41.77(b)(1). A newly proposed rejection is not permitted as a matter of right. A newly proposed rejection may be appropriate if it is presented to address an amendment and/or new evidence properly submitted by the patent owner, and is presented with a brief explanation as to why the newly proposed rejection is now necessary and why it could not have been presented earlier. Compliance with the page limits pursuant to 37 C.F.R. § 1.943(b), for all patent owner responses and requester comments, is required. The examiner, after the Board’s entry of a patent owner response and requester comments, will issue a determination under 37 C.F.R. § 41.77(d) as to whether the Board’s rejection is maintained or has been overcome. The proceeding will then be returned to the Board together with any comments and reply submitted by the owner and/or requester under Appeal 2012-001639 Reexamination Control Nos. 95/001,109 & 95/001,155 Patent 6,546,446 B2 50 37 C.F.R. § 41.77(e) for reconsideration and issuance of a new decision by the Board as provided by 37 C.F.R. § 41.77(f). Extensions of time for taking action under 37 C.F.R. § 41.77(b) are governed by 37 C.F.R. § 41.77(g). See also 37 C.F.R. § 41.77 regarding extensions of time for requesting rehearing. REVERSED Finnegan, Henderson, Farabow, Garrett & Dunner, LLP 901 New York Avenue, NW Washington, DC 20001-4413 Third Party Requesters: Haynes & Boone, LLP IP Section 2323 Victory Avenue Suite 700 Dallas, TX 75219 Novak Druce & Quigg, LLP 1000 Lousiana Street 53rd Floor Houston, TX 77002 Copy with citationCopy as parenthetical citation