Ex Parte 6465893 et alDownload PDFPatent Trial and Appeal BoardDec 21, 201295000229 (P.T.A.B. Dec. 21, 2012) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/000,229 02/15/2007 6465893 TESSERA 3.5-018CCIICIICII 7288 530 7590 11/14/2014 LERNER, DAVID, LITTENBERG, KRUMHOLZ & MENTLIK 600 SOUTH AVENUE WEST WESTFIELD, NJ 07090 EXAMINER KIELIN, ERIK J ART UNIT PAPER NUMBER 2814 MAIL DATE DELIVERY MODE 11/14/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ SILICONWARE PRECISION INDUSTRIES CO., LTD and SILICONWARE, U.S.A. Requester, Cross-Appellant, and Respondent v. TESSERA, INC. Patent Owner, Appellant, and Respondent ____________ Appeal 2014-004291 Reexamination Control 95/000,229 Technology Center 3900 Patent 6,465,893 B1 ____________ Before DAVID M. KOHUT, ERIC B. CHEN, and IRVIN E. BRANCH, Administrative Patent Judges. CHEN, Administrative Patent Judge. DECISION ON EXAMINER’S DETERMINATION UNDER 37 C.F.R. § 41.77(d) Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 2 This is a decision under 37 C.F.R. § 41.77 (f) on the Examiner’s determination under 37 C.F.R § 41.77(d) maintaining the rejections of claims 5, 6, 19, 21, 25, 26, 61, and 62. The Examiner confirmed the patentability of claim 63. We have jurisdiction under 35 U.S.C. §§ 6(b), 134, and 315. We affirm. STATEMENT OF THE CASE In a prior Decision on Appeal, entered December 21, 2012, another panel of this Board reversed the Examiner’s refusal to reject claims 5, 6, 19, 21, 25, 26, and 61–63 under 35 U.S.C. §§ 102(b) and 103(a) as proposed and appealed by Requesters Siliconware Precision Industries Co., Ltd. and Siliconware USA, Inc. These rejections were entered as a new ground of rejection pursuant to our authority under 37 C.F.R. § 41.77(b), as follows: 1. Claims 5, 21, and 63 are rejected under 35 U.S.C. § 102(b) as anticipated by Nishide (JP H1-118456; Aug. 10, 1989). 2. Claims 5, 6, 19, 25, and 26 are rejected under 35 U.S.C. § 102(e) as anticipated by Tsubosaki (US 5,583,375; Dec. 10, 1996). 3. Claims 6, 19, 25, and 26 are rejected under 35 U.S.C. § 103(a) as obvious over Nishide and Okinaga (JP S61-177759; Aug. 9, 1986). 4. Claims 6, 19, 25, 26, and 63 are rejected under 35 U.S.C. § 103(a) as obvious over Okinaga and Takahira (JP S58-218130; Dec. 19, 1983). 5. Claims 5, 21, and 63 are rejected under 35 U.S.C. § 103(a) as obvious over Freyman (US 4,700,276; Oct. 13, 1987) and Takahira. 6. Claims 6, 19, 21, 25, 26, and 63 are rejected under 35 U.S.C. § 103(a) as obvious over Otsuka (Kanji Otsuka et al., High Reliability Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 3 Mechanism of New Silicone Gel Sealing in Accelerated Environment Test, PROC. INT’L. ELECTRONICS PACKAGING SOC’Y. 720–26 (1984)) and Takahira. 7. Claims 61 and 62 are rejected under 35 U.S.C. § 103(a) as obvious over Tsubosaki and Suzuki. Patent Owner Tessera, Inc. submitted a Request to reopen prosecution before the Examiner under 37 C.F.R. § 41.77(b)(1), dated February 21, 2013, accompanied by arguments and additional evidence in the form of a Declaration under 37 C.F.R. § 1.131 of Dr. Ephraim Suhir, dated February 19, 2013 (“Suhir Declaration”) with supporting exhibits (“PO § 41.77(c) Comments”). In response to Patent Owner’s Request, Requesters Siliconware Precision Industries Co., Ltd. and Siliconware USA, Inc. filed written comments to Patent Owner Tessera, Inc. Request, dated March 21, 2013. Requesters subsequently filed a notice of withdrawal from the inter partes reexamination proceeding, dated May 9, 2013. The Examiner determined that claims 5, 6, 19, 21, 25, 26, 61, and 62 were unpatentable, confirmed the patentability of claim 63, and issued a Determination under 37 C.F.R. § 41.77(d), dated July 17, 2013 (“Determination”). Patent Owner contends that the Examiner’s Determination maintaining these rejections is erroneous for various reasons, and has submitted Requester Comments on the Examiner’s Determination, dated August 16, 2013 (“PO § 41.77(e) Comments”). Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 4 Claims 1, 2, and 5 are exemplary, with disputed limitations in italics: 1. A semiconductor chip assembly, comprising: a) a first semiconductor chip having a front surface, a rear surface and contacts on said front surface; b) a second semiconductor chip having a front surface, a rear surface and contacts on said front surface, said rear surface of said second semiconductor chip being juxtaposed with said front surface of said first semiconductor chip; c) a first backing element having electrically conductive first terminals, said first backing element being juxtaposed with said rear surface of said first semiconductor chip so that at least some of said terminals overlie said rear surface of said first semiconductor chip, at least some of said contacts on said first and said second semiconductor chips being electrically connected to at least some of said terminals; and d) a substrate having contact pads thereon, said first terminals being connected to said contact pads of said substrate, said substrate being adapted to connect the assembly with other elements of a circuit, at least some of said first terminals overlying said rear surface of said first semiconductor chip. 2. The assembly as claimed in claim 1 wherein said first terminals are movable with respect to said first chip to compensate for differential thermal expansion of said first chip and said substrate. 5. The assembly as claimed in claim 4 further comprising first bonding wires extending between at least some of said contacts of said first semiconductor chip and said lead portions so that said terminals of said first backing element are electrically connected to at least some of the contacts on said first semiconductor chip through said lead portions and said first bonding wires. Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 5 ANALYSIS § 102 Rejection – Nishide The Examiner found that the mounting board 1 of Nishide corresponds to the claimed “backing element,” as recited in dependent claim 5. (Determination 3–4.) We agree with the Examiner’s determination. Nishide “relates to a chip mounting structure in arranging chips on a circuit board.” (P. 1.) Figure 1 of Nishide illustrates a cross-sectional view of a chip mounting structure that includes a mounting board 1, a chip 2 (e.g., an integrated circuit), and a flat shaped circuit board 3. (P. 2.) Nishide explains that the chip 2 is housed in a chip housing hollow 5 of each mounting board 1. (P. 3.) Furthermore, Nishide explains that the mounting board 1 is formed as a single item using three green sheets 10–12. (P. 3; see also Figs. 2(a)–(b).) Because Nishide explains that the chip 2 is housed in the mounting board 1, Nishide discloses the claimed “backing element.” Patent Owner argues that “Nishide’s mounting board is a rectangular cup-shaped structure, not a generally planar or flat structure.” (PO § 41.77(e) Comments 16.) In particular, Patent Owner argues that “[t]his cup-shaped element simply is not thin in comparison to its length and width and is not generally planar or flat, as required by the proper construction of the term ‘backing element’” and “[a] hollow cup is not a planar or flat sheet.” (Id.) Similarly, Patent Owner argues, “[t]he unitary ‘co-fired’ ceramic body of Nishide’s mounting board 1 is not thin in relation to its length and width” and “[a]s Dr. Suhir explains: ‘A person of ordinary skill would not understand the mounting board 1 to be a “sheet-like” structural Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 6 element as required of the “backing element” in the ’893 Patent.’” (PO § 41.77(c) Comments 3.) However, the Examiner cited to the entire mounting board 1 of Nishide, rather than the penetration holes 16 and 20, for the disclosure of the claimed “backing element,” which is illustrated in Figure 1 of Nishide as having a sheet-like structure. (Determination 4–5.) Furthermore, the statements in the Suhir Declaration relied upon by Patent Owner lack persuasive factual support because the Suhir Declaration does not cite to sufficient corroborating evidence. See In re Beattie, 974 F.2d 1309, 1313 (Fed. Cir. 1992) (“[D]eclarations themselves offer only opinion evidence which has little value without factual support.”). The Examiner further found that the wiring patterns 13, 14, 17, 18, 21, 22 and via holes 15, 19, 21 of Nishide collectively correspond to the claimed “wherein said first backing element has electrically conductive lead portions thereon.” (Determination 5–6.) We agree with the Examiner’s determination. Figure 2(a) of Nishide illustrates that the green sheets 10–12 are stacked to form a single item, including forming wiring patterns 13, 14 in via hole 15 of green sheet 10, forming wiring patterns 17, 18 in via hole 19 of green sheet 11, and forming wiring patterns 21, 22 in via hole 23 of green sheet 12. (P. 3.) Figure 2(a) of Nishide further illustrates that such wire patterns collectively extend from a bottom surface to a top surface of the mounting board 1. Because wiring patterns 13, 14, 17, 18, 21, and 22 are formed in the mounting board 1 of Nishide, including the top surface, Nishide discloses the limitation “wherein said first backing element has electrically conductive lead portions thereon.” Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 7 Patent Owner argues that “Nishide still would not have bonding wires extending to lead portions on the backing element” because “Nishide’s bonding wires terminate at a top surface of layer 11 overlying the bottom layer 10.” (PO § 41.77(e) Comments 17; see also PO § 41.77(c) Comments 5.) To support this position, Patent Owner points to paragraph 9 of the Suhir Declaration. (Id.) The Suhir Declaration states that “even if one could imagine the bottom layer 10 alone as a ‘backing element’, Nishide still would not have bonding wires extending to lead portions on the backing element” and “Nishide’s bonding wires terminate at a top surface of layer 11 overlying the bottom layer 10.” (Suhir Decl. ¶ 9.) Contrary to Patent Owner’s arguments, Figure 2(a) of Nishide illustrates that the wiring patterns 13, 14, 17, 18, 21, and 22 extend from a bottom surface to a top surface of the mounting board 1. Furthermore, the statements in the Suhir Declaration relied upon by Patent Owner lack persuasive factual support because the Suhir Declaration does not cite to sufficient corroborating evidence. See Beattie, 974 F.2d at 1313. Accordingly, we agree with the Examiner that the rejection of claim 5 under 35 U.S.C. § 102(b) as anticipated by Nishide should be maintained. § 102 Rejection – Tsubosaki Claims 5 and 6 The Examiner found that the insulating adhesive films 2 and 7 of Tsubosaki, which secures the outer lead 3B to the semiconductor device 20, collectively correspond to the claimed “backing element . . . electrically connected to at least some of the contacts on said first semiconductor chip Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 8 through said lead portions and said first bonding wires,” as recited in dependent claim 5. (Determination 10–12.) In particular, the Examiner found that “[t]he leads on the backing element [as claimed,] are leads 3B of the lead frame having terminals at the ends of the leads 3B, terminating at the rear surface of the semiconductor chip 1.” (Id. at 11 (citing ACP 35, mailed February 5, 2009).) We agree with the Examiner’s determination. Tsubosaki relates to stacked semiconductor devices, “in which leads and external terminals of a semiconductor chip are electrically connected on the principal surface of the semiconductor chip having circuits.” (Col. 1, ll. 13–16.) Figure 2 of Tsubosaki illustrates a cross-sectional view of a semiconductor device 20, such that the semiconductor device 20 is connected to inner leads 3A via a solder bump 4. (Col. 6, ll. 11–18.) Figure 2 of Tsubosaki further illustrates that the inner leads 3A are secured to the principal surface of the semiconductor device 20 and that the outer leads 3B are secured to the rear surface the semiconductor device 20 via adhesive film (tape) 2 and 7, respectively. (Col. 6, ll. 12–14, 26–31.) Figure 5 of Tsubosaki illustrates that the adhesive film (tape) is on the order of 0.1 mm in thickness. (Col. 7, ll. 46–51.) Figure 8 of Tsubosaki illustrates that the semiconductor device 20 is connected to the inner leads 3A using a bonding wire 31. (Col. 8, ll. 60–62.) Because Figure 2 of Tsubosaki illustrates the outer lead 3B extends along the rear surface of the semiconductor device 20 (i.e., the claimed “lead”), which is secured by the adhesive film (tape) 7, Tsubosaki discloses the limitation “backing element . . . electrically connected to at least some of the contacts on said first semiconductor chip through said lead portions and said first bonding wires.” Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 9 Patent Owner argues that [t]he extraneous adhesive film 2 on the chip top surface is clearly not “juxtaposed with the rear surface” . . . and therefore is not the claimed ‘backing element,’ and the bonding wires 31 which connect to leads 3A above the chip top surface therefore do not extend to “lead portions” on the backing element as required by claim 5. (PO § 41.77(e) Comments 7.) Similarly, Patent Owner argues [t]he same is true of other embodiments of Tsubosaki seen in FIGS. 9 and 10 . . . where the adhesive film portions that extend on the top surface or the sides of the chip are not a “backing element,” but at best are extraneous elements that extend away from an element underlying the chip rear surface. (Id.) However, as discussed previously, the Examiner cited to the adhesive film (tape) 7 of Tsubosaki extending along the rear surface of the semiconductor device 20 and the portion of the outer lead 3B that contacts the adhesive film (tape) 7, to disclose the limitation “backing element . . . electrically connected to at least some of the contacts on said first semiconductor chip through said lead portions and said first bonding wires.” Patent Owner further argues that the width of the adhesive film strip 7, i.e., the dimension of the film strip 7 to the left and right as shown in FIG. 7, is relatively small, such that the thickness of the adhesive film strip is “comparable to its width” . . . rather than being “thin in relation to its length and width.” (PO § 41.77(e) Comments 8–9.) To support this position, Patent Owner points to paragraph 15 of the Suhir Declaration. (Id.) The Suhir Declaration states that “Tsubosaki Fig. 3 . . . shows adhesive film 7 that is in effect an elongated strip having a width comparable to its thickness.” (Suhir Decl. ¶ 15.) However, the statements in the Suhir Declaration relied upon by Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 10 Patent Owner lack persuasive factual support because the Suhir Declaration does not cite to sufficient corroborating evidence. See Beattie, 974 F.2d at 1313. For example, the Suhir Declaration has not sufficiently established that the adhesive film (tape) 7 of Tsubosaki has a width that is on the order of 0.1 mm. Accordingly, we agree with the Examiner that the rejection of claims 5 and 6 under 35 U.S.C. § 102(e) as anticipated by Tsubosaki should be maintained. Claims 19, 25, and 26 Claims 19, 15, and 26 are multiple dependent claims, which depend from claims 2 and 3. The Examiner found that the mechanical stress due to heating of the semiconductor chip, the lead, and insulating adhesive films, collectively corresponds to the limitations “wherein said first terminals are movable with respect to said first chip to compensate for differential thermal expansion of said first chip and said substrate,” as recited in dependent claim 2 and “wherein said first semiconductor chip and said substrate have different coefficients of thermal expansion,” as recited in dependent claim 3. (Determination 11–12 (citing Office Action 27–28, mailed August 21, 2008); see also ACP 36–37, mailed February 5, 2009.) We agree with the Examiner’s determination. Tsubosaki explains that [a]s the lead 3 is secured via the insulating adhesive films 2, 7 to the semiconductor chip 1, the connection between the semiconductor chip 1 and the lead 3 is prevented from peeling off or rupturing even when the lead 3 undergoes mechanical stress originating from heat because of the difference in thermal Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 11 expansion coefficient between the monocrystalline silicon semiconductor chip 1 and the wiring board such as printed circuit board. (Col. 8, ll. 31–39.) Furthermore, Tsubosaki explains that “[a]lthough the leads 3 are secured via the insulating adhesive films 2, 7 to the semiconductor chip 1 in the embodiment 1 shown, it may be modified . . . by increasing the adherent areas or places of the insulating adhesive films 2, 7 to prevent the deformation.” (Col. 8, ll. 55–60.) Accordingly, because an embodiment of Tsubosaki is modified to “prevent the deformation” of the leads 3, Tsubosaki provides an implicit disclose of an “unmodified” embodiment, in which the leads 3 deform due to stress originating from heat. Patent Owner argues that “the asserted ‘backing element’ 2 is, in fact, a polyimide adhesive film which firmly bonds the leads in Tsubosaki (including the asserted terminals 3B) to the chip 1 and thus serves to prevent movement of the terminals relative to the chip.” (PO § 41.77(e) Comments 11.) However, as discussed previously, Tsubosaki provides a disclosure of an “unmodified” embodiment, in which the leads 3 deform due to stress originating from heat. Accordingly, we agree with the Examiner that the rejection of claims 19, 25, and 26 under 35 U.S.C. § 102(e) as anticipated by Tsubosaki should be maintained. § 103 Rejection – Nishide and Okinaga We do not reach the additional rejections of claims 6, 19, 25, and 26 under § 103(a) as obvious over Nishide and Okinaga. Affirmance of the anticipation-based rejections discussed previously renders it unnecessary to Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 12 reach the remaining obviousness rejections, as all of pending claims have been addressed and found unpatentable. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009). § 103 Rejection – Freyman and Takahira We do not reach the additional rejection of claim 5 under § 103(a) as obvious over Freyman and Takahira. Affirmance of the anticipation-based rejection discussed previously renders it unnecessary to reach this remaining obviousness rejection, as this pending claim has been addressed and found unpatentable. Cf. Gleave, 560 F.3d at 1338. § 103 Rejection – Otsuka and Takahira Claim 21 The Examiner found that the glass reinforced epoxy base FR-4 in Figure 2 of Otsuka corresponds to the claimed “first backing element,” as recited in dependent claim 21. (Determination 24.) The Examiner further found that the embedded pins in Figure 2 of Otsuka correspond to the limitation “terminals are disposed at said top surface.” (Id.) In particular, the Examiner found that “Otsuka’s Fig. 2 . . . shows that the terminal pins extend to the top surface of the FR-4 substrate (i.e. the claimed ‘backing element’) on which the chip is bonded; therefore, the terminals are disposed ‘at’ the top surface of the backing element as required by claim 21.” (Id.) We agree with the Examiner’s determination. Otsuka relates to pin grid array (PGA) packages with pins embedded in printed circuit boards and silicone gel encapsulation. (Abstract.) Figure 2 Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 13 illustrates a cross-sectional view of a PGA package structure with a chip mounted on a glass reinforced epoxy base or PC board FR-4 (i.e., the claimed “first backing element”), with two embedded pins (i.e., the claimed “terminals”) on either side of the chip. Figure 2 further illustrates that the embedded pins extend through the entire thickness of the glass reinforced epoxy base, including the top surface. Accordingly, Otsuka teaches the limitation “wherein said first backing element has a top surface facing toward said first chip and said lead portions and terminals are disposed at said top surface.” Patent Owner argues that “[t]he word ‘terminal,’ in the context of the ’893 Patent specification and the identical specifications of other related patents means ‘an end point for the connection of the package to the outside’” and “[a]s seen in FIG. 2 of Otsuka, the pins extend through the glass-reinforced epoxy package base and project downwardly below the bottom surface of the base for insertion into corresponding socket holes of a substrate.” (PO § 41.77(e) Comments 24.) Contrary to Patent Owner’s arguments, Figure 2 of Otsuka illustrates that the embedded pins (i.e., the claimed “terminal”) extend through the entire thickness of the glass reinforced epoxy base, including the top surface. Accordingly, we agree with the Examiner that the rejection of claim 21 under 35 U.S.C. § 103(a) as obvious over Otsuka and Takahira should be maintained. Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 14 Claims 6 and 25 Patent Owner does not present any substantive arguments with respect to the rejection of claims 6 and 25 under 35 U.S.C. § 103(a) over Otsuka and Takahira. Thus, any such arguments are deemed to be waived. Claim 19 We do not reach the additional rejection of claim 19 under 35 U.S.C. § 103(a) over Otsuka and Takahira. Affirmance of the anticipation-based rejection discussed previously renders it unnecessary to reach this remaining obviousness rejection, as this pending claim has been addressed and found unpatentable. Cf. Gleave, 560 F.3d at 1338. § 103 Rejection – Tsubosaki and Suzuki The Examiner found that stress free die bonding technology of Suzuki, including the die bond adhesive with a very low Young’s modulus, corresponds to the limitations “wherein the backing element comprises a dielectric element and a compliant layer, said compliant layer having an elastic modulus lower than an elastic modulus of said dielectric element,” as recited in dependent 61 and “wherein said dielectric element comprises a flexible layer,” as recited in dependent claim 62. (Determination 13.) The Examiner concluded that: [i]t would have been obvious . . . to ensure that the adhesive layers A on the captone or other polyimide film B of Tsubosaki’s backing element 2, 7 is a low Young’s modulus elastomer, such as the “silicon elastomer” taught in Suzuki, in order to relieve stress caused by differential thermal expansion between the chip 1, the leads 3, and the substrate 21, 41, and Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 15 thereby to prevent “die warpage, crack, and delamination”, as taught by Suzuki. (Id. (quoting ACP 48, mailed February 5, 2009).) We agree with the Examiner’s determination. Suzuki relates to the application of copper lead frames to plastic encapsulated very large scale integration (VLSI) technology. (Abstract.) Suzuki explains that some problems associated with stress in such copper lead frames include “die warpage, crack and delamination from the lead frame.” (Id.) Suzuki further explains that for stress free die bonding technology, “it was found that the die bond adhesive of very low Young’s modulus is effective to reduce the thermal stress.” (Id.) A person of ordinary skill in the art would have recognized that incorporating the die bond adhesive of Suzuki, having a very low Young’s modulus, with insulating adhesive films of Tsubosaki, would improve Tsubosaki by reducing warpage, crack and delamination. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007) (“[I]f a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill.”). Thus, we agree with the Examiner (Determination 13) that modifying Tsubosaki to incorporate the adhesive of Suzuki with a very low Young’s modulus would have been obvious. Patent Owner argues that “the problems contemplated in Suzuki are not present in the small area attachments contemplated by the Tsubosaki structure, there is no reason to combine these references.” (PO § 41.77(e) Comments 15; see also PO § 41.77(c) Comments 10.) To support this Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 16 position, Patent Owner points to paragraph 16 of the Suhir Declaration. (PO § 41.77(e) Comments 14–15.) The Suhir Declaration states that: The problems of die cracking and delamination treated in Suzuki arise from bonding a large area of a substantially rigid chip to a structure (the die paddle) which also has substantial stiffness and which has a coefficient of thermal expansion (“CTE”) markedly different from the chip. The small area attachments such as those between chip 1 and each of many individual outer leads 3B shown in Tsubosaki Figs. 3 and 8 would not cause die cracking or delamination phenomena as contemplated by Suzuki. (Suhir Decl. ¶ 16.) Again, the statements in the Suhir Declaration relied upon by Patent Owner lack persuasive factual support because the Suhir Declaration does not cite to sufficient corroborating evidence. See Beattie, 974 F.2d at 1313. For example, the Suhir Declaration does not provide quantitative calculations with respect to the “large area” of Suzuki and the “small area” of Tsubosaki. Accordingly, we agree with the Examiner that the rejection of claims 61 and 62 under 35 U.S.C. § 103(a) as obvious over Tsubosaki and Suzuki should be maintained. DECISION We affirm the Examiner’s decision not to maintain the rejection of claim 63 under 35 U.S.C. § 102(b) as anticipated by Nishide and under 35 U.S.C. § 103(a) as obvious over various combinations of Okinaga, Takahira, Freyman, and Otsuka. We affirm the Examiner’s decision to maintain the rejection of claim 5 under 35 U.S.C. § 102(b) as anticipated by Nishide. Appeal 2014-004291 Reexamination Control 95/000,229 Patent 6,465,893 B1 17 We affirm the Examiner’s decision to maintain the rejection of claims 5, 6, 19, 25, and 26 under 35 U.S.C. § 102(b) as anticipated by Tsubosaki. We affirm the Examiner’s decision to maintain the rejection of claims 6, 21, and 25 under 35 U.S.C. § 103(a) as obvious over Otsuka and Takahira. We affirm the Examiner’s decision to maintain the rejection of claims 61 and 62 under 35 U.S.C. § 103(a) as obvious over Tsubosaki and Suzuki. Requests for extensions of time in this inter partes reexamination proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79. This is a final decision. Parties to the proceeding seeking judicial review of the decision must comply with the notice and service requirements of 37 C.F.R. § 90.2. AFFIRMED Patent Owner: Lerner, David, Littenberg, Krumholz & Mentlik 600 South Avenue Westfield, NJ 07090 Third Party Requester: Tracy Druce IP Prosecution Department 2050 Main Street, Suite 1100 Irvine, CA 92614 Copy with citationCopy as parenthetical citation