Ex Parte 6,426,916 et al

Patent Trial and Appeal Board

Dec 7, 2012

95001122 (P.T.A.B. Dec. 7, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/000,166 08/22/2007 6426916 38512.3 7919
22852 7590 12/10/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
12/10/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,122 11/20/2008 6,426,916 8963.002.916 1557
22852 7590 12/10/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
12/10/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

MICRON TECHNOLOGY, INC.
Requester, Appellant

v.

RAMBUS, INC.
Patent Owner, Respondent
____________

Appeal 2012-001638
Reexamination Control Nos. 95/000,166 & 95/001,122
United States Patent 6,426,916 B2
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON REQUEST FOR REHEARING
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Rambus seeks relief in its Patent Owner’s Request for Rehearing, see
37 C.F.R. § 41.79, from the (formerly-named) Board of Patent Appeals and
Interferences Decision (June 14, 2012) reversing the Examiner’s decision
not to maintain the rejections of claims 26 and 28 of the ‘916 patent. (See
Reh’g Req. 1.) In response to Rambus’s Rehearing Request, Micron filed
Third Party Requestor’s Comments to Patent Owner’s Request for
Rehearing Pursant to 37 CFR § 41.79.
As the underlying Decision points out, the Board’s prior decisions,
BPAI 2012-000168 and BPAI 2012-000169, and a prior District Court
Order (hereinafter “Hynix II”)1 address the same or similar issues involving
the prior art patent to Bennett. (See Bd. Dec. 8.) Rambus now raises similar
issues to those addressed in related recent rehearing Board decisions, PTAB
2012-000168 and PTAB 2012-000169. The ‘168 and ‘169 rehearing
decisions are also adopted and incorporated by reference herein. Rambus’s
central arguments generate similar issues to those addressed in the related
cases and in the District Court, but nonetheless are addressed below along
with other arguments presented.
In a rehearing request, appellants have the burden to “state with
particularity the points believed to have been misapprehended or overlooked
by the Board.” 37 C.F.R. § 41.52 (a)(1). Rambus has not made the requisite
showing.

1 The underlying Decision refers to the District Court Order (see Bd. Dec. 5-
6 n. 5) as an attached Rambus Respondent Brief Exhibit O-3. The District
Court Order is now officially reported as follows: Rambus, Inc. v. Hynix
Semiconductor, Inc. 628 F.Supp.2d 1114, 1132-38 (N.D. Cal. 2008) (“Hynix
II”).
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Rambus asserts at the outset that “[t]hroughout the many related
proceedings,” the Board has not “affirmed the Examiner’s confirmation of a
claim.” (Reh’g Req. 1 n.1.) Rambus does not state why this assertion shows
that the Board misapprehended or overlooked anything of consequence.
Judicial consistency demands similar results “[t]hroughout the many related
proceedings.” Also, contrary to the assertion, the Board has affirmed the
Examiner’s refusal to maintain certain rejections of the claims in several
proceedings, including this proceeding, as one example. (See Bd. Dec. 22-
25 (affirming the Examiner’s decision not to reject claims 26 and 28 based
on Park or JEDEC).) In another related reexamination, control no.
90/010,574, the Board reversed the Examiner’s only rejection and did not
enter new rejections, contrary to Rambus’s assertions. (See BPAI 2011-
013706.)
Single Chip Memory Device
Rambus contends that Bennett does not disclose a single chip memory
device which Rambus maintains that claims 26 and 28 require. (See Reh’g
Req. 14-20.) As Micron contends, the Decision addresses this issue. (See
Reh’g Comments 7-8; Bd. Dec. 3-11.) Rambus concedes that “Bennett
makes clear that the VBI is normally but not always implemented on the
same chip substrate.” (Reh’g Req. 16.)
This concession alone reveals that despite numerous other arguments,
Rambus has failed to show a material overlooked point as to the single chip
issue. In addition, Rambus’s argument that skilled artisans would have
understood that a “memory device” in Bennett signifies a card and not a
chip, while the same term signifies just the opposite in the ‘916 patent, i.e., a
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chip and not a card, contradict one another, as the Decision points out. (Bd.
Dec. 10, n.6.)
Rambus argues that Bennett refers to a “large memory” and a “fast
memory” and that neither description refers to a single chip – i.e. both refer
to multi-chip memory cards. (See Reh’g Req. 14-15) To support this
position, Rambus refers to findings issued in a summary judgment order in a
related district court jury trial, which the Board Decision also relies on, as
noted supra. See “Hynix II” n.1 supra (Judge R. H. Whyte ruling on
anticipation by Bennett of similar claim terms in the ‘916 patent and other
Rambus patents). Rambus faults the Board for relying on Hynix II because
Rambus “made arguments here that were not presented to Judge Whyte.”
(Reh’g Req. 15, n. 9.) Rambus does not explain how shifting its arguments
in different tribunals helps Rambus or shows the Board overlooked anything.
Notwithstanding that Rambus attached Hynix II as an exhibit to its
Respondent Brief and also relies on it here and in other proceedings to
support its position (see Reh’g Req. 15; PTAB 2012-000169 at 5 (rehearing
decision)), Rambus’s attempt to back away from Hynix II now is
understandable because it does not help Rambus. Judge Whyte there made
extensive factual findings and “concludes that the Manufacturers [including
Micron] have carried their burden of producing evidence that Bennett
discloses a memory device, and that Rambus failed to rebut this showing.”
Hynix II at 1131. In making that determination, the court noted that the
Bennett inventors “were aware of memory cards and referred to them as
such when they chose” and “disparaged the . . . ‘many cards [that] can be
placed on the bus.’” (Id. (quoting Bennett at col. 37, ll. 26-28).) The court
also found that the Bennett inventors turned away from such memory cards
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and toward “VLSIC devices, including memory devices” which the court
referred to as “such memory chips.” Hynix II at 1131. The Board’s
Decision similarly finds that “Bennett also refers to ‘VLSIC chip devices’
and in the next full sentence (under the ‘Section 4.1’ heading) states that
‘[m]any, if not most, applications of VLSIC technology are likely to include
memory devices.’ ([Bennett] Col. 90, 11.42-43.)” (Bd. Dec. 5 (quoting
Bennett as noted).)2
Addressing Rambus’s expert Murphy’s opinion that Bennett’s 32
address and words bits would signify a room full of memory cards at the
time of Bennett (1982), and not a chip, the court found that “this ‘large
memory’ is meant to illustrate the flexibility of the bus interface, not to
suggest that Bennett contemplates that all memory devices designed for use
in its system should be so large.” Hynix II at 1130. The court also
recognized that Bennett teaches operating with as few as three VBI interface
pins and minimizing the number of node pins; hence, the court reasoned that
Murphy improperly focuses on Bennett’s 32 bit example and other examples
involving a larger number of pins. See id. at 1130-1131.

2 As the Decision explains, “Bennett’s ‘paramount object’ is to provide
communication between ‘very large scale integrated VLSI (circuit)
elements’ (col. 12, ll. 14-18) – i.e., “VLSIC chips” (col. 9, ll.35-40). (Bd.
Dec. 3.) In other words, VLSIC means very large scale integrated circuit
and itself means a single chip device.” Accord Rambus Inc. v. Infineon
Tech. AG, 318 F.3d 1081, 1085-86, 1091 (Fed. Cir. 2003) (defining
Rambus’s claim term, “integrated circuit device,” as a “circuit constructed
on a single monolithic substrate, commonly called a ‘chip’”) (relying on
trade dictionaries, citations omitted).

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Murphy here does not assert that Bennett’s 32 address and word bits
signify a room full of cards as he did in Hynix II, but he now asserts that it
signifies “a large number of memory chips on memory boards or cards”
(with a single VBI interface ). (See Supp. Murphy Decl. ¶ 33 (cited at
Reh’g Req. 14, 15).) Murphy does not set forth the basis for his shifted
position here or compare it to his earlier position.
In any event, the Decision makes similar findings to Hynix II. For
example, the Decision finds that Bennett’s large or fast memories come in
“different address widths, including 16, 24, or 32.” (Bd. Dec. 4.) In other
words, Bennett discloses “up to . . . 32 bit words.” (Bennett, col. 95, ll. 59-
64.) As the Decision finds, Bennett contemplates replacing cards with chips.
(See Bd. Dec. 5-6.) Bennett also discloses the option of passing “but a single
bit of data from a single master device to a single slave device.” (Bennett,
col. 15, ll. 43-44.) The Decision also points to a 16 word bit embodiment in
a memory slave device having 37 total pins. (See Bd. Dec. 4.) Bennett’s
Figure 3 discloses options for 1, 2, 4, 6, 8, 16, or 32 bit words and a similar
number of data lines. (See Bennett Fig. 3, Configuration Parameters VII,
VIII.) Bennett states that preferred embodiments range from “37 down to 3
pins in various configurations.” (Bennett, col. 65, ll. 54-56.)
The Decision also finds as follows:
B2. Figure 38 shows “memories device” 3802c and
3802d connected to a “Versatile Bus.” (Col. 97, ll. 8-10.) In the
next paragraph, Bennett refers to “VSLI chips hav[ing] access
to all Versatile Bus lines and therefore, the Versatile Bus
protocols.” (Id. at 11.20-22.)
Bennett elsewhere refers to “memory devices” including,
but not limited to, a ROM: “Not all memory devices can
perform all operations; for example, read only memory (ROM)
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cannot execute the write operations.” (Col. 90, 1. 66 to col. 91,
1. 2.) Bennett then refers to “[s]ample memory operations in the
following paragraphs” (col. 90 [sic: 91], ll. 4-5) and thereafter
describes “relatively small fast memories, and, larger and
relatively slower memories” (col. 92, 11. 13-14).
Bennett also refers to “VLSIC chip devices” and in the
next full sentence (under the “Section 4.1” heading) states that
“[m]any, if not most, applications of VLSIC technology are
likely to include memory devices.” (Col. 90, 11.42-43.) Bennett
discusses these chip devices, including memory devices, as
employing the interconnection standards outlined generally in
Section 3, and more specifically in Section 4 of Bennett.
(Bd. Dec. 4-5.)

As the Decision finds, Bennett’s passages supra show that Bennett
discloses a single chip memory device, including “relatively small fast
memories, and, larger and relatively slower memories” which Bennett
describes as having differences in terms of the number of pins, speed, and
perhaps functionality in some cases. (See Bennett, col. 94, col. 26-33.)
Rambus’s argument that Bennett does not disclose a single chip
memory device, if accepted, would also incorrectly mean that the well-
known single chip ROM (read only memory), which Bennett refers to in
describing “not all memory devices” (as quoted in the Decision passage
supra), is not a single chip memory device. By referring to a ROM, a
known single chip, as within the subset of “memory devices,” Bennett also
implicitly, but clearly, refers to other single chip memory devices which can
execute both read and write commands.
As noted, Bennett refers to relatively small fast memories and larger
relatively slower memories in the paragraph following the ROM (i.e., chip)
discussion. In other words, Bennett implies other well-known single chip
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“memory devices” that can perform write executions. (See Bennett, col. 90,
ll. 66-68.) Hynix II similarly relies, inter alia, on this Bennett ROM
disclosure, as explained further below, in deciding to present to the jury, the
question of whether or not Bennett discloses a DRAM (single chip) memory
device.
While Rambus argues that at various times, Micron or Samsung
admitted that the “large memory” in Bennett refers to multiple chips on a
card, Rambus’s citations show that Micron or Samsung did so only in the
context of the alternative broader reading of the claimed “memory device”
as embracing multiple chips. Micron did not admit that a “large memory”
cannot also refer to a single chip. To the contrary, as Micron contends, “no
party disputes that Bennett discloses a system that includes multiple chips.”
(Reh’g Comments 7.)3 In line with Micron’s position, as noted, Bennett

3 Despite faulting the Board for relying on Hynix II as discussed supra,
Rambus relies on Hynix II and states that “Micron’s expert had to concede
that Bennett’s memory is made of multiple chips in order to argue that
Bennett discloses a plurality of arrays.” ( Reh’g Req. 11.) Hynix II reasons
as follows: “To establish that Bennett discloses a memory device with a
plurality of memory arrays, Mr. McAlexander refers to the ‘large memory’
discussed above. Bennett Chart, C-14. In so doing, he concedes that such a
large memory would have been composed of multiple chips . . . .” Hynix II
at 1337. But without the “Bennett Chart C-14,” the context is not clear, as
the Manufacturers reasonably could have been asserting a broad and/or
alternative claim construction and/or reading of Bennett as regards the large
memory. Still further, the court finds that “Rambus has not raised a question
of fact with respect to Bennett’s ‘small fast memories’.” Id. As another
example, Rambus refers to Samsung’s Inter Partes Request at 43 in
reexamination control no. 95/001,106, which also includes an attached
Bennett claim chart. (See Reh’g Req. 15.) But in that claim chart, Samsung
also asserts that Bennett discloses “Versatile Bus Interface Logics at each
chip.” (See control no. 95/001,106, Samsung IP Request, Bennett Claim
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implies a large memory is a relatively slower chip having fewer pins than a
fast memory device.
Rambus also argues that Bennett’s disclosure of a 40 nanosecond fast
memory could not be a reference to a single chip because Bennett discloses
CMOS processes for the VBI and that “one of ordinary skill in the art would
have recognized that fast memory would have been fabricated using
different processes such as bipolar or emitter coupled logic.” (Reh’g Req.
16 (citing Supp. Murphy Decl. ¶¶ 33-34).) This argument, even if accepted,
simply shows that skilled artisans would have known that the VBI, which
Bennett discloses as “upon the same chip substrate” as the VLSIC
“Memory” (see Bd. Dec. 4 (quoting Bennett)), could be made with other
processes, and that they knew how to make fast chip devices - whether using
other processes or some combination involving CMOS – which corresponds
to merely a preferred embodiment in Bennett. (See Bennett, col. 13, ll. 21-
23; PTAB 2012-000169 Rehearing Decision 9 (citing evidentiary patents
U.S. 3,955,269 and 4,484,388 relied upon by Micron to show that “the
combination of CMOS and bipolar logic on the same chip” was well known
at the relevant time).)
In addition, despite whatever speed or other constraints may have
existed at the time of Bennett filing, Bennett is presumed to be enabling for

Chart at Exhibit H (discussing claim 16 in US 6,266,285).) Rambus also
cites to another reexamination proceeding (Reh’g Req. 15 (citing control no.
95/001,133 at 30)), but that shows a similar context: Rambus refers to
Micron’s statement about “‘memory devices to be used in a large memory to
be a reference to DRAM.’” (Reh’g Req. 15 (citation omitted.) This
sentence shows that Micron deems Bennett’s memory device to be a single
chip DRAM, but it does not show that Micron admits that all references to
Bennett’s large memory implies a memory card.
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all that it teaches, even if it is forward looking in the context of expected
speed increases and numbers of pins for future chip devices (see Bd. Dec. 4
(pin numbers); Bennett col. 9, l.20 to col. 10, l. 29 (present and future pin
numbers and speed)), and Rambus’s evidence relies on the wrong time
frame. Rambus challenges the related Board decision for pointing out that
Murphy relies on the wrong time frame to describe what skilled artisans
would have understood about Bennett. (See Reh’g Req. 15 n.10 (citing
BPAI 2012-000169 at13 n.8).)
Rambus’s challenge relies on paragraphs in Murphy’s two
declarations which opine “from the perspective . . . of the 1990 [‘916 patent
effective filing] date.” (Reh’g Req. 15 n. 10.) But those generic paragraphs
have nothing to do with Murphy’s testimony about Bennett’s fast memory.
Rather, in testifying about Bennett’s fast memory, Murphy states that “I am
not aware of any 16-bit wide memory chips in the Bennett timeframe . . . .”
(Murphy Decl. ¶ 97 – attached to Rambus’s Brief in the BPAI 2012-000169
proceeding.) Rambus similarly maintains that no single 16 bit memory
chips were in existence in the Bennett time frame according to Murphy (see
Reh’g Req. 15), but this does not show that Bennett does not disclose such
chips as forward looking or what was available at the time of the invention.
Bennett discloses chips ranging from 1 to 32 bits as noted supra. Murphy
also does refute that 8 bit DRAM chips were in existence even in the
Bennett time frame and does not opine that memory chips could not have
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been built using the preferred CMOS process even at the Bennett
timeframe.4
Under Rambus’s logic, Bennett does not even disclose or enable a 2,
4, or 8 bit memory chip, and only discloses single bit chips “aggregated on a
memory card.” (See Reh’g Req. 15.) In addition to Figure 3 disclosing 1, 2,
4, 8, or 16 word configurations, Bennett refers to Figure 32 as representing a
4-bit address width fast memory which may be a “sole slave on a Versatile
Bus.” (Col. 93, ll. 13-26.) Rambus’s view of Bennett’s disclosure is overly
restrictive of the high level of skill in the art as evidenced by the voluminous
record of prior art and expert testimony at trial and in the form of
declarations.
Rambus does not address whether these memory chips having a
relatively fewer number of pins (e.g., 3-8 data and address pins) could have
responded quickly, for example, within 40 nanoseconds even at the Bennett
time frame – assuming arguendo that the earlier time frame is relevant to the
analysis of what Bennett teaches to skilled artisans. If a memory card can
respond quickly, then certainly, the memory chips on such cards must be
able to respond just as quickly or more quickly – apparently, according to
Rambus’s implied arguments, the memory chips each respond with a fewer
number of data pins (i.e., less data) which the card interface effectively
aggregates into more effective parallel data pins. (See Reh’g Req. 15.)

4 See BPAI 2012-000169 decision at 12-13 (finding that “Rambus does not
dispute Micron's contention that 8-bit wide DRAM chips were well known
memory chips at the time of the invention (and prior to that during Bennett's
time frame.”).
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Hynix II relies on Bennett’s disclosure of generic memory chips and
leaves the DRAM question to a jury:
Bennett discusses ROMs while explaining the limited number
of operations that can be done with a memory device, and it
does so to point out that memories like ROMs cannot receive
write operations. . . .Bennett’s discussion thus impliedly
discloses some type of memory device than can receive write
operations. The jury will have to determine at trial whether
that implied disclosure encompasses a dynamic random access
memory.

Hynix II at 1137 (emphasis added).)

Based on the foregoing discussion, Rambus does not show that the
Decision overlooks a material point in finding that Bennett discloses a single
chip memory.
Representative Value
Rambus maintains that the Decision overlooks findings by the
Examiner and misapprehends Bennett in finding that Bennett discloses the
claim 26 “value which is representative of a number of clock cycles of the
external clock signal to transpire before sampling a first portion of data.”
(Reh’g Req. 2-10.) Micron responds and shows that the Decision does not
overlook or misapprehend a material point related to Bennett and this
claimed delay value. (See Bd. Dec. 6-8 (B5-B6), 11-18; Reh’g Comments
2-4.) Micron’s Rehearing Comments are adopted and incorporated by
reference.
As the Decision points out, this claim phrase lacks a meaningful point
of reference from which to measure the transpired time. (See Bd. Dec. 12,
18.) Rambus fails to show error in this claim interpretation. (See Reh’g
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Req. 5.) Despite this lack of a recited starting frame of reference in claims
26 and 28, the Decision primarily explains how Bennett satisfies the claims
based on a frame of reference defined by “receipt of an operation code” –
i.e., a frame of reference which Rambus maintains the claims require based
on an improper incorporation of limitations from the ‘916 Patent disclosure.
(See id.)
Rambus maintains that Bennett’s Figures 25a-h do not refer to
memory, inter alia, because “they do not show any address information”
(Reh’g Req. 5) while other figures, such as Figures 34 and 36, show fast or
large memory devices (see id. at 5-7). This argument does not appear in
Hynix II which relies on the same Bennett figures to explain how memory
devices operate, see, e.g., Hynix II at 1133, though Rambus, without
explanation, now describes Judge Whyte’s findings as “incorrect references
to ‘memory devices.’” (Reh’g Req. 5.)
Moreover, Rambus does not show what the Board misapprehends in
finding that “Figures 25a-h, depict timing diagrams for slave devices” (Bd.
Dec. 6 (see Bennett, col. 85, ll. 17-82 (describing Slave Identification)),
thereby implying chip memory slave devices in light of Bennett's teachings
directed toward memory chips discussed supra. (See also Bd. Dec. 14
(relying partially on the District Court findings).) Figures 25a-h, described
in Section 3 in Bennett, describe generic informational transactions in chips
on a bus, whereas Figures 31-36, described in Section 4 in Bennett, describe
more “specific kinds of information[al]” (Bennett, col. 90, l. 34) transactions
for “subsets of connected VLSIC chip devices” (id. at ll. 40-41.) (See id. at
col. 90, ll. 26-35.) The absence of a specific discussion in Bennett of
address lines with respect to the generic memory devices (i.e., the relatively
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full set of VLSIC chip devices) in Figures 25a-h means nothing, because in
addition to Bennett’s reference to slave devices, Bennett’s system
specifically envisions treating much of the multiplexed information as
generic data, including address information – the varied information travels
over the same data lines.5
Rambus also faults the Decision for referring to different
configurations in Figure 25a-h as different embodiments. (Reh’g Dec. 2.)
But Rambus’s arguments amount to a red herring. The Decision does refer
to the figures as different embodiments but also refers to the “different
configurations”: “Micron also persuasively explains that Bennett's Figures
25a, 25b, and 31- 36 . . . signify different configurations for memory devices
and that Bennett's system knows the specific timing relationship for each
protocol configuration.” (Bd. Dec. 14.)
Rambus does not dispute this underlying rationale or the specific
finding that in Figures 25a-h, the number 1 always results in a two clock
cycle delay for DATA after a write request, and the programmable number 3

5 “The bracketing of data communication within some of these operations
into ‘function’ and ‘data’ is meant to highlight that the sample memory may
be receiving addresses, operation codes . . . and the like as ‘Slave
Identification/Function information’ . . . but this need not be so. The sample
memory may receive this ‘function’ information as data. As may be
surmised, the manner of receipt is purely a function of the communications
convention adopted by the interconnected devices, and the resultant
configuration of the Versatile Bus.” (Col. 90, ll. 50-61 (emphasis added).)
Bennett specifically refers to “Slave/Identification and Function,”
arbitration, and data transfers in relation to Figures 25a-h – i.e., in context,
reading from and writing data to slave memory chips. (See generally
Bennett, col. 74-77; col. 85, ll. 15-20.) “[N]o other chips need be aware of
this agreement . . . .” (Bennett, col. 74, l. 53.)
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always results in a one clock delay for DATA after a write request. (See Bd.
Dec. 5, 11-13; Bennett Figures 25a-h.)6 In fact, Rambus agrees with it, but
asserts that by looking only at Figure 25, the Board erred. (See Reh’g Req. 6
(arguing that “limiting the analysis to a comparison of only Figures 25a and
25b would be an error”).) But Rambus simply fails to explain why
anticipation cannot be shown by the configurations represented in Figure 25
(i.e., configurations represented by Figures a-h).
Rambus also contradicts itself by making the confounding dual
arguments that “‘Figures 25a-h do not relate to memory’” (Reh’g Req. 5) but
that “nothing in Bennett suggest the various configurations in shown in
Figures 25a, 25b, 25c, . . . 25h, 35, and 36 constitute different
embodiments” (Reh’g Req. 2). Each of the different configurations in the
noted figures represents a differently configured memory device – as they
must where Rambus maintains they represent the same embodiment and
concedes that some of the figures represent memory.
As discussed supra and in the Decision and supra, Figures 25a-h
relate to generic slave devices including slave memory devices with the
other figures representing more specific memory devices and transactions.

6 Rambus states that Figure 25b “shows no delay cycles between providing
the request on the ID/Function lines and transmission of data.” (Reh’g Req.
4.) Rambus does not explain that this shows a lack of anticipation as to
Figure 25. Any distinction is one of semantics: The Board refers to “one
clock delay” after the write request where Rambus refers to “no delay
cycles” because the data comes immediately one clock cycle after the
request. “Data transfers begin after Wait if multiplexed, or simultaneously
with Wait if pipelined . . . .” (Bennett, col. 77, ll. 40-41.) (The “pipeline”
refers to transferring the wait signal to its own designated pin so that
waiting, otherwise required with multiplexing over the same lines, is not
required.)
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Rambus fails to show that the Board overlooked the finding that Figures
25a-h show anticipation, regardless of what the other figures show. (See Bd.
Dec. 14-15.)
As the Decision indicates, Micron’s Appeal Brief, comparing a
modified Figure 36 to Bennett’s original Figure 36 (i.e., comparing the
Configuration Parameter values 3 and 1), also shows that in addition to the
Figure 25 embodiment (or configuration(s)), the Figure 36 embodiment also
satisfies the disputed value in the claim. (See Bd. Dec. 15-16 (citing App.
Br. 14).) Rambus’s arguments do not show that the Board overlooked a
material point with respect to that embodiment.
Rambus takes issue with a related Decision finding regarding Figure
36 and argues that Bennett’s additional “associated control” to maintain a
fixed delay relationship between Data and the Wait signal shows error.
(Reh’g Req. 4 n. 4.) But Rambus does not explain persuasively why claim
26 precludes additional associated control. As Micron points out, the ‘916
patent’s disclosed system and Bennett’s system necessarily interprets its own
coding scheme based on values or codes stored elsewhere than in a single
register – i.e., not necessarily solely on one configuration parameter or delay
value. (See Reh’g Comments 3.) In other words, the ’916 patent employs a
similar interrelated coding system for the “representative” “block size
information” in claim 26 as discussed further below – i.e., a coded value
depends on another value so that the same code may represent different
block values. (See Reh’g Comments 3.) Rambus’s counter arguments about
these “representative” codes fail to show that the Board overlooked a
material point and rely on Bennett’s generic Figure 3 which has little or
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nothing to do with the issues presented. (See Reh’g Req. 9-10 (discussing
“Bennett’s preferred embodiment” at 10).)
Based on the discussion supra, and notwithstanding that Figures 25a-h
and Figure 36 each separately satisfies the claimed delay value, even if
Figure 36 is compared to Figure 25 as Rambus urges, changing the
Configuration Parameter VI from 3 to 1still satisfies the claimed
“representative” relationship. Rambus compares the configuration
parameter 3 in Figure 36 to that in Figure 25b and argues that the former
creates no delay and the latter creates a three cycle delay – relative to the
Function (read or write) command. Even if the comparison is valid, Rambus
over-simplifies and mischaracterizes what skilled artisans would have
garnered from Bennett.7 Essentially treating the address word as a first data
word in Figure 36 as Bennett implies and the Decision explains (Bd. Dec.
15-16) shows that it occurs at the same time relative to the Function
command as the data word does in Figure 25b – i.e., concurrent with the
Wait signal and immediately after the Function command. (See note 7.)

7 Figure 36 shows address and data information following the Wait signal
and Rambus maintains that the configuration value does not show when the
data transfers relative to the Wait signal – i.e., since the two address words
come first, before the two data words. Bennett’s Figure 36 corresponds to a
large memory system of up to 232 addresses of 32 bit words. But to the VBI
system, 32 bit address and data bit words look like “4 sixteen bit words.”
(See Bennett, col. 95, ll. 59-64; see also note 5.) And Bennett’s system
knows exactly which two groups of these sixteen bit groups constitutes the
two address groups and their timing relation to the two following data
groups – the whole purpose of Bennett’s system is to transfer data. (See Bd.
Dec. 14 (Bennett’s protocol knows “when (in what relationship and/or
sequence)”.)
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Rambus’s arguments directed to Figure 35 also fail to show an overlooked
point.8
Rambus also characterizes Judge Whyte’s analysis in Hynix II as
supporting its position regarding the representative value. (See Reh’g Req.
5.) But Judge Whyte in Hynix II only ruled on a summary judgment motion,
“drawing all inferences in favor of [non-movant] Rambus” in construing the
term “representative” and left the ultimate determination of the meaning to
the jury. See Hynix II at 1134. Judge Whyte reasoned, in denying the
Manufacturer’s (i.e., including Micron) motion, that the word
“representative” implies some level of recognition by another. (See Hynix II
at 1134.) But Judge Whyte and the Decision factually agree: “[T]he value
of Parameter VI still determines the ‘write latency’ that will exist in the . . .
memory operations.” Hynix II at 1134. Stated differently, with respect to
“the amount of delay between the slave ID/function and data activities[, t]hat
delay is determined by the status of the wait signal.” Hynix II at 1134.
Rambus also relies on Bennett’s Figure 3 and asserts that “[n]othing
in Bennett limits Configuration Parameter VI to 1 and 3.” (Reh’g Req. 4, n.
3.) But Rambus fails to explain how this shows an overlooked point. The
Decision states that Figures 25a-h only use 1 and 3, and Rambus does not

8 Rambus argues that Figure 35 reveals “an indeterminate amount of time
before data is output by the memory” even if the device does win arbitration
the first time. (Reh’g Req. 9.) But even if Figure 35 is relevant to the
inquiry, it shows, after winning arbitration, the same data to function delay
as other memory devices using a 3 for Parameter VI (e.g., Figures 25b).
(See Bennett, col. 95, ll. 18-27; Bd. Dec. 17-18.) Rambus’s other argument
that not winning arbitration shows a lack of a correlation is not
commensurate in scope with the claims which do not require arbitration.
(See Reh’g Req. 9.)
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dispute that finding or address the specific findings in Bennett showing that
1 and 3 are preferred values for that parameter. (See Bd. Dec. 6 -B5; 13.)
Moreover, as the Decision, Hynix II, and even Rambus recognizes, a
parameter value of 1 (signifying multiplexing) predictably results in an
additional clock cycle relative to all other possible values 2-5 (signifying
different numbers of wait lines, including zero). (See Bd. Dec. 13-14 n.7
(citing Rambus’s Resp. Br. at 5; Hynix II at 1133-34).)
Since the wait parameter VI determines the delay value as the
Decision finds (in agreement with Hynix II), based on this record, in light of
the ‘916 patent, it is “representative” of the claimed delay. (See below for
further discussion of “representative” in light of the ‘916 patent and the
analogous representative block size information.) Even if some recognition
of that determination is required to satisfy the product claims at issue here,
skilled artisans would have recognized the relationship based on the
discussion above which shows its consistently predictable nature in
determining a relative one clock cycle delay at least within different
configurations of the Figure 25a-h memory device and the Figure 36
memory device – if not the same delay across these embodiments for the
same configuration parameter VI.
Block Size Information
Rambus contends that Bennett does not disclose the claimed block
size information recited in claim 26. (Reh’g Req. 10-14.) Rambus’s
contentions fail to show that the single word read satisfies the claim
limitation. The Examiner, the District Court, and the Decision all agree as to
this single word read in Bennett. (See Bd. Dec. 18-20.)
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Similar to the contentions supra about the “representative” delay
value relationship, Rambus contends that Figures 32 and 36 show different
representative block size information transferred for the same configuration
parameters VII and VIII of 5 and 5. (Reh’g Req. 11.) This argument
improperly compares two different embodiments as noted supra and in the
Decision. But even if the comparison is proper, Figure 36 represents a
special case in Bennett which transfers a 16 bit word over two successive
data cycles. (See Bd. Dec. 19.) Rambus attempts to create confusion by
ignoring what skilled artisans would have gleaned from Bennett and refer to
the two-clock cycle word transfer in Figure 36 as a “single word transfer” so
as to compare it to the same in Figure 32. (See Reh’g Req. 11.) But in each
separate configured embodiment, each of which use some of the same
parameter values, as the Decision explains, the separately configured
memory devices each know what is being transferred. Hence, even though
Figure 36 transfers two “16 bit data words” over two data cycles (which can
be viewed as a “32 bit data word on two clock cycles” (i.e., excluding the
first two 16 bit word blocks of address information, see Bd. Dec. 19-20), the
configuration parameter VII and VIII values 5 and 5 in that embodiment not
only “is representative of the amount of data to be output,” as claim 26
requires, it “dictates” the total 32 bit word transfer. (See Bennett, col. 96, ll.
27-29.)
Similarly, as indicated at the outset, in other configurations, Bennett’s
system transfers 1, 2, 4, 8, or 16 bit words over one data cycle based on
specific configuration parameter VII and VIII values, thereby specifying the
claimed block size as set forth in the claim – i.e., even if Figure 36 presents a
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special case or otherwise does not satisfy claim 26. (See Bd.Dec. 19;
Bennett Fig. 3.)
Rambus also contends that Bennett proves a lack of anticipation by
stating, inter alia, that the “‘seventh configuration dimension is the format—
the partitionment in pins times cycles as equals bits—of data words and is
not the amount thereof.’” (Reh’g Req. 12 (quoting Bennett at col. 96, ll. 39-
41).) But as explained in the Decision and above, the configuration
parameters VII and VIII together dictate the amount of data in a word.
Rambus has not shown that the Board, which relies on Hynix II, overlooks
anything that would otherwise disturb this finding. (See Bd. Dec. 18-20.)
As the District Court found, “[i]ndisputably, parameters VII and VIII specify
the total amount of data that will be transferred in response to two basic
types of transaction requests.” Hynix II at 1139 (emphasis added).) The
court compared the ‘916 patent Specification to Bennett in finding the block
size information term satisfied: “Analogously, when Parameter VII equals
VIII, the two parameters ‘specify’ that one data word will be transferred in
response to basic read and write operations.” Id.
Rambus also relies on a passage that states that the “Versatile Bus
knows naught of this information.” (Reh’g Req. 12 (quoting Bennett at col.
96, ll. 39-41).) This passage only refers to the special case in Figure 36 of
multiple word transfers and which does require some “associated control” as
Rambus points out and as discussed supra. (See Reh’g Req. 4 n. 4.)
Moreover, the passage only shows that Bennett’s Versatile Bus does not
know how much data is transferred because it “is simply handling data.”
(Bennett, col. 96, ll. 40-41.) On the other hand, the VBI, the Versatile Bus
Interface on each chip, does know how much data to transfer, and controls
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the operation based on the configuration; i.e., “‘the what (what operations),
when (in what relationship and/or sequence)’.” (See Bd. Dec. 14 (quoting
Bennett at col. 39, ll. 31-34).) “In FIG. 36 a Versatile Bus of 43153355
configuration has handled a block of 4 sixteen bit data words.” (Bennett,
col. 96, ll.40-42.)
Bennett makes clear that with respect only to the large memory
represented in Figure 36, “the configuration that four total cycles should be
utilized requires naught but some associated control between the Versatile
Bus Interface Logic(s) and User(s).” (Bennett, col. 96, ll. 33-36.) And even
if claim 26 precludes such minimal (“naught”) “associated control,” which it
does not, in any given system contemplated by Bennett wherein such
minimal control sets the total number of clock cycles for the block data
transfer, the specific (e.g., 43153355 for Fig. 36) configuration ultimately
dictates both the word length and time delay within that configured
embodiment, thereby satisfying claim 26. Viewed another way, the Figure
36 species may include different subspecies each of which have different
“associated control,” for example, 4 total clock cycles, 8 total clock cycles,
etc., but within each subspecies, the configuration parameters VI, VII, and
VIII dictate the delay and block size.
Therefore, contrary to Rambus’s related assertions (Reh’g Req. 8, 11-
12), Tehrani v. Hamilton Med. Inc., 331 F.3d 1355, 1361 (Fed. Cir. 2003)
does not support Rambus’s position that the Board’s interpretation of
“representative” is too broad. Bennett’s parameters VI, VII, and VIII not
only represent the delay time and block size information as discussed, they
dictate that time and size in a direct manner. As such, contrary to Rambus’s
assertion, Bennett’s parameters do not constitute “any [non-representative]
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case in which the two items are [merely] related in some way.” See id.
Rather, Bennett’s configuration parameter values represent, “‘symbolize’,”
or “‘stand for’,” see id., the delay time and block size - since they dictate
that time and size. Skilled artisans, given the parameter values and
specifically configured embodiment (including any associated control if a
large memory subspecies of Figure 36 is implemented) as described in
Bennett, would be able to directly determine the delay time and block size
from those parameters.
Most importantly, this interpretation comports with the ‘916 patent as
indicated above in the discussion regarding the term “representative” – used
twice in claim 26 as indicated supra. In the ‘916 patent, skilled artisans
must know which code of several “other block size encoding schemes” will
be used to determine the block size. (See ‘916 patent, col. 11, ll. 66-67.)
Also, in addition to these other encoding schemes, as Micron points out,
even in the preferred embodiment of the ‘916 patent, “the same 3-bit pattern
can represent two different block sizes.” (Reh’g Comments 3.) In other
words, without knowing the particular encoding scheme or first code bit in
the ‘916 patent, skilled artisans could not determine the block size
“representative” value. As such, the term “representative” as used in the
‘916 patent does not preclude dependency on other information or control.
The busy signal alternative theory of anticipation as regards the block
size information is not required to satisfy the claims. Therefore, the Board
hereby does not consider that alternative theory further, and abandons it
here, as it is not necessary to the Decision as noted there. (See Reh’g Req.
13; Bd. Dec. 20-21.)

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Other Contentions
In a footnote, Rambus alleges that the Board did not address other
claim features in claim 26. (See Reh’g Req. 20, n. 13.) Relying on its
Respondent Brief to support its truncated argument, Rambus asserts that the
Decision does not address “[f]or example, clock receiver circuitry to receive
an external clock signal” and “first input receiver circuitry to sample block
size information synchronously with respect to the external clock signal.”
Id.
As to the first clause, Rambus asserts that Bennett does not disclose a
memory device that includes such “clock receiver circuitry to receive an
external clock signal” because “any clock signal” would only be received by
Bennett’s VBI which is separate from Bennett’s memory chips. (See
Rambus Resp. Br. 15 (cited at Reh’g Req. 20 n. 13).) This argument is just
another version of the single chip argument. It fails to show error in the
Examiner’s RAN or Micron’s Appeal Brief, upon which the Decision relies,
and which address the asserted elements. (See Micron App. Br. 7
(addressing “Element [a]” and citing RAN at 89-90).)
As to the second clause, like the first clause, Rambus points to the
Respondent Brief at 15-16 to support the argument, but Rambus’s
Respondent Brief there does not argue that Bennett fails to disclose “first
input receiver circuitry.” So it is not clear what part of the clause Rambus
asserts is missing. Nonetheless, Micron’s Rebuttal Brief points out that
Rambus elsewhere makes what amounts to a similar argument, and Micron
shows that the argument relies on the same asserted lack of a single chip in
Bennett –i.e., Rambus asserts that Bennett’s VBI is not part of the memory
chip. (See Micron Reb. Br. 7 (citing “Rambus Resp. Br. at 5”); see also
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Micron App. Br. 7-9.) Micron also points to its Inter Partes “Request at 13-
14” (see Micron App. Br. 8) and the Request at 14 states that “the
configuration register is programed using input receivers that sample the
block size information synchronously” as disclosed in “Bennett at Col. 125,
lines 46-56.” Rambus’s truncated rehearing arguments fail to show the
Board overlooked a material point. Rambus does not maintain that
Bennett’s VBI does not have some receiver circuitry to receive the block
size information synchronously and store it in the configuration register.
(See Bd. Dec. 8 (B7) (finding synchronous clocked sampling in Bennett).)
Rambus’s other arguments in the Respondent Brief possibly alluded
cited in the Rehearing Request footnote focus on an alleged lack in Bennett
of “‘to sample block size information synchronously with respect to the
external clock signal . . . in response to a first operation code”.” (See
Rambus Resp. Br. 16.) As indicated, Rambus’s truncated, shifting, and
unclear arguments render it difficult to determine what Rambus contends the
Board overlooks. In any event, as Micron explains, and without any
persuasive dispute by Rambus, the Read operation, a function code in
Bennett, corresponds to the first operation code in claim 26. (See App. Br.
8; Bd. Dec. 13, 17 (discussing Bennett’s FUNCTION and READ signals).)

Claim 28
Rambus relies on arguments presented for claim 26 and asserts that
the Board improperly shifts the burden to Rambus as to other elements
recited in claim 28. (See Reh’g Req. 20-21.) Rambus maintains that
“Rambus also presented evidence showing that one of ordinary skill in the
art would not have considered serially shifting bits to correspond to storing a
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value in a register in response to a second operation code.” (Reh’g Req. 21
(citing Supp. Murphy Decl. ¶ 54).)
Rambus appears to be alleging that Bennett does not disclose the
second operation code recited in claim 28. But Rambus refers to Bennett’s
“control signals on the VM Node Interface [which] must be held at a
particular level.” (Reh’g Req. 21.) Rambus acknowledges that Micron relies
on these “SET DATA” control signals for the second operation code. (See
Resp. Br. 17 (citing App. Br. at 16).) Murphy also only concludes, without
explanation or adequate support, that “serially shifting bits in such a
manner” does not satisfy claim 28, and fails to explain adequately, if at all,
why the “control signals” in Bennett do not satisfy the claimed second
operation code. (See Murphy Decl. ¶ 54.) The Board relies on Micron’s
citations and explanation in reaching its Decision and reasons that Micron
“explains persuasively, in line with the Examiner, how Bennett satisfies the
second operation code.” (Bd. Dec. 21.) The Decision notes that “Rambus’s
contentions do not explain how storing a value in a register in response to a
second operation code is patentably distinct from shifting bits [the values]
into registers pursuant to the [second operation code] signals in Bennett.”
(Bd. Dec. 21.)
Rambus still does not explain why Bennett fails to satisfy the claim 28
limitations. As the Decision points out, the Examiner relies on independent
claim 26 in deciding not to reject of claim 28. (Bd. Dec. 21 (citing RAN
104-105).) While the Examiner appears to have interpreted the recited
second operation code more broadly (see RAN 105) than Micron, the
Examiner does not refute Micron’s more narrow reading of that code onto
Bennett’s control signals. As such, Rambus had the burden to show error in
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the Examiner’s ultimate finding that but for the above-discussed
representative “value” limitation in claim 26, Bennett satisfies claim 28.
And even if Micron had the burden to show anticipation as to claim 28
elements raised by Rambus, Micron met that burden; i.e., “persuasively” as
the Decision reasons. (See Bd. Dec. 21.)9

CONCLUSION
Micron’s contentions are more persuasive than Rambus’s contentions.
Rambus fails to show that the Board overlooked or misapprehended a
material point in reversing the Examiner’s decision not to reject claims 26
and 28.
REHEARING DECISION
We decline to modify the Decision reversing the Examiner’s decision
not to reject claims 26 and 28.

DENIED

ack

9 The Board’s related decision, PTAB 2012-2081 at 23-24, explains further
why the recited second operation code in a similar claim does not require
bits or a packet and is broad enough to read on Bennett’s control signals,
which reasonably correspond to information bits in any case.

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