DULUK, Jerome F. et al.

Patent Trials and Appeals BoardDec 3, 2019

14055345 - (D) (P.T.A.B. Dec. 3, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/055,345 10/16/2013 Jerome F. DULUK JR. NVDA/SC-12-0563- US0-US2 5165 102324 7590 12/03/2019 Artegis Law Group, LLP/NVIDIA 7710 Cherry Park Drive Suite T #104 Houston, TX 77095 EXAMINER LEE, CHUN KUAN ART UNIT PAPER NUMBER 2181 NOTIFICATION DATE DELIVERY MODE 12/03/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ALGdocketing@artegislaw.com jmatthews@artegislaw.com kcruz@artegislaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JEROME F. DULUK, JR., CAMERON BUSCHARDT, SHERRY CHEUNG, JAMES LEROY DEMING, SAMUEL H. DUNCAN, LUCIEN DUNNING, ROBERT GEORGE, ARVIND GOPALAKRISHNAN, MARK HAIRGROVE, HENGHUAN JIA, and JOHN MASHEY Appeal 2019-000307 Application 14/055,345 Technology Center 2100 Before ERIC S. FRAHM, KRISTEN L. DROESCH, and MICHAEL T. CYGAN, Administrative Patent Judges. DROESCH, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1, 3–10, and 12–21. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as NVIDIA Corporation. Appeal Br. 3. Appeal 2019-000307 Application 14/055,345 2 CLAIMED SUBJECT MATTER The claims are directed to a fault buffer for tracking page faults in a unified virtual memory system. See Spec. ¶ 2. Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A system for tracking page faults, the system comprising: a central processing unit (CPU) comprising a CPU memory management unit (MMU); one or more memories storing a CPU page table and a parallel processing unit (PPU) page table; a parallel processing unit (PPU) comprising a PPU MMU, a first streaming multiprocessor, and a second streaming multiprocessor, wherein the PPU: executes a first instruction that is associated with a first virtual memory address, determines that the PPU page table does not include a first mapping associated with the first virtual memory address, and transmits a first fault buffer entry to a fault buffer in response to determining that the PPU page table does not include the first mapping, wherein the fault buffer stores fault buffer entries received from only the PPU, the fault buffer including both the first fault buffer entry and a second fault buffer entry at a first point in time, the first fault buffer entry including an indication that the first streaming multiprocessor caused a corresponding page fault, and the second fault buffer entry including an indication that the second streaming multiprocessor caused a corresponding page fault. Appeal 2019-000307 Application 14/055,345 3 REFERENCES The prior art relied upon by the Examiner is: Name Reference Date Fleming et al. US Patent 6,961,840 B2 Nov. 1, 2005 Ginzburg et al. US 2014/0304559 A1 Oct. 9, 2014 Sharp et al. US 2014/0075060 A1 March 13, 2014 Ronen et al. US 2013/0268804 A1 Oct. 10, 2013 Deming et al. US 2011/0072235 A1 March 24, 2011 REJECTIONS Claims 1, 3, 6–10, 12, and 15–21 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Fleming et al. (“Fleming”), Deming et al. (“Deming”), Ginzburg et al. (“Ginzburg”), and Ronen et al. (“Ronen”). Final Act. 2–8. Claims 4, 5, 13, and 14 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Fleming, Deming, Ginzburg, Ronen, and Sharp et al. (“Sharp”). Final Act. 8–10. OPINION Appellant disputes the Examiner’s findings that the combination of Fleming, Deming, Ginzburg, and Ronen, teach or suggest a parallel processing unit (PPU) that “transmits a first fault buffer entry to a fault buffer in response to determining that the PPU page table does not include the first mapping,” where the fault buffer stores fault buffer entries received from only the PPU, the fault buffer including both the first fault buffer entry and a second fault buffer entry at a first point in time, the first fault buffer entry including an indication that the first streaming multiprocessor caused a corresponding page fault, and the second fault buffer entry including an indication that the second streaming multiprocessor caused a corresponding page fault, Appeal 2019-000307 Application 14/055,345 4 as recited in claim 1. See Appeal Br. 10; Final Act. 2–8. Appellant argues claims 1, 3–10, and 12–21 together as a group. See Appeal Br. 10–15. Consequently, we choose claim 1 as representative of the group. 37 C.F.R. 41.37(c)(1)(iv) (2017). Appellant contends that Ginzburg fails to disclose any techniques that implement a fault buffer that includes both a first fault buffer entry and a second fault buffer entry at a first point in time, where the first fault buffer entry includes an indication that a first streaming multiprocessor caused a corresponding page fault, and the second fault buffer entry including an indication that a second streaming multiprocessor caused a corresponding page fault. Appeal Br. 10; Reply Br. 3. Appellant asserts that, in Ginzburg, all page faults are associated with a single processor. See Appeal Br. 10–11; Reply Br. 3–4. Appellant further contends that Ginzburg is silent about receiving page faults from two different streaming multiprocessors and page fault entries associated with the page faults are included in a buffer at a first point in time. See Appeal Br. 11; Reply Br. 4. Appellant’s argument is not persuasive of error because the Examiner does not rely on Ginzburg alone for teaching or suggesting the fault buffer including both the first fault buffer entry and a second fault buffer entry at a first point in time, the first fault buffer entry including an indication that the first streaming multiprocessor caused a corresponding page fault, and the second fault buffer entry including an indication that the second streaming multiprocessor caused a corresponding page fault, as recited in claim 1. The Examiner relies on Ginzburg, for teaching a CPU MMU and transmitting a first fault buffer entry to a fault buffer, wherein the fault buffer stores fault buffer entries received by combining multiple page faults being processed together in combination with Fleming’s teaching of Appeal 2019-000307 Application 14/055,345 5 page fault transmission in association with the first processing entity, and in combination with the PPU architecture of Deming. See Final Act. 4 (citing Ginzburg ¶¶ 4, 5, 34–38, 107–114). Instead, the Examiner relies on the teachings of Fleming, Deming, and Ginzburg, in combination with Ronen for teaching the aforementioned limitation of claim 1. See Final Act. 4–5. In regard to the teachings of Ronen, Appellant argues that claim 1 expressly requires a single buffer that includes multiple entries, and that the Examiner erred by trying to map the single buffer structure of claim 1 to two different buffer structures disclosed in Ronen. See Appeal Br. 12; Reply Br. 5. Appellant asserts that Ronen discloses multiple buffers are implemented, and each core (i.e., multiprocessor) in Ronen is associated with a different buffer. See Appeal Br. 11–12; Reply Br. 4–5. Appellant argues that a single buffer structure that has multiple entries has non-obvious advantages over the multiple buffer architecture disclosed in Ronen. See Appeal Br. 12; Reply Br. 6. Appellant’s arguments are not persuasive of Examiner error because claim 1 does not recite or otherwise require a single buffer. Claim 1 merely recites “a fault buffer.” “[A]n indefinite article ‘a’ or ‘an’ in patent parlance carries the meaning of ‘one or more’ in open-ended claims containing the transitional phrase ‘comprising.’” KCJ Corp. v. Kinetic Concepts, Inc., 223 F.3d 1351, 1356–57 (Fed. Cir. 2000) (“[u]nless the claim is specific as to the number of elements, the article “a” receives a singular interpretation only in rare circumstances when the patentee evinces a clear intent to so limit the article. . . . In the present case, neither the claim nor its context suggests an exceptional meaning for the article.”). Here, the Specification describes the fault buffer 216 as storing a number of fault buffer entries 502. Spec. ¶ 67. The fault buffer may be part of a virtual memory system 600. Id. ¶ 68. The Appeal 2019-000307 Application 14/055,345 6 function of the fault buffer is thus to store multiple buffer entries. Appellant does not identify, nor do we locate, any limitation in the Specification of the fault buffer to a single discrete article. See generally, Appeal Br.; Reply Br. Appellant points to paragraphs 8, 105, and 106 of the Specification as allegedly showing advantages of a single buffer. Reply Br. 8. Paragraphs 8 and 106 state, “[a]nother advantage is that a fault buffer is provided that allows faults generated by the PPU to be coalesced for efficient execution.” Paragraph 105 states, “PPU fault handler[] examines the contents of the fault buffer to resolve the page faults. Providing a fault buffer allows the PPU fault handler to ‘coalesce’ page faults executed by the PPU.” Although the Specification makes clear that “coalescing” faults provides efficient execution, the Specification does not require coalescence into a single discrete article to achieve the purported advantage. See generally Spec. In the absence of a clear limitation to a single discrete article, the recitation of “a fault buffer” carries the meaning of “one or more fault buffers,” and “the fault buffer” carries the meaning of “the one or more fault buffers.” Ronen is relied upon by the Examiner for teaching or suggesting “the fault buffer” through its use of a set of “N order buffers” to store fault buffer entries. See Final Act. 4–5. Therefore, we agree with the Examiner’s finding that Ronen’s N order buffers, which function as a group to store multiple fault buffer entries, teach or suggest “a fault buffer” and “the fault buffer,” recited in claim 1. See Final Act. 4–5; Ans. 12. Related to the previous arguments, Appellant contends that Ronen does not disclose each page fault entry stored in the single buffer includes an indication of which core caused the page fault corresponding to that given Appeal 2019-000307 Application 14/055,345 7 page fault entry.2 See Appeal Br. 11; Reply Br. 4, 7. Appellant argues that Ronen necessarily fails to disclose that each page fault entry includes an indication of which core caused the page fault corresponding to that page fault entry because such an indication is unnecessary given the one-to-one buffer/core relationship taught by Ronen. See Appeal Br. 11; Reply Br. 4, 7. Appellant asserts that, although Ronen generally discloses that a status is associated with an instruction and may indicate that a page fault has occurred when executing that instruction, Ronen does not disclose that this status (i.e., indication) is included in a page fault entry, or that the status indicates which core caused a particular page fault, as required by the claim language. See Appeal Br. 11–12; Reply Br. 4–5. Appellant’s arguments are not persuasive of Examiner error because they are not commensurate in scope with the language of claim 1. Claim 1 does not recite or require the buffer entries stored in a buffer to include an indication (i.e., the indication itself is included in the buffer entry). As explained by the Examiner, Ronen’s 1st Order Buffer to Nth Order Buffer teaches the claimed “a fault buffer” or “the fault buffer,” and each N order buffer corresponds to or indicates the N cores for tracking inflight transactions, such as whether a page fault has occurred for the corresponding core. See Ans. 12–13 (citing Ronen ¶¶ 23, 25); see also Final Act. 5 2 We note that Appellant’s Specification does not disclose explicitly “a fault buffer including both the first fault buffer entry and a second fault buffer entry at a first point in time,” and “the first fault buffer entry including an indication that the first streaming multiprocessor caused a corresponding page fault, and the second fault buffer entry including an indication that the second streaming multiprocessor caused a corresponding page fault.” See, e.g., Spec. ¶¶ 32–36, 85–100. Appeal 2019-000307 Application 14/055,345 8 (explaining that “a first of the N order buffers including a page fault status indication for a corresponding first core,” and “a second of the N order buffers including page fault status indication for a corresponding second core.”). Stated another way, due to the correspondence of the N order buffers to the N cores, when a particular one of the N order buffers of Ronen includes information identifying whether a page fault has occurred, the existence of that page fault information on a particular N order buffer provides an indication of the corresponding N core that caused the page fault. For the foregoing reasons, Appellant has not demonstrated that the Examiner erred in rejecting claims 1, 3–10, and 12–21. CONCLUSION We affirm the Examiner’s rejections of claims 1, 3–10, and 12–21 under 35 U.S.C. § 103 (a). In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 3, 6–10, 12, and 15– 21 103(a) Fleming, Deming, Ginzburg, and Ronen 1, 3, 6–10, 12, and 15– 21 4, 5, 13, and 14 103(a) Fleming, Deming, Ginzburg, Ronen, and Sharp 4, 5, 13, and 14 Overall Outcome 1, 3–10, and 12–21 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). Appeal 2019-000307 Application 14/055,345 9 AFFIRMED