Dirk Wendel et al.Download PDFPatent Trials and Appeals BoardSep 4, 201914445237 - (D) (P.T.A.B. Sep. 4, 2019) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/445,237 07/29/2014 DIRK WENDEL AM20966EH 2332 34814 7590 09/04/2019 NXP-LARSON NEWMAN, LLP 6501 William Cannon Drive West Austin, TX 78735 EXAMINER SADLER, NATHAN ART UNIT PAPER NUMBER 2139 NOTIFICATION DATE DELIVERY MODE 09/04/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ip.department.us@nxp.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte DIRK WENDEL, OLIVER BIBEL, JOACHIM FADER, and WILHARD CHRISTOPHORUS VON WENDORFF ____________________ Appeal 2018-007721 Application 14/445,2371 Technology Center 2100 ____________________ Before JOSEPH L. DIXON, JAMES W. DEJMEK, and STEPHEN E. BELISLE, Administrative Patent Judges. DEJMEK, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of claims 1–6, 8–18, and 20. Appellants have canceled claim 19. See App. Br. 20. The Examiner has objected to claim 7 as being dependent upon a rejected base claim, but has indicated this claim would be allowable if rewritten in independent form. See Final Act. 17. We have jurisdiction over the remaining pending claims under 35 U.S.C. § 6(b). We reverse. 1 Appellants identify NXP USA, Inc. as the real party in interest. App. Br. 1. Appeal 2018-007721 Application 14/445,237 2 STATEMENT OF THE CASE Introduction Appellants’ disclosed and claimed invention generally relates to “detecting failures in a cache-coherent multiprocessor system.” Spec. 1:7–8. In a disclosed embodiment, Appellants describe a multiprocessor system comprising a plurality of memory caches, a shared memory resource, a coherency unit, and a monitoring unit. Spec. 6:13–8:6, Fig. 1. According to the Specification, the coherency unit “secures the coherency of the data/instructions stored in the first cache and the second cache when a processing unit accesses them for further calculations.” Spec. 5:13–15. When a first copy of the cached region that is stored in the first cache 24 is altered by the first processing unit 12, the coherency unit 28 may mark and/or update the corresponding copy of the cached region in the second cache 26 to manage such conflicts and maintain consistency between cache and memory. Spec. 7:10–13; see also Fig. 1. In addition, “the monitor unit may check whether a region of the shared memory resource that is assigned exclusively to a specific processing unit is altered by another processing unit and/or vice versa.” Spec. 5:23–25. Claim 1 is illustrative of the subject matter on appeal and is reproduced below with the disputed limitation emphasized in italics: 1. A cache-coherent multiprocessor system comprising a first processing unit and a second processing unit, a shared memory resource accessible by the first processing unit and the second processing unit, the shared memory resource being divided into a shared region, a first region assigned to the first processing unit, and a second region assigned to the second processing unit, a first cache related to the first processing unit, Appeal 2018-007721 Application 14/445,237 3 a second cache related to the second processing unit, a coherency unit adapted to secure the cache-coherency of the cache-coherent multiprocessor system, to determine that a first copy of data stored in the first cache is altered, to update an original copy of the data stored in the shared region to match the altered first copy of data in response to the first copy of data being altered, and to update a second copy [of] data stored in the second cache to match the altered first copy of data and the updated original copy of the data in response to the first copy being altered, and a monitor unit adapted to generate an error signal, when the coherency unit affects the first region due to a memory access from the second processing unit and when the coherency unit affects the second region due to a memory access from the first processing unit. The Examiner’s Rejections2 1. Claims 1–3, 8, and 13 stand rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Franke et al. (US 6,449,699 B2; Sept. 10, 2002) (“Franke”). Final Act. 3–10. 2. Claims 4–6, 9–11, and 14–16 stand rejected under 35 U.S.C. § 103 as being unpatentable over Franke and Pádraig Brady, Updating the Bios using linux (2013), www.pixelbeat.org/ docs/bios/ (“Brady”). Final Act. 10–15. 3. Claims 12 and 17 stand rejected under 35 U.S.C. § 103 as being unpatentable over Franke and Karlapalem et al. (US 8,732,408 B2; May 20, 2014) (“Karlapalem”). Final Act. 15. 2 The Examiner has rejected claim 19 under 35 U.S.C. §§ 103 and 112(b). Final Act. 2–3, 16. Because Appellants have canceled claim 19 (see Amend. 7 (filed December 1, 2017)), these rejections are moot and, accordingly, we do not include claim 19 in the listed rejections. Appeal 2018-007721 Application 14/445,237 4 4. Claims 18 and 20 stand rejected under 35 U.S.C. § 103 as being unpatentable over Franke and Chaudhry et al. (US 2002/0152420 A1; Oct. 17, 2002) (“Chaudhry”). Final Act. 16. ANALYSIS3 Rejection under 35 U.S.C. § 102(a)(1) Appellants dispute the Examiner’s finding that Franke anticipates, inter alia, independent claim 1. App. Br. 5–10; Reply Br. 2–4. In particular, Appellants assert claim 1 requires a coherency unit to do two things in response to determining a first copy of data stored in a first cache has been altered—update the second copy of data stored in a second cache, and update the original copy of the data store in shared memory. App. Br. 5–6. Appellants argue Franke, as relied on by the Examiner, fails to disclose that a second copy of data in a second cache is updated in response to the first copy being altered. App. Br. 6–10; Reply Br. 2–4. Instead, Appellants argue the relied upon memory transactions of Franke are self-contained and are not performed in response to one another. App. Br. 7–10; Reply Br. 2–4. Franke generally relates to “providing fault contained memory partitioning in a cache coherent, symmetric shared memory multiprocessor system while enabling fault contained cache coherence domains as well as cache coherent inter partition memory regions.” Franke, col. 3, ll. 28–32. In a disclosed embodiment, all memory accesses are intercepted and processed 3 Throughout this Decision, we have considered the corrected (Supplemental) Appeal Brief, filed December 1, 2017 (“App. Br.”); the Reply Brief, filed July 23, 2018 (“Reply Br.”); the Examiner’s Answer, mailed June 1, 2018 (“Ans.”); and the Final Office Action, mailed April 12, 2017 (“Final Act.”), from which this Appeal is taken. Appeal 2018-007721 Application 14/445,237 5 to verify the address is within the memory region assigned to the particular processor. Franke, col. 3, ll. 36–40. If the address is outside the assigned memory region, the operation is aborted. Franke, col. 3, ll. 36–40. “Consistency of the cache coherency domains is achieved through a protocol performing address verification concurrently with the bus snooping protocol.” Franke, col. 3, ll. 49–51. Franke describes, inter alia, three memory transactions—ReadLine, ReadWithIntentToModify, and WriteLine. Franke, col. 5, ll. 6–20. The Examiner finds these memory transactions disclose determining a first copy of data stored in a first cache has been altered and updating both a second copy of the data stored in a second cache and the original copy of the data stored in a shared region of memory in response to the first copy being altered. See Final Act. 4–5 (citing Franke, col. 5, ll. 9–29). Franke describes the three memory transactions as: ReadLine: Reads a line into the cache 102 of the issuing CPU 101. If the cache 102 is owned by another CPU 101, that processor will respond with data. If not owned by another processor 101 the memory will respond. ReadWithIntentToModify: Similar to ReadLine reads a line into the cache 102 of the issuing processor 101. The line is invalidated in all other processor 101 caches 102 resulting in an inter cache 102 transfer and no write back to memory 111 occurring. Otherwise memory 111 responds. WriteLine: Write a cache line back to memory 111. No snooping takes place. A cache line may only be written back to memory 111, if the cache line is already owned by the processor 101. Ownership can only be achieved via a previous ReadWithIntentToModify. Franke, col. 5, ll. 6–20. Appeal 2018-007721 Application 14/445,237 6 The Examiner finds the ReadWithIntentToModify discloses determining that a first copy of data stored in a first cache has been altered. Final Act. 4–5; Ans. 4. In addition, the Examiner finds the WriteLine transaction discloses updating an original copy of data stored in a shared region of memory. Final Act. 5. Further, the Examiner finds the ReadLine transaction discloses updating a second copy of the data stored in a second cache. Final Act. 5; Ans. 4–5. The Examiner explains the “three separate requests” (i.e., memory transactions) are performed in response to one another and that “ownership of the cache line is the causal link between the separate requests.” Ans. 5–6. “A claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference.” Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628, 631 (Fed. Cir. 1987). Additionally, to anticipate, a prior art reference must disclose more than “multiple, distinct teachings that the artisan might somehow combine to achieve the claimed invention.” Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008); see also In re Arkley, 455 F.2d 586, 587 (CCPA 1972) (“[T]he [prior art] reference must clearly and unequivocally disclose the claimed [invention] or direct those skilled in the art to the [invention] without any need for picking, choosing, and combining various disclosures not directly related to each other by the teachings of the cited reference.”). We agree with Appellants that Franke discloses three separate memory transactions. Although there is a relationship between some of the requests (i.e., ownership of the cache line), the Examiner has not provided sufficient evidence or persuasive technical reasoning that the WriteLine (i.e., Appeal 2018-007721 Application 14/445,237 7 updating an original copy of data in a shared region) and ReadLine (i.e., updating a second copy of data in a second cache) are executed “in response to” a ReadWithIntentToModify (i.e., updating a first copy of data in a first cache) transaction. Our reviewing court has stated the phrase “‘[i]n response to’ connotes that the second event occur in reaction to the first event.” Am. Calcar, Inc. v. Am. Honda Motor Co., 651 F.3d 1318, 1340 (Fed. Cir. 2011). Instead, the Examiner suggests that the second copy is not updated until “a subsequent read is executed by the second processing unit.” Ans. 4. Thus, the second copy of data is not updated “in response to” the first data being altered, as recited in claim 1, but rather in response to a subsequent read by a second (different) processing unit. For the reasons discussed supra and constrained by the record before us, we do not sustain the Examiner’s rejection under 35 U.S.C. § 102(a)(1) of independent claim 1. Additionally, we do not sustain the Examiner’s rejections of claims 2 and 3, which depend therefrom. For similar reasons, we do not sustain the Examiner’s rejection of independent claims 8 and 13, which recite commensurate limitations. Rejections under 35 U.S.C. § 103 Claims 4–6, 9–12, 14–18, and 20 depend directly or indirectly from independent claims 1, 8 and 13. The Examiner does not rely on the additionally cited references to cure the deficiency of Franke related to the independent claims, discussed above. Accordingly, constrained by the record before us, we do not sustain the Examiner’s rejections under 35 U.S.C. § 103 of claims 4–6, 9–12, 14–18, and 20. Appeal 2018-007721 Application 14/445,237 8 DECISION We reverse the Examiner’s decision rejecting claims 1–3, 8, and 13 under 35 U.S.C. § 102(a)(1). We reverse the Examiner’s decision rejecting claims 4–6, 9–12, 14–18, and 20 under 35 U.S.C. § 103. REVERSED Copy with citationCopy as parenthetical citation