Cavium, LLC

Patent Trials and Appeals Board

Aug 18, 2021

2020003059 (P.T.A.B. Aug. 18, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/540,656 11/13/2014 Robert A. Sanzone MP12638/3795.1154-000 7595
114350 7590 08/18/2021
Hamilton, Brook, Smith & Reynolds, P.C.
Cavium
530 Virginia Rd.
Concord, MA 01742
EXAMINER
TSAI, SHENG JEN
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
08/18/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@hbsr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte ROBERT A. SANZONE, WILSON P. SNYDER II,
and RICHARD E. KESSLER
____________________

Appeal 2020-003059
Application 14/540,656
Technology Center 2100
____________________

Before JOHN A. EVANS, JUSTIN BUSCH, and
JOHN P. PINKERTON, Administrative Patent Judges.

PINKERTON, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1–12. We have jurisdiction under 35 U.S.C. § 6.
We AFFIRM.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies Marvell International Ltd. as the real
party in interest. Appeal Br. 2.
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STATEMENT OF THE CASE
Introduction
Appellant generally describes the disclosed and claimed invention as
relating to “a circuit configured to manage and enforce order among multiple
independent threads of requests to a memory.” Spec. ¶ 2.2
Claims 1 and 7 are independent. Claim 1, which is reproduced below,
is representative of the subject matter on appeal:
1. A memory control circuit comprising:
a device interface configured to:
receive a plurality of access requests to access a memory
from a plurality of devices;
parse each of the plurality of access requests to retrieve a
respective transaction identifier, the transaction identifier
1) being associated with a device originating the request and
2) identifying a thread of access requests to which the access
request belongs, the thread of access requests requiring
completion in a specific order; and
update a plurality of ordered lists stored concurrently to
the memory control circuit, each of the plurality of ordered lists
having entries corresponding to the access requests associated
with a distinct transaction identifier, the entries being ordered
according to the specific order; and
a memory interface configured to:
update a top list stored by the memory interface, the top
list being an ordered list including entries from each of the
plurality of ordered lists stored concurrently to the memory
interface;

2 Our Decision refers to the Final Office Action mailed June 13, 2019
(“Final Act.”); Appellant’s Appeal Brief filed Nov. 13, 2019 (“Appeal Br.”)
and Reply Brief filed Mar. 17, 2020 (“Reply Br.”); the Examiner’s Answer
mailed Jan. 24, 2020 (“Ans.”); and the Specification filed Nov. 13, 2014
(“Spec.”).
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populate the top list in an order that 1) alternates among
the entries from each of the plurality of ordered lists, and 2)
maintains the specific order of each of the plurality of ordered
lists; and
forward the plurality of access requests to the memory in
an order corresponding to the top list.
Appeal Br. 12 (Claims App.).
Rejections on Appeal
The Examiner rejects claims 1–12 under the following grounds:
Claims 35 U.S.C. § Reference(s) Citation
1, 5, 7, 11 103 Strongin,3 Marietta4 Final Act. 8–19
2–4, 8–10 103 Strongin, Marietta, White5 Final Act. 19–21
6, 12 103 Strongin, Marietta, Loh6 Final Act. 21–22

ANALYSIS
We have reviewed the Examiner’s rejections of claims 1–12 in light
of Appellant’s arguments in the Appeal Brief and the Reply Brief. See
Appeal Br. 4–11; Reply Br. 2–8. Any other arguments Appellant could have
made, but chose not to make, are waived. See 37 C.F.R. § 41.37(c)(1)(iv)
(2019). For the reasons discussed below, Appellant’s arguments are not
persuasive of error by the Examiner. Unless otherwise indicated, we agree
with, and adopt as our own, the Examiner’s findings of fact and conclusions
as set forth in the Final Office Action from which this appeal is taken and in

3 US 6,546,439 B1 (issued Apr. 8, 2003, “Strongin”).
4 US 2010/0325327 A1 (published Dec. 23, 2010, “Marietta”).
5 US 6,859,208 B1 (issued Feb. 22, 2005, “White”).
6 US 2013/0297906 A1 (published Nov. 7, 2013, “Loh”).
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the Answer. Final Act. 2–22; Ans. 3–17. We provide the following
explanation primarily for emphasis.
Appellant argues independent claim 1 and states that the rejections of
claims 2–12 are improper for the reasons set forth for claim 1. See Appeal
Br. 4–11. Accordingly, we select claim 1 as representative, and the
remaining claims stand or fall with claim 1. See 37 C.F.R. § 41.37(c)(1)(iv).
The Examiner rejects claim 1 under 35 U.S.C. § 103 for obviousness
based on Strongin and Marietta. Final Act. 8–18; see also Ans. 3–17.
Appellant argues Examiner error for the following reasons:
(1) the cited references fail to teach or suggest “parse each
of the plurality of access requests to retrieve a respective
transaction identifier . . . identifying a thread of access requests
to which the access request belongs, the thread of access requests
requiring completion in a specific order” (Appeal Br. 4–6; Reply
Br. 2–4);
(2) the cited references fail to teach or suggest “update a
top list . . . , the top list being an ordered list including entries
from each of the plurality of ordered lists stored concurrently to
the memory interface”7 (Appeal Br. 7–8, 10–11; Reply Br. 4–5,
7–8);
(3) a prima facie case of obviousness has not been
established because the rejection cites a reference improperly
(Appeal Br. 8–9; Reply Br. 5–6); and
(4) it would not be obvious to combine Strongin and
Marietta in the manner suggested by the rejection, and such

7 For reasons similar to those given for the “update a top list” limitation,
Appellant argues the cited references also fail to teach or suggest “a memory
interface configured to. . . populate the top list in an order that 1) alternates
among the entries from each of the plurality of ordered lists, and 2)
maintains the specific order of each of the plurality of ordered lists.” Appeal
Br. 10–11; Reply Br. 7–8.
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combination would still fail to provide Applicant’s invention
(Appeal Br. 9–10; Reply Br. 6–7).
We consider these arguments below, but we are not persuaded that the
Examiner erred.
1. “parse each of the . . . access requests to retrieve a respective
transaction identifier . . . identifying a thread of access requests”
Appellant argues the cited references fail to teach or suggest “parse
each of the plurality of access requests to retrieve a respective transaction
identifier, the transaction identifier . . . 2) identifying a thread of access
requests to which the access request belongs, the thread of access requests
requiring completion in a specific order,” as recited in claim 1. Appeal Br.
4–6; Reply Br. 2–4. With respect to Strongin, Appellant argues that its
“source attributes” and “source indications” are not “transaction
identifier[s]” that are components of or associated with an access request,
but instead these elements are generated by the memory controller based on
the bus that carried the access request. Reply Br. 3; Appeal Br. 5 (citing
Strongin 8:57–67, 10:1–6, claims 1, 14). Appellant also argues that
Strongin’s indicator 300 does not identify a particular thread of access
requests; instead, it merely identifies the source of a request. Appeal Br. 5–6
(citing Strongin Fig. 3 (item 300)). With respect to Marietta, Appellant
argues that its transfer IDs are for sorting requests into request queues, and
are not associated with a particular thread of access requests requiring
completion in a specific order. Id. at 6 (citing Marietta Fig. 8, ¶ 40).
We are not persuaded of error because the Examiner’s findings show
that Strongin at least suggests the “parse” limitation as recited. E.g., Ans. 7–
8 (citing Strongin 8:58–9:15, 9:59–10:13, Fig. 5, claim 9). Figure 5 of
Strongin is reproduced below.
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Figure 5 of Strongin depicts a system that uses queues dedicated to each bus
for servicing memory access requests. Strongin 5:48–53, 9:59–10:13. As
shown in Figure 5, memory access requests from CPU bus 115 are deposited
in CPU bus queue 500, memory access requests from accelerated graphics
port (“AGP”) interconnect 102 are deposited on AGP interconnect queue
502, and memory access requests from PCI bus 118 are deposited in PCI bus
queue 504. Id. at 9:63–10:1. “Thus, due to their association with the
various bus[s]es, queues 500–504 convey information about the sources of
queued memory transactions,” and memory controller 200 can then use such
information to make decisions relative to the order in which queued memory
requests will be serviced. Id. at 10:1–6.
Information made available to memory controller 200 may also
include an identification of an initiator of a request and whether or not
requested access can be completed out of order. Id. at 8:58–9:2. Using such
information, memory controller 200 can re-order memory transactions to
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substantially maximize memory efficiency. Id. at 9:3–6. “For example,
memory controller 200 may group transactions from a single data source
together, and may present these transactions to data chip (memory array)
130, while other transactions that were issued by a different initiator earlier
may be held back.” Id. at 9:6–10.
The fact that memory controller 200 can group memory transactions
by source indicates that the controller has certain information that identifies
and distinguishes the group of memory transactions by its source. See id.
Strongin therefore teaches or suggests a transaction identifier made available
to memory controller 200 for identifying the thread of access requests to
which the access request belongs. See id. Strongin also teaches that such
access requests require completion in a specific order because the memory
controller can service requests using information such as whether requested
access can be completed out of order. See Strongin 8:58–9:2; see also id. at
Fig. 4 (item 302, “Order Important? Y/N”), claim 9. And while the memory
controller may have received the respective transaction identifiers from
various system interfaces, Strongin at least suggests that those identifiers
were based on identifying information found by examining or “pars[ing]”
the memory access requests themselves in order for the system to be able to
group the requests by source. See id.
We find the Examiner’s interpretation of the term “parse” as
“examine” to be reasonable. Appellant does not propose its own
interpretation of the term, much less a limiting interpretation that would
preclude “examining” the access memory requests as Strongin suggests. See
Ans. 5–6. Nor does the Specification define the term “parse” or specifically
explain what it means to “parse” a memory access request. In fact, the word
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“parse” appears only twice in the Specification. See Spec. ¶¶ 2, 30. First,
the Specification describes that “[t]he device interface may operate to
receive a plurality of access requests to access a memory from a plurality of
devices, and parse each of the access requests to retrieve a respective
transaction identifier (TID).” Id. ¶ 2. Second, the Specification describes
that “[t]he IOBN[8] also parses a virtual address portion of the access request
and forwards the virtual address to the SMMU 180 for translation (720).”
Id. ¶ 30. These descriptions, however, do not define the term “parse” in any
limiting way, nor do they explain how a device interface or IOBN may
“parse” an access request. See id. ¶¶ 2, 30.
Thus, we are not persuaded of error because we find the cited
descriptions of Strongin at least suggest to “parse each of the . . . access
requests to retrieve a respective transaction identifier” as recited.
2. “update a top list . . . including entries from each of the plurality
of ordered lists”
Appellant argues that Strongin’s memory operation buffer 336, which
the Examiner finds teaches a “top list,” receives memory access requests
from multiple different sources, but is not populated with access requests
from ordered lists. Appeal Br. 7 (citing Final Act. 14; Strongin Figs. 1, 3
(item 336), 8:26–50). Appellant also acknowledges that Strongin describes
memory access requests (“CPU Memory Access 1,” “Read Request 1”), but
argues that such requests are sent from the devices to the buffer rather than
stored in a list at a device interface. Id.
We are not persuaded of error. Rather, we agree with the Examiner
that Strongin teaches or at least suggests the disputed claim limitation. See

8 Input/output bridge. See Spec. ¶ 15.
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Final Act. 14 (citing Strongin Fig. 2, Fig. 3 (items 300, 336), 8:34–9:16);
Ans. 10–12. We agree with the Examiner that Strongin’s description of a
sequence of memory access requests for each source teaches “a plurality of
ordered lists” as recited. See Final Act. 12–13 (citing Strongin, Fig. 1).
Figure 1 of Strongin is reproduced below.

Figure 1 of Strongin depicts an example of an AGP-enabled data processing
system. Strongin 5:29–33. As shown in Figure 1, each source (CPU, Read,
PCI Bus, 1394 Device, Network Memory Card) has a sequence of memory
access requests numbered from 1 to N based on transmission order. Id. at
6:54–66, 7:26–40, 7:66–8:10.
Figure 3 of Strongin is reproduced below.
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Figure 3 of Strongin depicts an embodiment in which information available
at various system interfaces is carried all the way to the memory controller.
Id. at 5:41–44. As shown in Figure 3, requester memory operation buffer
336 has been populated with a sequence of indicators 300 identifying certain
memory access requests from each of the source-specific lists shown above
in Figure 1 of Strongin. See id. at 9:21–25. In particular, Strongin’s
requested memory operation buffer 336 illustrates a sequence identifying the
following memory access requests: “CPU Memory Access 1,” “AGP Read
Request 1,” “PCI Bus Device 150 Memory Access 1,” “1394 Device
Memory Access 1,” “CPU Memory Access 2,” “AGP Read Request 2,” and
“1394 Device Memory Access 2.” Id. at Fig. 3 (items 300, 336).
In view of Figure 3 and its associated description, we agree with the
Examiner that Strongin teaches or at least suggests “a top list . . . being an
ordered list including entries from each of the plurality of ordered lists.” See
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Final Act. 14. Strongin also describes the counter-clockwise “round-robin”
servicing of requests across different sources, which suggests that when a
memory access request is serviced, or a new memory access request is made,
the requested memory operation buffer is updated to remove or include that
entry. See Strongin 8:26–57. In addition, Strongin’s memory controller can
re-order memory transactions, which also suggests updating the requested
memory operation buffer to account for that change.
Thus, we are not persuaded the Examiner erred in finding the
combination of Strongin and Marietta teaches or suggests to “update a top
list . . . including entries from each of the plurality of ordered lists” as
recited.
For reasons similar to those given for the “update a top list”
limitation, Appellant argues the cited references also fail to teach or suggest
“a memory interface configured to. . . populate the top list in an order that 1)
alternates among the entries from each of the plurality of ordered lists, and
2) maintains the specific order of each of the plurality of ordered lists.”
Appeal Br. 10–11; Reply Br. 7–8. In view of our analysis above for the
“update a top list” limitation, we are not persuaded by this argument either.
3. Prima facie case of obviousness
Appellant argues a prima facie case of obviousness has not been
established because the rejection on appeal cites a reference improperly.
Appeal Br. 8–9; Reply Br. 5–6. In particular, Appellant argues that Strongin
does not teach or suggest “storing the access requests prior to their receipt at
the buffer 136.” Appeal Br. 8. Appellant also argues that Strongin’s labels
do not actually exist, nor are they possible, in Strongin’s system. Appeal Br.
8.
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Appellant’s arguments do not persuade us that the Examiner failed to
establish a prima facie case of obviousness. Appellant’s first argument
attacks Strongin, but the Examiner relies on Marietta for teaching the
storage-related elements of claim 1, including the concept of storing of a
plurality of ordered lists concurrently. See Final Act. 16–18 (citing Marietta
Figs. 7, 8, ¶¶ 40, 41); Ans. 12–13. For example, the Examiner finds that
Marietta’s “incoming memory requests are received by the crossbar (702)
and then concurrently stored in 3 request queues.” Ans. 12–13 (citing
Marietta Fig. 7). The test for obviousness is not that the claimed invention
must be expressly disclosed in any one or all of the references but rather,
what the combined teachings of the references would have suggested to
those of ordinary skill in the art. In re Keller, 642 F.2d 413, 426 (CCPA
1981).
Appellant’s second argument fares no better. Regardless of whether
Strongin’s system actually uses labels like those used in the figures for
identifying memory access requests and their sources, these labels are
representative of how Strongin’s system works and, moreover, they identify,
order, and group memory access requests such that they at least suggest “a
plurality of ordered lists” and “a top list” as claimed. See Final Act. 12–14
(citing Strongin Figs. 1, 2, 3 (items 300, 336), 8:34–9:16); Ans. 10–12. To
find otherwise would abandon the principle that “[a]ll of the disclosures in a
reference must be evaluated for what they fairly teach [to] one of ordinary
skill in the art,” as “a reference is not limited to the disclosure of specific
working examples.” In re Boe, 355 F.2d 961, 965 (CCPA 1966); In re
Mills, 470 F.2d 649, 651 (CCPA 1972); see also In re Mouttet, 686 F.3d
1322, 1331 (Fed. Cir. 2012).
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4. Combination of Strongin and Marietta
Appellant argues it would not have been obvious to combine Strongin
and Marietta in the manner suggested by the Rejection, and that such
combination would still fail to provide Appellant’s invention. Appeal Br. 9–
10; Reply Br. 6–7. In particular, Appellant argues that the proposed
combination would not have been obvious because Strongin’s buffer 136
and Marietta’s request queues 704, 706 perform the same function—serving
buffer requests. Appeal Br. 9. Appellant also argues that, although the
proposed combination would employ a single buffer (Strongin) or three
parallel buffers (Marietta), neither reference suggests connecting two request
buffers in series. Id.
We are not persuaded of error. The Examiner relies on Marietta
merely for teaching the concept of storing ordered lists concurrently to the
memory control circuit or interface. See Final Act. 16–18 (citing Marietta
Figs. 7, 8, ¶¶ 40, 41); Ans. 12–13. Accordingly, the Examiner reasons that
incorporating this feature into Strongin’s system would have been obvious to
one of ordinary skill in the art “because Marietta teaches [that] doing so
allows flexible assignments of incoming memory access requests to the
plurality of lists based on the sources or other arrangements.” Final Act. 17–
18 (citing Marietta Figs. 7, 8). Contrary to Appellant’s arguments, the
Examiner does not propose physically combining the disclosed prior art
systems, nor does an obviousness determination require that. “[A]
determination of obviousness based on teachings from multiple references
does not require an actual, physical substitution of elements,” nor does it
require a secondary reference’s features to be bodily incorporated into the
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structure of the primary reference. Mouttet, 686 F.3d at 1332 (citations
omitted); Keller, 642 F.2d at 425.
5. Conclusion
For the reasons stated above, we are not persuaded the Examiner erred
in rejecting claim 1 under 35 U.S.C. § 103 for obviousness based on
Strongin and Marietta.
Thus, we sustain the Examiner’s rejection of claim 1 under 35 U.S.C.
§ 103 for obviousness based on Strongin and Marietta. For the same
reasons, we sustain the Examiner’s rejections of claims 2–12 under
35 U.S.C. § 103 for obviousness based at least on Strongin and Marietta. As
discussed above, Appellant does not argue the rejections of those claims
beyond the arguments advanced for claim 1.

DECISION
We affirm the Examiner’s rejections of claims 1–12.

SUMMARY
In summary:
Claim(s)
Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1, 5, 7, 11 103 Strongin, Marietta 1, 5, 7, 11
2–4, 8–10 103 Strongin, Marietta, White 2–4, 8–10
6, 12 103 Strongin, Marietta, Loh 6, 12
Overall
Outcome 1–12

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No period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R.
§ 41.50(f).
AFFIRMED