ATI Technologies ULC

Patent Trials and Appeals Board

Mar 25, 2022

2021001425 (P.T.A.B. Mar. 25, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/229,932 08/05/2016 Guennadi Riguer 5800-56800 4576 53806 7590 03/25/2022 Kowert, Hood, Munyon, Rankin & Goetzel (AMD) 1120 S. Capital of Texas Hwy Building 2, Suite 300 Austin, TX 78746 EXAMINER MCCULLEY, RYAN D ART UNIT PAPER NUMBER 2611 NOTIFICATION DATE DELIVERY MODE 03/25/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): patent_docketing@intprop.com ptomhkkg@gmail.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE _____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD _____________ Ex parte GUENNADI RIGUER1 _____________ Appeal 2021-001425 Application 15/229,932 Technology Center 2600 ______________ Before ROBERT E. NAPPI, LARRY J. HUME, and BETH Z. SHAW, Administrative Patent Judges. NAPPI, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. § 134(a) of the Final Rejection of claims 1 through 20. We REVERSE. INVENTION The disclosed and claimed invention is directed to implementing fine- grain power management of the graphical processing unit (GPU) in virtual reality (VR) systems. Abstract, Spec. ¶16. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). According to Appellant, ATI Technologies ULC is the real party in interest. Appeal Br. 2. Appeal 2021-001425 Application 15/229,932 2 Claim 1 is illustrative of the invention and is reproduced below: 1. A system comprising: one or more processors configured to: execute an application, wherein the application specifies a priority of each rendering task of a plurality of rendering tasks for a given virtual reality (VR) frame; logic comprising circuitry configured to: utilize a scale value in a feedback control loop of the application to dynamically adjust a power performance state of the one or more processors; utilize a first power performance state for the one or more processors while performing a first rendering task in a first interval of a period of the given VR frame; and utilize a second power performance state for the one or more processors while performing a second rendering task in a second interval of the period of the given VR frame, wherein the second power state is different from the first power state. REJECTIONS AT ISSUE The Examiner rejected claims 1 through 4, 6, 8 through 11, 13, 15 through 18 and 20 under 35 U.S.C. § 103 as being unpatentable over Vaishampayan (US 2015/0348226 A1, pub. Dec. 3, 2015), Acharya (US 2017/0221173 A1, pub. Aug. 3, 2017), and Law (US 8,924,752 B1, pub. Dec. 30, 2014). Final Act. 3-6.2 2 Throughout this Opinion, we refer to the Appeal Brief, filed October 1, 2020 (“Appeal Br.”), the Reply Brief, filed December 18, 2020 (“Reply Br.”), the Examiner’s Answer, mailed October 29, 2020 (“Ans.”), and the Final Office Action, mailed November 1, 2019 (“Final Act.”). Appeal 2021-001425 Application 15/229,932 3 The Examiner rejected claims 5, 12 and 19 under 35 U.S.C. § 103 as being unpatentable over Vaishampayan, Acharya Law, and Raghavan (US 2016/0018869 A1, pub. Jan. 21, 2016). Final Act. 6-7. The Examiner rejected claims 7 and 14 under 35 U.S.C. § 103 as being unpatentable over Vaishampayan, Acharya, Law, and Bellamkonda (US 2015/0000889 A1, pub. Jan. 1, 2015). Final Act. 7-8. ANALYSIS We have reviewed Appellant’s arguments in the Briefs, the Examiner’s rejection, and the Examiner’s response to Appellant’s arguments. Appellant’s arguments have persuaded us of error in the Examiner’s rejections of claims 1 through 20. Appellant argues that the Examiner’s rejection of independent claims 1, 8 and 15 is in error as the combination of Vaishampayan, Acharya and Law do not teach the feature of a plurality of rendering tasks for a given virtual reality frame where each has a specific priority and performing the rendering of the first rendering task in a first period of the virtual reality frame and rendering the second task during a second period of the virtual reality frame as recited in each of the independent claims. Appeal Br. 9-16, Reply Br. 2-9. The Examiner finds that Vaishampayan teaches that rendering processes are given a higher priority than other process. Ans. 3-4 (citing Vaishampayan ¶ 22). Further, the Examiner finds that the skilled artisan would understand that in Vaishampayan Figure 5A, multiple time slots are associated with a single frame. Ans. 5-6. The Examiner reasons that: Vaishampayan discloses “the device can restrict the lowest or lower priority GPU utilizations. This would decrease the GPU Appeal 2021-001425 Application 15/229,932 4 usage for these lower priorities, but leave the GPU usage for the higher priorities unchanged” (para. 22, emphasis added). Appellant's allegation that each time slot of Fig. SA corresponds to “the rendering of many, many, frames” (Appeal Brief, pg. 13, para. 1) would mean that during time slot “Low Proc 504A,” high priority user-interface rendering tasks would be blocked from execution for “many, many” frames. One having ordinary skill in the art would recognize that blocking high priority rendering tasks for “many, many” frames would be inconsistent with Vaishampayan’s goal of leaving the execution of high priority rendering tasks “unchanged.” Vaishampayan states that when the GPU needs to be throttled (i.e. reduce the processing power) for thermal reasons, it is desirable to first throttle the lower priority processes, while “the GPU operations for higher quality of service (QoS) priority process are not affected” (para. 22). Ans. 5-6. Further, the Examiner states: Acharya also teaches the disputed claim features of having different priority processes executing during a single frame. A “time warp” in the context of virtual reality means that an image is rendered with one process and subsequently updated with another process, all within a single frame (in order to account for head motion that occurs during the time it takes to render the image). Acharya discloses “a GPU preempts executing a low-priority set of commands for a higher-priority set of commands” (para. 14), and additionally “workloads like VR may benefit from a finer granularity of preemption than draw call boundaries to support time-warp (per frame)” (para. 37). In computer graphics, the rendering of a typical image frame may contain millions of draw calls, i.e. individual draw instructions from a graphics application. Therefore, switching from low to high priority rendering tasks using “a finer granularity ... than draw call boundaries” means that the low and high priority tasks switch on a sub-frame basis. This can further be seen in Fig. 3 of Acharya which illustrates low priority rendering command stream 36A and high priority Appeal 2021-001425 Application 15/229,932 5 rendering command stream 36B switching within a single virtual reality frame. Ans. 8. We have reviewed the Examiner’s findings and the cited teachings of the reference cited by the Examiner and are persuaded of error in the Examiner’s rejection of independent claims 1, 8 and 15. The independent claims recite that each of a plurality of rendering tasks for a given frame has a priority, and that during the first interval of a period of a frame a first power performance level for the processor is utilized and during a second interval of a period of a frame a second performance level for the processor is utilized. Thus, the scope of the claim is that during a period of a frame there are at least two rendering tasks of two priority levels, and two power performance levels are used. We concur with the Examiner that that Vaishampayan, in paragraph 22, teaches that rendering processes are given a higher priority than other process. However, paragraph 22 discusses priority of rendering tasks compared to other processes such as batch processes, and does not address different rendering tasks in the same frame having different priority. Thus, the Examiner has not cited sufficient evidence to demonstrate that the combination of the references teaches two rendering tasks with two priority levels as claimed. Further, we do not find that the Examiner has sufficiently demonstrated that either Vaishampayan or Acharya teach performing two rendering tasks in intervals of a period for a frame. The Examiner has not cited, nor do we find that, a teaching in either of the references that discusses a relationship between the frame period and the number of rendering processes in that period. The Examiner’s rationale, reproduced above, as to why the skilled artisan would recognize that the references teach performing Appeal 2021-001425 Application 15/229,932 6 two rendering tasks in intervals of a period for a frame, is based upon speculation and we do not find it to be supported by sufficient evidence. Accordingly, the Examiner has not demonstrated that the combination of Vaishampayan, Acharya and Law teach all of the limitations of independent claims 1, 8 and 15. As such, we do not sustain the Examiner’s obviousness rejection of claims 1 through 4, 6, 8 through 11, 13, 15 through 18 and 20. The Examiner’s rejections of dependent claims 5, 7, 12, 14 and 19 similarly rely upon the disclosure of Vaishampayan, Acharya and Law teach all of the limitations the independent claims. Final Act 6, 8. Further, the Examiner has not shown that the teachings of Raghavan or Bellamkonda make up for the deficiencies in the rejection of the independent claims discussed above. Accordingly, we similarly do not sustain he Examiner’s obviousness rejections of claims 5, 7, 12, 14 and 19. DECISION In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-4, 6, 8-11, 13, 15-18, 20 103 Vaishampayan, Acharya, Law 1-4, 6, 8- 11, 13, 15- 18, 20 5, 12, 19 103 Vaishampayan, Acharya, Law, Raghavan 5, 12, 19 7, 14 103 Vaishampayan, Acharya, Law, Bellamkonda 7, 14 Overall Outcome 1-20 REVERSED