ARM LIMITED

Patent Trials and Appeals Board

Mar 30, 2022

2020005153 (P.T.A.B. Mar. 30, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/938,285 11/11/2015 Vladimir VASEKIN JRL-550-1923 1059 73459 7590 03/30/2022 NIXON & VANDERHYE, P.C. 901 NORTH GLEBE ROAD, 11TH FLOOR ARLINGTON, VA 22203 EXAMINER PETRANEK, JACOB ANDREW ART UNIT PAPER NUMBER 2183 NOTIFICATION DATE DELIVERY MODE 03/30/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): PTOMAIL@nixonvan.com pair_nixon@firsttofile.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte VLADIMIR VASEKIN, IAN MICHAEL CAULFIELD, and CHILODA ASHAN SENARATH PATHIRANE Appeal 2020-005153 Application 14/938,285 Technology Center 2100 Before BARBARA A. BENOIT, DAVID J. CUTITTA II, and MICHAEL J. ENGLE, Administrative Patent Judges. ENGLE, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1-6, 8, and 10-13, which are all of the claims pending in the application. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. 1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies ARM Ltd. as the real party in interest. Appeal Br. 3. Appeal 2020-005153 Application 14/938,285 2 TECHNOLOGY The application relates to “out-of-order program instruction execution” in a processor. Spec. 1. ILLUSTRATIVE CLAIM Claim 1 is illustrative and reproduced below with certain limitations at issue emphasized: 1. An apparatus comprising: processing circuitry to perform data processing operations in response to instructions, wherein the instructions reference architectural registers; register storage circuitry comprising physical registers to store data values for access by the processing circuitry when performing the data processing operations; register rename storage circuitry to store mappings between the architectural registers and the physical registers, and to provide the processing circuitry with a mapping indicating a physical register to use in place of an architectural register specified in an instruction, wherein the register rename circuitry is responsive to identification of a data hazard condition with respect to the architectural register for out-of-order program execution of the instruction to remap the architectural register to an available physical register; reorder buffer circuitry to store an entry for each destination architectural register specified by the instruction, wherein entries are stored in program order and wherein the entry specifies the destination architectural register and an original physical register to which the destination architectural register was mapped by the register rename storage circuitry before the register rename storage circuitry remapped the architectural register to the available physical register; wherein the reorder buffer circuitry is capable of storing an entry for every instruction processed by the processing circuitry, wherein the reorder buffer circuitry is responsive to no Appeal 2020-005153 Application 14/938,285 3 destination architectural register being specified in an instruction to store an entry for which the destination architectural register is specified as a predetermined value which does not indicate an architectural register; and register rename recovery circuitry responsive to an error indication from the processing circuitry to perform a recovery procedure comprising removing a youngest entry from the reorder buffer circuitry and updating the mapping in the register rename storage circuitry for the destination architectural register specified in the youngest entry with the original physical register; wherein the register rename recovery circuitry is responsive to an entry comprising the predetermined value to remove the entry from the reorder buffer without updating the mapping in the register rename storage circuitry. REFERENCES The Examiner relies on the following references as prior art: Name Number Date Chaussade US 2014/0195780 A1 July 10, 2014 Hennessy Computer Architecture: A Quantitative Approach (3rd ed.) 2003 Mylius US 2014/0089638 A1 Mar. 27, 2014 Ogawa US 2004/0255098 A1 Dec. 16, 2004 White US 5,632,023 May 20, 1997 REJECTIONS The Examiner makes the following rejections under 35 U.S.C. § 103: Claims References Final Act. 1-4, 10-13 Ogawa, Chaussade, Hennessy, Official Notice2 2-9 5, 6 Ogawa, Chaussade, Hennessy, Mylius, Official Notice 9-11 8 Ogawa, Chaussade, Hennessy, White 11-12 2 In the Final Office Action, the summary paragraph states that these claims are rejected over the cited prior art references “and selectively in view of Appeal 2020-005153 Application 14/938,285 4 ANALYSIS Claim 1 recites “the reorder buffer circuitry is responsive to no destination architectural register being specified in an instruction to store an entry for which the destination architectural register is specified as a predetermined value which does not indicate an architectural register” and “the register rename recovery circuitry is responsive to an entry comprising the predetermined value to remove the entry from the reorder buffer without updating the mapping in the register rename storage circuitry.” “It is axiomatic that, in proceedings before the PTO, claims in an application are to be given their broadest reasonable interpretation [(‘BRI’)] consistent with the specification.” In re Sneed, 710 F.2d 1544, 1548 (Fed. Cir. 1983). Here, the Examiner finds that “specification page 8 lines 1-3 . . . is the sole paragraph that mentions the term ‘predetermined value’ and only makes mention that the predetermined value does not indicate an architectural register.” Ans. 9. The Examiner therefore determines that “the BRI of ‘predetermined value’ is of a value known in advance that doesn’t indicate an architectural register.” Id. The Examiner relies on Figure 3.31 of Hennessy for teaching the claimed “predetermined value.” Final Act. 5-6. For a specific example supporting memory addresses being interpreted as predetermined values, Hennessy in figure 3.31 shows entry number 3 as a store instruction . . . to store the value in floating-point register four to the memory address in register one. As register one holds the memory address to store the data prior to the store instruction, this memory address is known in advance and reads upon a predetermined value. Page 227 of Hennessy further states that this predetermined memory address Official Notice.” Final Act. 2. However, in the detailed discussion of each claim, Official Notice is only applied against claim 11. Id. at 8. Appeal 2020-005153 Application 14/938,285 5 is stored in the destination field of the store instruction. In addition, during compilation of programs executed on processors such as detailed by Ogawa and Hennessy, memory addresses of loads and stores are assigned predetermined values so that variables can be correctly loaded and stored at known spaces. As such, the memory address of a store instruction reads upon the broadest reasonable interpretation of the claimed predetermined value. Ans. 9. Appellant argues “there is no disclosure in any of the cited references that the register rename recovery circuitry is configured to detect an entry comprising ‘the predetermined value.’” Appeal Br. 13. According to Appellant, “since the memory address in the destination field for a store instruction as taught by Hennessy is random and varies from instruction to instruction, the register rename recovery circuitry would not be ‘responsive to an entry comprising the predetermined value’ as recited in claim 1.” Id. at 16. “The fact that the value is predetermined means that it must be known. If a value is not known it cannot be predetermined.” Id. at 18. Although we agree with the Examiner that under the broadest reasonable interpretation, a “predetermined value” must be “known in advance” (Ans. 9), we agree with Appellant that the Examiner has not sufficiently shown how looking at a destination field with a register for a random memory address is known in advance. Put another way, such a random memory address may be determined at runtime, but the Examiner has not shown how it is predetermined. Accordingly, we do not sustain the Examiner’s rejection of independent claims 1, 12, and 13, and their dependent claims 2-6, 8, 10, and 11, which Appellant argues are patentable for similar reasons. See Appeal Br. 18; 37 C.F.R. § 41.37(c)(1)(iv). Appeal 2020-005153 Application 14/938,285 6 OUTCOME The following table summarizes the outcome of each rejection: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-4, 10-13 103 Ogawa, Chaussade, Hennessy, Official Notice 1-4, 10-13 5, 6 103 Ogawa, Chaussade, Hennessy, Mylius, Official Notice 5, 6 8 103 Ogawa, Chaussade, Hennessy, White 8 Overall Outcome 1-6, 8, 10-13 REVERSED