ARM Inc.v.Vantage Point Technology, Inc.

Patent Trial and Appeal Board

Sep 5, 2014

08146818 (P.T.A.B. Sep. 5, 2014)

Trials@uspto.gov Paper 10
Tel: 571-272-7822 Entered: September 5, 2014

UNITED STATES PATENT AND TRADEMARK OFFICE
_______________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________
ARM INC.,
Petitioner,
v.
VANTAGE POINT TECHNOLOGY, INC.,
Patent Owner.
_______________

Case IPR2014-00467
Patent 5,463,750
_______________

Before BRYAN F. MOORE, HYUN J. JUNG, and DAVID C. MCKONE,
Administrative Patent Judges.

MCKONE, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
37 C.F.R. § 42.108

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I. INTRODUCTION
A. Background
ARM Inc. (“Petitioner”) filed a Corrected Petition (Paper 7, “Pet.”) to
institute inter partes review of claims 1 and 8 of U.S. Patent No. 5,463,750
(Ex. 1001, “the ’750 patent”). Vantage Point Technology, Inc. (“Patent
Owner”) filed a Preliminary Response (Paper 9, “Prelim. Resp.”).
We determine that the record before us does not demonstrate that
there is a reasonable likelihood, under 35 U.S.C. § 314(a), that Petitioner
would prevail with respect to at least one challenged claim. We
consequently deny the Petition and decline to institute inter partes review of
the ’750 patent.

B. Related Matters
Patent Owner has asserted the ’750 patent against various companies
in several lawsuits filed in the United States District Court for the Eastern
District of Texas. Pet. 1–2; Paper 4, at 2–4.

C. References Relied Upon
Petitioner relies upon the following prior art references:
Ex. 1006 US 4,933,835 June 12, 1990 (“the ’835 patent”)
Ex. 1007 US 4,920,477 Apr. 24, 1990 (“the ’477 patent”)
DIGITAL EQUIPMENT CORPORATION, DIGITAL TECHNICAL JOURNAL,
VAX 8800 FAMILY (Richard W. Beane, ed., No. 4, Feb. 1987)
(Ex. 1002, “VAX 8800”).
Robert P. Colwell et al., A VLIW Architecture for a Trace Scheduling
Compiler, VOL. 37, NO. 8, IEEE TRANSACTIONS ON COMPUTERS
967–79 (Aug. 1988) (Ex. 1013, “Colwell”).
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D. The Asserted Grounds
Petitioner contends that the challenged claims are unpatentable based
on the following specific grounds (Pet. 9-10):
References Basis Claims Challenged
VAX 8800 § 102(b) 1, 8
VAX 8800 § 103(a) 1, 8
VAX 8800 and the
’835 patent
§ 103(a) 1, 8
The ’477 patent § 102(b) 1, 8
The ’477 patent § 103(a) 1, 8
The ’477 patent and
Colwell
§ 103(a) 1, 8
The ’477 patent, Colwell,
and the ’835 patent
§ 103(a) 1, 8

II. ANALYSIS
A. The ’750 Patent
The ’750 patent is directed to a computer memory access technique
that includes a translation lookaside buffer (“TLB”) for each of a plurality of
instruction pipelines. Ex. 1001, Abstract. A TLB is a component of an
address translator that translates virtual addresses to physical addresses. Id.
The ’750 patent describes a computer issuing instructions that operate
on data stored in various physical memories (e.g., cache memory, random
access memory (“RAM”), registers, and hard drive memory). Id. at col. 1,
ll. 15–28. The locations in a particular physical memory, such as a
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computer’s main RAM memory (“main memory”), have physical addresses
(“PAs”). Id. at col. 2, ll. 1–10. The computer can address data stored in
memory using virtual addresses (“VAs”), which typically have a larger
address space such that there are many more VA locations than PA
locations. Id. at col. 1, ll. 53–60. Some of the data referred to by VAs may
not be stored in the main memory at a particular time and, instead, may be
stored only in a slower storage location, such as a hard drive. Id. at col. 2,
ll. 49–57. PAs can be assigned to data referred to by VAs on an as-needed
basis. Id. The mapping of VAs that point to data actually stored in the main
memory is tracked using page tables stored in the main memory. Id. at
col. 2, ll. 11–26. To further speed up accessing data, a subset of the VA to
PA mappings may be stored in a faster buffer, specifically a TLB. Id. at
col. 2, ll. 61–65.
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Figure 5 of the ’750 patent is reproduced below:

Figure 5 is a block diagram of a system that uses multiple TLBs to translate
VAs to PAs. Id. at col. 4, ll. 56–59. The system includes three instruction
pipelines 210A, 210B, 210C, that communicate virtual addresses
(representing data to be used by the instructions) to address registers 214A,
214B, 214C. Id. at col. 4, ll. 59–65. For pipeline 210A, a portion of a VA is
communicated to TLB 222A and a portion of the VA is communicated to
comparator 230A. Id. at col. 4, l. 63–col. 5, l. 2. TLB 222A produces a real
address (“RA”) associated with the VA and communicates it to comparator
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230A. Id. at col. 5, ll. 2–6. Comparator 230A determines, from the RA
produced by TLB 222A and the portion of the VA received from address
register 214A, whether the data corresponding to the VA is stored in main
memory (a “TLB hit”) or whether the data must be retrieved using the page
tables in the main memory (a “TLB miss”). Id. at col. 5, ll. 6–9.
In the case of a TLB miss, update control circuit 240 activates a
dynamic translation unit (“DTU”) to retrieve the VA to PA mapping from
the page tables in the main memory. Id. at col. 5, ll. 10–18. Update control
circuit 240 then causes the VA to PA mapping to be stored in the TLB. Id.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. An apparatus for translating virtual addresses in a
computing system having at least a first and a second
instruction pipeline and a direct address translation unit for
translating virtual addresses into real addresses, the direct
address translation unit including a master translation memory
for storing translation data, the direct address translation unit
for translating a virtual address into a corresponding real
address, comprising:
a first translation buffer, associated with the first
instruction pipeline, for storing a first subset of
translation data from the master translation
memory;
a first address translator, coupled to the first instruction
pipeline and to the first translation buffer, for
translating a first virtual address received from the
first instruction pipeline into a corresponding first
real address, the first address translator
comprising:
first translation buffer accessing means for
accessing the first translation buffer;
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first translation indicating means, coupled to the
first translation buffer accessing means, for
indicating whether translation data for the
first virtual address is stored in the first
translation buffer; and
first direct address translating means, coupled to
the first translation indicating means and to
the direct address translation unit to translate
the first virtual address when the first
translation indicating means indicates that
the translation data for the first virtual
address is not stored in the first translation
buffer, the first direct address translating
means including first translation buffer
storing means, coupled to the first
translation buffer, for storing the translation
data for the first virtual address from the
master translation memory into the first
translation buffer;
a second translation buffer, associated with the second
instruction pipeline, for storing a second subset of
translation data from the master translation
memory; and
a second address translator, coupled to the second
instruction pipeline and to the second translation
buffer, for translating a second virtual address
received from the second instruction pipeline into
a corresponding second real address, the second
address translator comprising:
second translation buffer accessing means for
accessing the second translation buffer;
second translation indicating means, coupled to the
second translation buffer accessing means,
for indicating whether translation data for
the second virtual address is stored in the
second translation buffer; and
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second direct address translating means, coupled to
the second translation indicating means and
to the first address translation unit, for
activating the direct address translation unit
to translate the second virtual address when
the second translation indicating means
indicates that the translation data for the
second virtual address is not stored in the
second translation buffer, the second direct
address translating means including second
translation buffer storing means, coupled to
the second translation buffer, for storing the
translation data for the second virtual
address from the master translation memory
into the second translation buffer.

B. Claim Construction
The ’750 patent is expired. “[T]he Board’s review of the claims of an
expired patent is similar to that of a district court’s review.” In re Rambus
Inc., 694 F.3d 42, 46 (Fed. Cir. 2012) (internal citations omitted). Thus, we
construe the claims in accordance with their ordinary and customary
meanings, as would be understood by a person of ordinary skill in the art, in
the context of the specification. See generally Phillips v. AWH Corp., 415
F.3d 1303 (Fed. Cir. 2005) (en banc).
Claim 1 recites limitations in “means-plus-function” format. “Section
112, ¶ 6 recites a mandatory procedure for interpreting the meaning of a
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means- or step-plus-function claim element.
1
These claim limitations ‘shall
be construed to cover the corresponding structure, material, or acts described
in the specification and equivalents thereof.’” Al-Site Corp. v. VSI Int’l,
Inc., 174 F.3d 1308, 1320 (Fed. Cir. 1999). We construe such a limitation
by determining what the claimed function is and identifying the structure or
materials disclosed in the specification that correspond to the means for
performing that function. See Kemco Sales, Inc. v. Control Papers Co.,
208 F.3d 1352, 1360 (Fed. Cir. 2000).

1. “first direct address translating means”
The function of the “first direct address translating means,” recited in
claim 1, is “to translate the first virtual address when the first translation
indicating means indicates that the translation data for the first virtual
address is not stored in the first translation buffer.”
Petitioner argues that this claim element is ambiguous. Pet. 15-16.
Claim 1’s preamble also recites a “direct address translation unit” as
performing a translating function. Petitioner contends that the structure
described in the specification for performing a translating function is the
DTU (shown in Figures 4 and 5). Pet. 14-15 n.1. According to Petitioner,
the DTU most naturally corresponds to the direct address translation unit,
not the first direct address translating means. Id. Because the first direct

1
Paragraph 6 of 35 U.S.C. § 112 was replaced with newly designated
§ 112(f) when § 4(c) of the Leahy-Smith America Invents Act, Pub. L. No.
112-29 (2011) (“AIA”) took effect on September 16, 2012. Because the
’750 patent has a filing date before September 16, 2012, we refer to the pre-
AIA version of § 112 in this decision.
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address translating means is coupled to the direct address translation unit,
Petitioner argues, if the DTU was also the structure corresponding to the first
direct address translating means, the first direct address translating means
would be coupled to itself. Id.
Petitioner, while maintaining that this element is unclear, notes that
claim 1 also recites a “second direct address translating means” that
performs an activating function, and that claim 4 recites a “third direct
address translating means” that performs an activating function. Id. at
15 n.1. Thus, Petitioner argues, the first direct address translating means
also should be understood to perform an activating function. Id. In other
words, Petitioner would construe “first direct address translating means” to
perform the function “for activating the direct address translation unit to
translate the first virtual address.” Pet. 16. Accordingly, Petitioner proposes
construing the first direct address translating means to correspond to the
update control circuit, which performs a function of activating the DTU to
translate. Id. at 15-16 (citing Ex. 1001, col. 5, ll. 10–15; col. 5, ll. 40–42).
Patent Owner does not propose a construction for “first direct address
translating means” in the Preliminary Response. See Prelim. Resp. 2.
For purposes of this decision, we accept Petitioner’s proposed
function and corresponding structure for the “first direct address translating
means.”
2

2
To be clear, Petitioner does not concede the definiteness of claim 1, nor do
we decide it. Rather, Petitioner recognizes that it cannot challenge a claim
under 35 U.S.C. § 112, second paragraph, in an inter partes review.
Pet. 14 n.1.
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2. “second direct address translating means”
The function of the “second direct address translating means,” recited
in claim 1, is “activating the direct address translation unit to translate the
second virtual address when the second translation indicating means
indicates that the translation data for the second virtual address is not stored
in the second translation buffer.” Petitioner contends that the specification
describes the update control circuit as performing this function. Pet. 17.
Patent Owner does not propose a construction of this term.
We agree with Petitioner. The specification describes update control
circuit 240 as activating the DTU when the comparators for pipelines 210B
and 210C indicate a TLB miss. Ex. 1001, col. 5, ll. 6–9, 15–26. On this
record, we conclude that the structure described in the specification
corresponding to the second direct address translating means is the update
control circuit, as disclosed in column 5, lines 15–26, of the ’750 patent.

3. “the first address translation unit”
Claim 1 recites “second direct address translating means, coupled to
. . . the first address translation unit” (emphasis added). Petitioner contends
that “the first address translation unit” has no antecedent basis or written
description support in the specification of the ’750 patent. Pet. 11.
Petitioner proposes that the term be construed to mean either “the direct
address translation unit” or “the first address translator,” two structures
previously recited in claim 1. Id. at 12. According to Petitioner, however, it
is unclear which of these structures the patentee intended to recite. Id.
Patent Owner does not propose a construction for this term.
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We disagree that “the first address translation unit” could be read as
“the first address translator.” As recited, the “first address translator”
includes several structures, including the “first direct address translating
means,” which we construe to correspond to the update control circuit. As
explained above, the “second direct address translating means,” coupled to
“the first address translation unit,” is the update control circuit. Construing
“the first address translation unit” to mean the “first address translator,”
then, would result in the update control circuit being coupled to a component
that itself includes the update circuit, a result that is not supported by the
specification. For purposes of this decision, we accept Petitioner’s alternate
proposal that the first address translation unit be construed as “the direct
address translating unit.”
3

C. Anticipation by VAX 8800
1. VAX 8800
VAX 8800 is a journal compiling several papers describing technical
details of the Digital Equipment Corporation VAX 8800 family of
multiprocessors. Ex. 1002, at 8. A VAX 8800 system consists of two
identical processors. Id. at 48. Communications between processors in the
VAX8800 system are performed by writing to portions of shared memory
rather than by passing messages directly between processors. Id. at 120.
Each processor includes a five-stage pipeline in which instructions are
processed simultaneously through logic boxes. Id. at 10.

3
As with the “first direct address translating means,” discussed above, we
do not view Petitioner’s proposal as a concession that “the first address
translation unit” is definite.
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One of the boxes is a cache box, or “C BOX,” which performs, inter
alia, virtual address (“VA”) to physical address (“PA”) translation and
includes a translation buffer. Id. at 14–15. Figure 6, on page 15, and
Figure 2, on page 43, are reproduced below:

Figure 6 is a block diagram of the C Box. A translation buffer of the C Box
receives a virtual address and translates it into a physical address. Id. at 14–
15. Figure 2 is a block diagram showing the operation of the translation
buffer (“TB”). The translation buffer receives a virtual address over address
lines (e.g., VA(31, 17–9)) and generates a TB tag and a physical address.
Id. at 42-43. A comparator compares the tag to the remaining virtual address
lines to determine whether the PA corresponding to the VA is in the TB (a
TB hit) or not (a TB miss). Id. at 43. In the case of a TB miss, “microcode
must perform the translation. The microcode then writes the data into the
TB for subsequent use.” Id.

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2. Claims 1 and 8
Claim 1 recites “a direct address translation unit for translating virtual
addresses into real addresses” and further recites “a first address translator”
including “first direct address translating means, coupled . . . to the direct
address translation unit.” Claim 8 includes similar recitations. Patent
Owner contends that both claims 1 and 8 require a single direct address
translation unit that, in the instances of TLB misses, translates VAs to PAs
for both first and second pipelines. Prelim. Resp. 5 (“[C]laim 1 by its very
terms makes clear that it is a single direct address translation unit that is
shared by the first and second address translating means.”); id. at 7.
According to Patent Owner, VAX 8800 does not anticipate claims 1 and 8
because it describes multiple direct address translation units, one for each
pipeline. Id. at 5-7. We agree.
We recognize that the Unites States Court of Appeals for the Federal
Circuit “has repeatedly emphasized that an indefinite article ‘a’ or ‘an’ in
patent parlance carries the meaning of ‘one or more’ in open-ended claims
containing the transitional phrase ‘comprising.’” Baldwin Graphic Sys., Inc.
v. Siebert, Inc., 512 F.3d 1338, 1342 (Fed. Cir. 2008) (internal citations and
quotation marks omitted). “An exception to the general rule that ‘a’ or ‘an’
means more than one only arises where the language of the claims
themselves, the specification, or the prosecution history necessitate a
departure from the rule.” Id. at 1342-43. In Abtox, Inc. v. Exitron Corp.,
122 F.3d 1019, 1024 (Fed. Cir. 1997), for example, a claim’s repeated use of
“said chamber,” as well as the specification’s description of a single
chamber, reinforced the singular nature of the claimed chamber. See also
Insituform Techs., Inc. v. Cat Contracting, Inc., 99 F.3d 1098, 1105-06 (Fed.
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Cir. 1996) (“[C]laim 1 refers to ‘a cup’ and ‘the cup’ repeatedly, suggesting
that only one cup is involved. . . . [W]e note that neither the specification
nor the drawings disclose the use of more than one cup.”).
As explained above, the ’750 patent is expired; accordingly, we
evaluate the meaning of “the direct address translation unit” under the
standard a district court would apply, not under a broadest reasonable
construction. Under a district court standard, we are persuaded that the
claim language and the written description of the ’750 patent overcome any
rule (or rebut any presumption) that “a direct address translation unit” should
be construed to mean “one or more direct address translation units.”
Both claims 1 and 8 first recite “a direct address translation unit” and
later repeatedly refer to “the direct address translation unit” when reciting
additional features of that component. For example, claim 1 (emphases
added) recites:
“the direct address translation unit including a master
translation memory for storing translation data”;
“the direct address translation unit for translating a virtual
address into a corresponding real address”;
“first direct address translating means, coupled . . . to the direct
address translation unit”; and
“second direct address translating means, . . . for activating the
direct address translation unit to translate the second
virtual address.”
Claim 8 recites similar limitations. Such usage suggests that a single direct
address translation unit must meet each of these additional limitations.
The description in the specification is consistent with the singular
reading. According to the specification, a known technique for accessing
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page tables in main memory was the use of a dynamic translation unit
(“DTU”). Ex. 1001, col. 3, ll. 41–48. The only component described in the
specification as performing a translation function in the event of a cache
miss is the DTU. Id. at col. 2, l. 67–col. 3, l. 1; col. 5, ll. 10–26. Thus, the
DTU is described as performing the functionality of the direct address
translation unit recited in the claims. According to the specification, several
pipelines using the same TLB can result in inefficient, excessive use of the
DTU, degrading performance. Id. at col. 3, l. 56–col. 4, l. 3. The patentee’s
described solution was to use a separate TLB for each pipeline, as shown in
Figure 5. Id. at col. 5, ll. 10-26. The ’750 patent does not describe using a
separate DTU for each pipeline. Rather, a single DTU 162 accesses the
main memory for each pipeline. Id. Although the specification does not
exclude expressly the use of multiple DTUs, it describes the invention as a
purported solution to the problem of excessive use of a DTU. This further
suggests that claims 1 and 8 should be construed as directed to a single
direct address translation unit that is activated to translate virtual addresses
from multiple pipelines.
To be sure, consistent with Federal Circuit precedent, claims 1 and 8
are not limited to devices that have a single direct address translation unit.
After all, both claims 1 and 8 are open-ended “comprising” claims.
However, a device within the scope of these claims must have at least one
direct address translation unit that meets the remaining claim limitations. In
other words, to be covered by claims 1 and 8, a device must have one direct
address translation unit that is activated to translate both a first and a second
virtual address. It is not enough to show a first direct address translation unit
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that translates a first virtual address and a second direct address translation
unit that translates a second virtual address.
Petitioner contends that the “direct address translation unit” disclosed
in VAX 8800 is “the combination of hardware and the microcode . . . that is
executed when a TB miss is detected.” Pet. 20 (citing Ex. 1002, at 43).
According to VAX 8800, “[i]f the PA that pertains to the VA is not in the
TB, called a TB miss, then microcode must perform the translation. The
microcode then writes the data into the TB for subsequent use.” Ex. 1002,
at 43.
Petitioner also argues that VAX 8800 discloses two separate processor
cores and that “[e]ach core possesses a pipeline for executing instructions
and a TB for translating addresses, locating the first instruction pipeline and
the associated TB in one processor, and the second instruction pipeline and
the associated TB in the second processor.” Pet. 21 (citing Ex. 1002, at 48).
Patent Owner argues that this evidences two direct address translation units,
one for each core. Prelim. Resp. 6.
Given VAX 8800’s discussion of dual cores separately processing
instructions for separate pipelines, we are not persuaded that VAX 8800
nevertheless describes a single set of microcode for performing translations
for both pipelines. In any case, Petitioner has not introduced persuasive
evidence showing that VAX 8800 discloses a single direct address
translation unit that is activated to translate virtual addresses from multiple
pipelines. Instead, Petitioner cites microcode executing on an unspecified
processor as disclosing the direct address translation unit. Pet. 20.
Accordingly, Petitioner has not demonstrated that it is reasonably
likely to succeed in showing that VAX 8800 anticipates claims 1 and 8.
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D. Obviousness over VAX 8800
Petitioner contends that claims 1 and 8 would have been obvious over
VAX 8800 if we were to construe “first and second instruction pipelines” to
require a common instruction issuing unit. Pet. 33. Petitioner does not
contend, however, that a single direct address translation unit activated to
translate both a first and a second virtual address would have been obvious
in light of VAX 8800. Accordingly, Petitioner has not demonstrated that it
is reasonably likely to succeed in showing that claims 1 and 8 would have
been obvious over VAX 8800.

E. Obviousness over VAX 8800 and the ’835 Patent
Petitioner contends that any elements of claims 1 and 8 missing from
VAX 8800 would have been obvious in view of the ’835 patent. Pet. 34.
Petitioner does not, however, identify in the ’835 patent a direct address
translation unit that is activated to translate both a first and a second virtual
address. Nor does Petitioner contend that this feature would have been
obvious in view of the ’835 patent. Accordingly, Petitioner has not
demonstrated that it is reasonably likely to succeed in showing that claims 1
and 8 would have been obvious over VAX 8800 and the ’835 patent.

F. Anticipation by the ’477 Patent
1. The ’477 Patent
The ’477 patent describes a technique for recovering from virtual
address table lookaside buffer misses. In particular, the ’477 patent
describes a computer system that has a CPU that includes a plurality of
clusters. Ex. 1007, col. 3, ll. 61–63; Fig. 1. Each cluster includes an integer
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processor, which, in turn, includes a data translation lookaside buffer
(“DTLB”) for translating VAs to PAs. Id. at col. 3, ll. 63–66; col. 5, ll. 9–
13. Petitioner contends that each of these clusters is a pipeline. Pet. 42.
The clusters are coupled to a plurality of memory systems. Ex. 1007, col. 3,
l. 66–col. 4, l. 1.
Figure 12 is reproduced below:

Figure 12 is a block diagram illustrating the conversion of virtual addresses
to physical addresses in an integer processor of a cluster. Id. at col. 3, ll. 33–
35; col. 23, ll. 15–37. Arithmetic logic unit (“ALU”) 0 generates a virtual
address, part of which is used as an address to TLB RAM 76. Id. at col. 23,
ll. 33–43. Hasher circuitry 310 associates the virtual address with a user
identification designation (an address space identification code (“ASID”))
before the virtual address is sent to TLB RAM 76. Id. at col. 23, l. 44–
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col. 24, l. 2. This allows a larger number of different processes to exist in
TLB RAM 76 at one time, where those processes would otherwise overlap.
Id. at col. 23, ll. 61–66.
Each TLB entry includes a TLB tag and a TLB ASID. Id. at col. 24,
ll. 10–17. The ’477 patent describes using comparators 312, 314 to
determine, from a TLB tag and a TLB ASID, whether or not the data at the
virtual address exists at the physical address indicated by TLB RAM 76, i.e.,
a TLB hit or a TLB miss. Id. at col. 23, ll. 46–50; col. 24, ll. 30–40.
The system of the ’477 patent enters a “trap mode” in the event of a
TLB miss. Id. at col. 25, ll. 33–44. Because instructions are pipelined, a
TLB miss might not be detected until after some memory accesses have
been initiated. Id. at col. 25, ll. 31–32. Only those memory accesses that
occur after the TLB miss is detected are flushed and restarted, while memory
accesses that were initiated before the TLB miss are allowed to complete.
Id. at col. 25, ll. 33–40; col. 27, ll. 25–28. The system loads the needed data
into physical memory and the memory load cycle is restarted. Id. at col. 27,
ll. 28–30.

2. Claims 1 and 8
As it did for VAX 8800, Patent Owner contends that the ’477 patent
does not anticipate claims 1 and 8 because it does not disclose a single direct
address translating unit that is activated to translate both a first virtual
address from a first instruction pipeline and a second virtual address from a
second instruction pipeline. Prelim. Resp. 13.
According to Petitioner, “[t]he ‘direct address translation unit’ in the
’477 Patent is the operating system that acts on the TLB misses generated by
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the TLB logic illustrated in and discussed in connection with the translation
operations depicted in Fig. 12.” Pet. 41. Petitioner (Pet. 41) relies on the
portion of the ’477 patent found at column 25, lines 33–44, which states, in
part, that “when a TLB miss is detected, the operating system must do more
than merely swap data as needed[;] . . . a trap code procedure is initiated and
the system enters a so-called ‘trap mode.’” In identifying a “direct address
translation means” in the ’477 patent, Petitioner further argues that “the ’477
patent also includes the software and/or microcode that assists in the
translation and TLB miss.” Pet. 47 (citing Ex. 1007, col. 27, ll. 24–34).
According to Petitioner, “[t]he needed data referred to in this portion of the
specification is the updated translation that was originally a miss. Once the
code executed in the trap handler executes, a translation is generated by
accessing the page tables in the main memory.” Pet. 47-48 (citing Ex. 1007,
col. 5, ll. 20–23).
Petitioner does not identify specific structure described in the
’477 patent for translating virtual addresses to physical addresses in the
event of a TLB miss. Rather, Petitioner identifies the operating system
generally “in connection with the translation operations depicted in
Figure 12.” Pet. 41. As Petitioner’s declarant, Dr. V. Thomas Rhyne,
acknowledges, the operations depicted in Figure 12 are performed by
structure in the integer processers, in particular the ALUs and DTLBs of the
integer processors. Ex. 1009 ¶¶ 28–29. Petitioner further argues that “each
TLB is associated with a[n] integer processor that has its own pipeline and
thus each TLB is associated with its own instruction pipeline.” Pet. 43.
Thus, the evidence presented by Petitioner suggests that an integer processor
for each cluster translates virtual addresses to physical addresses for the
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pipeline of that cluster in the event of a TLB miss. In any case, Petitioner
has not shown persuasively that the ’477 patent discloses one direct address
translation unit that translates virtual addresses for multiple pipelines.
As explained above, claims 1 and 8 require one direct address
translation unit that is activated to translate both a first virtual address from a
first instruction pipeline and a second virtual address from a second
instruction pipeline. Petitioner has not demonstrated that it is reasonably
likely to show this in the ’477 patent. Accordingly, Petitioner has not
demonstrated a reasonable likelihood of prevailing as to claims 1 and 8 as
anticipated by the ’477 patent.

G. Obviousness over the ’477 Patent
Page 9 of the Petition contends that claims 1 and 8 would have been
obvious over the ’477 patent. Petitioner repeats this contention at page 40
(“As shown below, the ’477 patent anticipates and/or renders obvious claims
1 and 8.”). Petitioner, however, presents no substantive arguments
supporting this contention. Accordingly, Petitioner has not demonstrated a
reasonable likelihood of prevailing as to claims 1 and 8 as obvious over the
’477 patent.

H. Obviousness over the ’477 Patent and Colwell
Petitioner contends that Colwell discloses technical details of the
computer described in the ’477 patent and that a person of ordinary skill in
the art would have sought to combine the ’477 patent and Colwell because
they discuss the same computer architecture. Pet. 53-54. Petitioner argues
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that Colwell “confirms and amplifies several aspects of the ’477 disclosure.”
Id. at 54.
Petitioner cites Colwell as teaching a direct address translation unit.
Specifically, Petitioner contends that Colwell teaches using software to re-
fill the TLBs when a miss occurs. Pet. 55-56 (citing Ex. 1013, at 970, 973).
Colwell explains that “[t]raps are taken on TLB misses; trap handling
software manages TLB refills.” Ex. 1013, at 970. This discussion is in the
context of “integer operations” in an “I board” of Colwell’s system. Id. at
970. According to Petitioner, an I board is a separate functional unit with its
own pipeline and TLB. Pet. 55. This suggests that each pipeline is
associated with its own software for managing TLB refills. Indeed, Colwell
further explains that the contents of TLBs are updated by a “history queue”
mechanism of each I board. Ex. 1013, at 973.
Petitioner has not demonstrated that it is reasonably likely to show
that Colwell teaches one direct address translation unit that is activated to
translate both a first virtual address from a first instruction pipeline and a
second virtual address from a second instruction pipeline. Thus, Petitioner
has not demonstrated a reasonable likelihood of prevailing as to claims 1
and 8 as obvious over the ’477 patent and Colwell.

I. Obviousness over the ’477 Patent, Colwell, and the ’835 Patent
Petitioner argues that claims 1 and 8 would have been obvious over
the ’477 patent, Colwell, and the ’835 patent. Pet. 57-60. Petitioner,
however, does not contend that the ’835 patent teaches the claimed direct
address translation unit or that this feature would have been obvious in view
of the ’835 patent. Accordingly, Petitioner has not shown that it is
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reasonably likely to succeed in showing that claims 1 and 8 would have been
obvious over the ’477 patent, Colwell, and the ’835 patent.

III. CONCLUSION
Petitioner has not demonstrated that it is reasonably likely to show
that VAX 8800, alone or in combination with the ’385 patent, teaches a
direct address translation unit as recited in claims 1 and 8. Likewise,
Petitioner has not demonstrated that it is reasonably likely to show that the
’477 patent, alone or in combination with Colwell and the ’385 patent,
teaches a direct address translation unit. Thus, Petitioner has not shown that
there is a reasonable likelihood that it would prevail with respect to at least
one of the claims challenged in the Petition.

IV. ORDER
For the reasons given, it is
ORDERED that the Petition is denied.
FURTHER ORDERED that no inter partes review is instituted.

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PETITIONER:

Scott Felder
sfelder@wileyrein.com

Floyd Chapman
fchapman@wileyrein.com

PATENT OWNER:

Tarek Fahmi
Tarek.fahmi@ascendalaw.com