Analog Devices, Inc.

Patent Trials and Appeals Board

Mar 11, 2022

IPR2020-01559 (P.T.A.B. Mar. 11, 2022)

Trials@uspto.gov Paper 31 571-272-7822 Date: March 11, 2022 UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD., Petitioner, v. ANALOG DEVICES, INC., Patent Owner. IPR2020-01559 Patent 7,286,075 B2 Before JEFFREY S. SMITH, SCOTT A. DANIELS, and GEORGIANNA W. BRADEN, Administrative Patent Judges. DANIELS, Administrative Patent Judge. JUDGMENT Final Written Decision Determining No Challenged Claims Unpatentable 35 U.S.C. § 318(a) IPR2020-01559 Patent 7,286,075 B2 2 I. INTRODUCTION A. Background On July 17, 2020, Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. (collectively, “Petitioner”) filed a Petition requesting an inter partes review of claims 1-25 of U.S. Patent No. 7,286,075 B2, issued on October 23, 2007 (Ex. 1001, “the ’075 patent”). Paper 2 (“Pet.”). Analog Devices, Inc. (“Patent Owner”) filed a Preliminary Response. Paper 6 (“Prelim. Resp.”). Following our Institution Decision (Paper 13, “Inst. Dec.”), Patent Owner filed a Response. Paper 19 (“PO Resp.”). Petitioner filed a Reply. Paper 23 (“Reply”). Patent Owner filed a Sur-Reply. Paper 24 (“PO Sur- Reply”). A hearing was held on December 9, 2021. A transcript of the hearing has been entered as Paper 30 (“Tr.”). We have jurisdiction under 35 U.S.C. § 6. This Final Written Decision is entered pursuant to 35 U.S.C. § 318(a). We determine that Petitioner has not shown by a preponderance of the evidence that claims 1- 25 are unpatentable. B. Additional Proceedings The parties indicate that the ’075 patent has been asserted against Petitioner in Analog Devices, Inc. v. Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd., Case No. 1:19-cv-02225 in the United States District Court for the District of Delaware. Pet. 1; Paper 4, 2. Patent Owner also states that “Petitioner[] filed petitions for Inter Partes Review of U.S. Patent No. 10,250,250 (Case No. IPR2020-01210), U.S. Patent No. 8,487,659 (Case No. IPR2020-01219), U.S. Patent No. 7,012,463 (Case No. IPR2020- 01336), U.S. Patent No. 7,719,452 (Case No. IPR2020-01561), and U.S. Patent No. 6,900,075 (Case Nos. IPR2020-01483, IPR2020-01484, and IPR2020-01564), which also are at issue in the above litigation.” Paper 4, 2. IPR2020-01559 Patent 7,286,075 B2 3 C. Real Parties in Interest The Petition identifies Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. as Real Parties in Interest. Pet. 1. Patent Owner identifies itself as the Real Party-in-Interest. Paper 4, 2. D. The ’075 Patent (Ex. 1001) The ’075 patent describes problems and improvements related to analog to digital converters (“ADC”). Ex. 1001, 1:6-9. An analog to digital converter takes an analog signal as input and converts that analog signal into a corresponding digital output. See id. at 3:37-41. Figures 1 and 2, reproduced below, are graphs showing the correspondence between input analog signals (on the y-axis) with output digital signals (on the x-axis). See id. at 3:36-43, 3:53-55. As shown in Figure 1, above left, an input analog signal having a voltage level ranging between 0.5 and 1.5 units corresponds to bit-encoded digital output code XX001 (where XX are irrelevant bits). Id. at 3:37-41. Ideally, each range of analog input signals which each digital code spans is equal, exhibiting “good linearity.” Id. at 1:13-14, 3:41-43. For example, each range should span 1.0 voltage units such that input voltages between 0.5 and IPR2020-01559 Patent 7,286,075 B2 4 1.5 units correspond to digital code XX001, input voltages between 1.5 and 2.5 units correspond to digital code XX010, and so on. Id. at 3:36-43. As shown in Figures 1 and 2, however, a digital output code problematically spans a greater corresponding input voltage range than it should - an error known as differential non-linearity (DNL). Id. at 3:43-46; 3:57-67. DNL errors may also result in missing codes, as shown in Figures 1 and 2. Id. at 3:49-52; 3:57-67. The ’075 patent states that one can reduce DNL errors and missing codes by “[a]dding a known dither to the operation of the analog to digital converter.” Id. at 4:1-7. The ’075 patent explains that this is known in the prior art to be accomplished by “sampling the input voltage and then summing it using a summer with a dither voltage prior to sending this to the analog to digital converter.” Id. at 4:8-10. The ’075 patent presents a different technique which uses a “switched capacitor architecture . . . to impose a perturbation or a dither onto the sampled signal.” Id. at 4:23-26. Figure 3, reproduced below, illustrates an analog to digital converter having a particular switched capacitor architecture which adds dither to the conversion. Id. at 3:29-30, 4:44-45. IPR2020-01559 Patent 7,286,075 B2 5 As shown in the analog to digital converter of Figure 3, an input voltage, signal AIN, is sampled onto the capacitors CB-CN of main P-DAC array 2 (interchangeably referred to as “main DAC array 2”). Id. at 5:62-65. That sampling is controlled by respective switches SB to SN, which selectively connect capacitors CB-CN to input signal AIN, first reference voltage Vrefp, or second reference voltage Vrefn. Id. at 5:57-6:2. Additionally, the analog to digital converter includes two other arrays of capacitors which are not used to sample input signal AIN: sub P-DAC array 10 having capacitors C1-CA (interchangeably referred to as “sub DAC array” or “sub array”) (Id. at 6:2-5) and an array of additional capacitors AC1-AC3 (Id. at 7:7-16). Using either, or both, of those other arrays, “a dither can be introduced into the analog to digital converter.” Id. at 7:46-51, 8:16-19. In the case of sub DAC array 10, capacitors C1-CA are each respectively connected to switches S1-SA, which alternatively switch their IPR2020-01559 Patent 7,286,075 B2 6 corresponding capacitors between first reference voltage Vrefp and second reference voltage Vrefn. Id. at 7:46-51. The ’075 patent explains that “selective switching of capacitors within the sub capacitor array can be used to perturb the voltage that was sampled onto the main capacitor array during the sampling phase and hence introduce a positive or negative dither into the analog to digital converter.” Id. at 7:62-8:4. And, similar to the sub DAC array, the array of additional capacitors AC1-AC3 provide a dither through respective switches SAC1- SAC3 selectively switching respective capacitors between first reference voltage Vrefp and second reference voltage Vrefn. Id. at 8:20-28. Furthermore, in both the sub DAC array 10 of capacitors C1-CA and the array of additional capacitors AC1-AC3, the capacitors’ respective switches “are driven in response to a pseudo random number generated by the pseudo random number generator 40.” Id. at 8:28-37. That is, “the pseudorandom generator 40 controls the switches SAC1, S1, S2, S3 and so on.” Id.; see id. at 8:52-58. This occurs, according to the ’075 patent, “once the sampling phase has been completed, [then] some of the capacitors are switched in response to the pseudorandom number generator. The switching can be done before the bit trials commence or during the bit trials.” Id. at 8:67-9:3. E. Illustrative Claims Petitioner challenges claims 1-25. Of the challenged claims, claims 1, 16, 20, 22, and 24 are independent. Each of dependent claims 2-15 depend from claim 1, claims 17-19 depend from claim 16, claim 21 depends from claim 20, claim 23 depends from claim 22, and claim 25 depends from IPR2020-01559 Patent 7,286,075 B2 7 claim 24. Claims 1 and 16 are reproduced below with certain limitations highlighted:1 1[pre]. An analog to digital converter for converting an analog input signal to a digital output signal, comprising 1[a] a first group of capacitors for participation in a successive approximation conversion, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; 1[b] a second group of capacitors for applying a dither and having switches for selectively connecting the capacitors to the first reference voltage or the second reference voltage and a sequence generator for generating a sequence of bits, 1[c] wherein during sampling of the analog input signal onto at least some of the capacitors of the first group of capacitors or during conversion of a sample of the analog input signal an output of the sequence generator is supplied to the switches of the second group of capacitors to control whether a given capacitor within the second group is connected by its associated switch to the first reference voltage or to the second reference voltage, so as to apply a dither to said conversion. Ex. 1001, 9:42-61 (emphases added). 16[pre] An analog to digital converter, comprising 16[a] a switched capacitor array for use in sampling an input signal and for converting a sample of said input signal to a digital value; and 16[b] a switched capacitor digital to analog converter responsive to a control word, 16[c] wherein after sampling an input signal onto the switched capacitor array to store charge in said array, the switched capacitor digital to analog converter is operated to make a known 1 We reference Petitioner’s bracketed labels and breaks in claims 1 and 16. See Pet. 29-30, 38-43. IPR2020-01559 Patent 7,286,075 B2 8 perturbation to the charge stored on the switched capacitor array. Id. at 10:49-59 (emphases added). F. Level of Ordinary Skill in the Art Factors pertinent to a determination of the level of ordinary skill in the art include: (1) educational level of the inventor; (2) type of problems encountered in the art: (3) prior art solutions to those problems; (4) rapidity with which innovations are made; (5) sophistication of the technology, and (6) educational level of workers active in the field. Envtl. Designs, Ltd. v. Union Oil Co., 713 F.2d 693, 696-697 (Fed. Cir. 1983) (citing Orthopedic Equip. Co. v. All Orthopedic Appliances, Inc., 707 F.2d 1376, 1381-82 (Fed. Cir. 1983)). Not all such factors may be present in every case, and one or more of these or other factors may predominate in a particular case. Id. Moreover, these factors are not exhaustive but are merely a guide to determining the level of ordinary skill in the art. Daiichi Sankyo Co. Ltd, Inc. v. Apotex, Inc., 501 F.3d 1254, 1256 (Fed. Cir. 2007). In determining a level of ordinary skill, we also may look to the prior art, which may reflect an appropriate skill level. Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001). Additionally, the Supreme Court informs us that “[a] person of ordinary skill is also a person of ordinary creativity, not an automaton.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 421. Petitioner, supported by the testimony of Dr. Holberg, argues that a person of ordinary skill in the art (“POSITA”) “would [have] at least a Master’s degree in Electrical Engineering or equivalent field, including studies in the area of analog circuitry; or at least a Bachelor’s degree in Electrical Engineering and at least two years of experience working on analog circuitry design.” Pet. 23 (citing Ex. 1003 ¶¶ 54-56). Neither Patent IPR2020-01559 Patent 7,286,075 B2 9 Owner nor its declarant, Dr. Moon, dispute or offer an alternative level or skill in the art at this time. See generally PO Resp., see also Ex. 2001 ¶ 13 (Dr. Moon stating that Petitioner’s asserted level of ordinary skill in the art is “reasonable”). On the full record now before us, the parties do not dispute the proposed level of ordinary skill in the art. Petitioner’s proposed level of ordinary skill is consistent with our review and understanding of the technology and descriptions in the ’075 patent and the prior art references that disclose electronic circuits including analog-to-digital converters using modulation feedback signals and charge injection in MOS transistor circuits to account for differential non-linearity. For purposes of this Decision, we rely on Petitioner’s proposed level of ordinary skill in the art. G. Claim Construction We interpret claims in the same manner used in a civil action under 35 U.S.C. § 282(b) “including construing the claim in accordance with the ordinary and customary meaning of such claim as understood by one of ordinary skill in the art and the prosecution history pertaining to the patent.” See Changes to the Claim Construction Standard for Interpreting Claims in Trial Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg. 51,340, 51,358 (Oct. 11, 2018) (amending 37 C.F.R. §42.100(b) effective November 13, 2018) (now codified at 37 C.F.R. § 42.100(b) (2019)).2 Only terms that are in controversy need to be construed, and then only to the extent necessary to resolve the controversy. Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017). 2 This rule change applies to the instant Petition because it was filed after November 13, 2018. See id. IPR2020-01559 Patent 7,286,075 B2 10 “Perturbation” The parties dispute the meaning of the term “perturbation.” Patent Owner contends that perturbation means, “a small, random, noisy change.” PO Resp. 19. Patent Owner argues that the claim language is consistent with the Specification, describing “that this perturbation is made by redistributing the charge already stored on the capacitor array during sampling of the input signal.” Id. (citing Ex. 1001, 10:57-59; Ex. 2017 ¶ 49). Patent Owner’s declarant, Dr. Moon, testifies that “[t]he ’075 specification repeatedly uses the term, consistent with this ordinary meaning, to describe the disturbance or agitation of the charge stored on the capacitor array, in a manner that introduces dither.” Ex. 2017 ¶ 50 (citing Ex. 1001, 7:46-62, 62-8:4, 2:7-11). Petitioner argues that Patent Owner attempts improperly to equate the terms “dither” and “perturbation,” and asserts that in the ’075 patent claims and specification it is described that a “perturbation” is applied to a single sample, not multiple samples and therefore “‘[n]oisy’ and ‘random’ simply have no meaning in the context of a single sample, because they both connote changes over time.” Reply 2. Petitioner asserts that “‘perturbation’ is a change applied to a single sample, and ‘dither’ is a sequence of different perturbations.” Id. at 5. Petitioner’s declarant, Dr. Holberg, testifies that “the ordinary meaning of ‘perturbation’ is simply a small change in movement, quality, or behavior of something, especially an unusual change.” Ex. 1003 ¶ 81. Independent claims 16, 20, and 22 use the term “perturbation.” Claim 16 recites in part: wherein after sampling an input signal onto the switched capacitor array to store charge in said array, the switched IPR2020-01559 Patent 7,286,075 B2 11 capacitor digital to analog converter is operated to make a known perturbation to the charge stored on the switched capacitor array. Ex. 1001, 10:55-59 (emphases added). A plain reading of this clause is that a perturbation is applied to the stored charge, i.e. an input signal sample, which was sampled onto the switched capacitor array. Claim 20 recites: supplying a perturbation control word to the switches of a group of capacitors during sampling of a signal onto at least one capacitor of the array of capacitors. Id. at 11:9-12 (emphases added). A plain reading of this clause, generally consistent with claim 16, is that the “perturbation control word” is supplied, i.e., applied, to the switches during sampling of a signal onto the capacitor array. Consistent with the language of independent claims 16 and 20 the specification expressly describes that a “perturbation” is applied to a sampled input signal. Id. at 2:5-7 (“It is thus possible to use capacitors forming part of the analog to digital converter to provide a controlled perturbation to the sampled input.”). Also, the specification sometimes alternatively refers to “perturbation” and “dither,” for example describing that [t]he inventors have realised that the switched capacitor architecture used in many successive approximation converters can be used to impose a perturbation or a dither onto the sampled signal. Id. at 4:23-26. At times the specification uses the terms interchangeably. Yet even still, the specification consistently describes the perturbation being imposed onto the sampled signal. Some clarity is provided by the further description that IPR2020-01559 Patent 7,286,075 B2 12 [a]pplying the same dither technique to the N-DAC sub array will produce a positive perturbation to the sampled input . . . [i]t can therefore be seen that selective switching of capacitors within the sub capacitor array can be used to perturb the voltage that was sampled onto the main capacitor array during the sampling phase. Id. at 7:60-8:4, see also id. at 8:49-51 (“a negative perturbation is introduced onto the sampled voltage on the main array 2.”). We find that a person of ordinary skill in the art would understand from a plain reading of the specification that in the context of the ’075 patent “dither” is a concept, or technique, which can occur, for instance, because a perturbation is applied to a sampled signal. This comports with Dr. Moon’s testimony that “[t]his ‘known perturbation’ is the mechanism through which the ’075 invention provides dither to the converter.” Ex. 2017 ¶ 49. Such an understanding is consistent with other claim language, for example independent claim 1 recites “a second group of capacitors for applying a dither.” Ex. 1001, 9:49. Dither is applied, in claim 1 when “an output of the sequence generator is supplied to the switches of the second group of capacitors.” Id. at 9:56-57. Thus, the mechanism of applying dither, in claim 1, is the output of the sequence generator, as opposed to specifically a perturbation applied to a sampled signal. The intrinsic evidence of the claims and specification does not describe perturbation as “noise” as Patent Owner urges. Patent Owner points us to extrinsic evidence, the WILEY ELECTRICAL AND ELECTRONICS ENGINEERING DICTIONARY (2004) (“Wiley”) which defines “dithering” as the “incorporation of a small perturbation or a little noise, for instance to minimize the effects of minor nonlinearities.” PO Resp. 21 (citing Ex. 2005; Ex. 2017 ¶ 52), see also Ex. 1024 (Analog Devices, Application Note AN- IPR2020-01559 Patent 7,286,075 B2 13 410 describing that “dither is an uncorrelated signal, usually pseudo random noise”). That “dithering” can be understood to include noise, does not necessarily mean that a perturbation is noise. In fact, the WILEY dictionary definition uses the phrase “perturbation or a little noise,” which can be read as alternatives. Ex. 2005. It is reasonable to understand from both the intrinsic and extrinsic evidence, that a person of ordinary skill in the art would have understood that dither can be accomplished by various mechanisms, including perturbation, adding noise, or suppling the output of a sequence generator to certain switches in a switched capacitor array. The term “perturbation” is, however, inextricably linked to “dither” in the context of the ’075 patent. It is clear from multiple descriptions in the ’075 patent that perturbation of the sampled voltage introduces dither into the analog to digital converter. See Ex. 1001, 7:62-8:4 (The ’075 patent states that “selective switching of capacitors within the sub capacitor array can be used to perturb the voltage that was sampled onto the main capacitor array during the sampling phase and hence introduce a positive or negative dither into the analog to digital converter.”); see also id. at 2:7-11 (The ’075 patent describing dithering where “[m]ultiple conversions of substantially the same input value can result in the input value being assigned different ‘bins’ within the conversion process as a result of different perturbations being applied at each individual sampling point.”).”) On the full record now before us, we agree with both parties to an extent. Considering Petitioner’s position, we find that dither has a broader meaning than perturbation in the context of the ’075 patent and, based on Dr. Holberg’s testimony, that a person of ordinary skill in the art would have understood perturbation as “a small change in movement, quality, or behavior of something, especially an unusual change.” Reply 5; Ex. 1003 IPR2020-01559 Patent 7,286,075 B2 14 ¶ 81. With respect to Patent Owner’s arguments and evidence, we do not agree that perturbation is simply random noise, but we find persuasive Patent Owner’s declarant, Dr. Moon, and his testimony that the ’075 patent uses this term “to describe the disturbance or agitation of the charge stored on the capacitor array, in a manner that introduces dither” into the analog to digital converter. PO Resp. 19-20. In sum, perturbation means “a small change in movement, quality, or behavior of something, especially an unusual change, and describes the disturbance or agitation of the charge stored on the capacitor array that introduces dither into the analog to digital converter.” H. Grounds Asserted Petitioner asserts that claims 1-7, 10-17, and 29 are unpatentable on the following grounds: Claim(s) Challenged 35 U.S.C. § Reference(s)/Basis 16, 17 103(a) Confalonieri3 1-7, 9, 10, 12-25 103(a) Confalonieri, Hiller4 8 103(a) Confalonieri, Hiller, Hester5 11 103(a) Confalonieri, Hiller, Bjornsen6 1-5, 7, 9-22 103(a) Cai,7 Bjornsen 8 103(a) Cai, Bjornsen, Hester Petitioner relies on the opinion testimony of Dr. Douglas R. Holberg (Ex. 1003). Patent Owner’s arguments are supported by the testimony of Dr. Un-Ku Moon (Ex. 2001; Ex. 2017). 3 Ex. 1012, US Patent No. 6,600,437 B1 (July 29, 2003). 4 Ex. 1013, US Patent No. 4,550,309 (Oct. 29, 1985). 5 Ex. 1014, US Patent No. 5,675,340 (Oct. 7, 1997). 6 Ex. 1015, US Patent No. 7,129,874 B2 (Oct. 31, 2006). 7 Ex. 1017, US Patent No. 6,914,550 B2 (July 5, 2005). IPR2020-01559 Patent 7,286,075 B2 15 II. ANALYSIS A. Legal Standards of Obviousness Section 103(a) forbids issuance of a patent when “the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains.” KSR, 550 U.S. at 406. The question of obviousness is resolved on the basis of underlying factual determinations, including: (1) the scope and content of the prior art; (2) any differences between the claimed subject matter and the prior art; (3) the level of ordinary skill in the art; and (4) when available, objective evidence such as commercial success, long-felt but unsolved needs, and failure of others. Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966); see KSR, 550 U.S. at 407 (“While the sequence of these questions might be reordered in any particular case, the [Graham] factors continue to define the inquiry that controls.”). The Court in Graham explained that these factual inquiries promote “uniformity and definiteness,” for “[w]hat is obvious is not a question upon which there is likely to be uniformity of thought in every given factual context.” Graham, 383 U.S. at 18. The Supreme Court made clear that we apply “an expansive and flexible approach” to the question of obviousness. KSR, 550 U.S. at 415. Whether a patent claiming the combination of prior art elements would have been obvious is determined by whether the improvement is more than the predictable use of prior art elements according to their established functions. Id. at 417. To reach this conclusion, however, it is not enough to show merely that the prior art includes separate references covering each separate limitation in a challenged claim. Unigene Labs., Inc. v. Apotex, Inc., 655 IPR2020-01559 Patent 7,286,075 B2 16 F.3d 1352, 1360 (Fed. Cir. 2011). Rather, obviousness additionally requires that a person of ordinary skill at the time of the invention “would have selected and combined those prior art elements in the normal course of research and development to yield the claimed invention.” Id. A claimed invention may be obvious even when the prior art does not teach each claim limitation, so long as the record contains some reason why one of skill in the art would have modified the prior art to obtain the claimed invention. See Ormco Corp. v. Align Tech., Inc., 463 F.3d 1299, 1307 (Fed. Cir. 2006). And, as a factfinder, we also must be aware “of the distortion caused by hindsight bias and must be cautious of arguments reliant upon ex post reasoning.” KSR, 550 U.S. at 421. This does not deny us, however, “recourse to common sense” or to that which the prior art teaches. Id. B. Obviousness over Confalonieri, claims 16 and 17 Although we address initially claim 16 and 17 challenged as obvious over Confalonieri, we point out that for grounds 1-5, Petitioner relies on Confalonieri as a base reference for the obviousness of claims 1-25. 1. Overview of Confalonieri (Ex. 1012) Confalonieri discloses a switched capacitor digital-to-analog (DAC) convertor for use with an analog-to-digital converter (ADC). Ex. 1012, 1:14-18. Confalonieri explains that it is common to design converters with capacitor arrays split into segments, and “[i]n the case of two segments, the first segment is associated with the least significant bits (LSBs) of the digital input code and a second segment is associated with the most significant bits (MSBs) of the digital input code.” Id. at 1:45-49. Figure 4 of Confalonieri is reproduced below. IPR2020-01559 Patent 7,286,075 B2 17 Figure 4 of Confalonieri, above, illustrates a two segment DAC converter having upper array and lower array including capacitors with binary coded weights for receiving the respective least significant bits (upper array) and the most significant bits (lower array) of digital input code A0-7. As also shown in Figure 4, Confalonieri teaches adding shunt capacitor CATT connected between the common node NSL of the lower array and ground. Id. at 4:40-42. Figure 5 of Confalonieri is reproduced below. IPR2020-01559 Patent 7,286,075 B2 18 Figure 5 of Confalonieri, above, illustrates the three capacitor (CA0-CA2) structure CATT in conjunction with the lower array. Id. at 5:25-27. Register 10 provides a correction digital code to CATT consisting of bits B0, B1, corresponding to a desired offset. Id. at 5:34-39. Confalonieri explains that “[i]n the operation, the capacitors C and 2C are charged according to the digital code, thus varying the voltage at the common node NSL by adding a voltage which compensates the offset.” Id. 2. Claims 16 and 17 Petitioner, relying on the testimony of Dr. Holberg, contends that claims 16 and 17 are obvious over Confalonieri. Pet. 27-31; Ex. 1003 ¶¶ 62-71, 79-87. a) Claim 16 The preamble of claim 16 requires an analog to digital converter which, Petitioner argues, is disclosed by Confalonieri’s analog to digital converter shown in Figure 7 reproduced below. IPR2020-01559 Patent 7,286,075 B2 19 Figure 7 of Confalonieri, above, illustrates an 8 bit SAR type analog to digital converter using the digital to analog converter shown in Figure 4. Id. at 6:12-14. Claim 16[a] requires a switched capacitor array for sampling an analog input signal and converting the sample to a digital output. Petitioner argues that “Confalonieri discloses a switched capacitor array CL0-CU1 for use in sampling input signal Vin and converting the sample to a digital value.” Pet. 29 (citing Ex. 1012, 6:28-55; Fig. 7). For element 16[b], which requires a digital to analog converter responsive to a control word, Petitioner argues that Confalonieri discloses DAC CATT and that bits B0 and B1 are a control word provided by register 10, as shown in Figure 5. Id. (citing Ex. 1012, 5:13-39, 6:51-55). For element 16[c], which requires first “sampling an input signal onto the switched capacitor array,” then applying “a known perturbation to the charge stored on the switched capacitor array,” Petitioner argues that it would have been obvious to a person of ordinary skill in the art “to provide IPR2020-01559 Patent 7,286,075 B2 20 the offset either before or after sampling the input signal.” Id. at 30 (citing Ex. 1003 ¶¶ 79-84). In support of Petitioner, Dr. Holberg testifies that a digital code for adding a voltage to common node NSL for compensating the offset corresponds to the switched capacitor digital to analog converter being operated to make a known perturbation. The common node NSL, being connected to the switch capacitor array, includes the charge stored on the switched capacitor array. Ex. 1003 ¶ 82. Petitioner’s arguments and Dr. Holberg’s testimony raise two critical questions, (1) whether “offset” is a “perturbation,” and if it is, (2) whether a person of ordinary skill in the art would have understood from Confalonieri to apply the offset “after sampling an input voltage onto the switched array” as required by element 16[c]. Ex. 1001, 10:55-56. We address these two questions below. (1) Whether a person of ordinary skill in the art would have understood Confalonieri’s “offset” as a “perturbation” The parties did not provide a specific meaning for the term “offset.” The Authoritative Dictionary of IEEE Standards Terms, 7th Ed. (2000), defines “offset voltage” as “[a] direct-current potential remaining across the comparison amplifier’s input terminals (from the null junction to the common terminal) when the output voltage is zero. . . [i]t is often deliberately introduced into the design of power supplies to reach and even pass zero output volts.” Ex. 3003, 756. In other words, offset, or offset compensation, is a voltage provided to correct for circuit variables that move the input voltages to the comparison amplifier away from ideal, and so that the offset compensation drives the actual amplifier output to zero.8 8 During Final Oral Hearing, Patent Owner’s counsel, Mr. Dichiara, explained “offset” in this way: “assume it’s an older bathroom scale, . . . and you look down at it and it reads two pounds; right? You haven’t stepped on IPR2020-01559 Patent 7,286,075 B2 21 Petitioner argues that offset “is a known perturbation onto the charge stored on the capacitor array.” Pet. 28 (citing Ex. 1003 ¶¶ 62-71). Petitioner relies for support of this position on Dr. Holberg who testifies that “[t]he capacitors CA1 and CA2 (included in the shunt capacitance CATT) are charged according to the digital code, which results in varying the voltage at the common node NSL of the lower array.” Ex. 1003 ¶ 64. However, nowhere in Dr. Holberg’s testimony does he equate the terms, or specifically compare the functions of “offset compensation” and “perturbation.” See, e.g., id. at ¶ 69 (Dr. Holberg explaining that for the implementations described by Confalonieri, “the shunt capacitance CATT is a switched capacitor DAC that adds a voltage that compensates the offset (i.e., an offset compensation voltage).”). Dr. Holberg testifies that a person of ordinary skill in the art would have understood that the three capacitors CA1 and CA2 selectively connecting the voltage reference terminals VREFP and VREFM based on a digital code for adding a voltage to common node NSL for compensating the offset corresponds to the switched capacitor digital to analog converter being operated to make a known perturbation. The common node NSL, being connected to the switch capacitor array, includes the charge stored on the switched capacitor array. Id. ¶ 82 (emphasis added). We find it unclear from this testimony what specifically “corresponds,” whether the physical circuit structures of Confalonieri’s shunt capacitance CATT correspond to the switched capacitor DAC in the ’075 patent, whether the offset functions of shunt capacitance it yet. That’s an offset; right? So what would people do? You adjust the scale. Maybe you turn a screw or whatever it is. That’s offset compensation.” Tr. 51. IPR2020-01559 Patent 7,286,075 B2 22 CATT correspond to the ’075 patent perturbation, or if the terms “offset” and “perturbation” themselves correspond in some manner. Despite the fact that an input signal sample is changed, or corrected, by offset compensation, none of Dr. Holberg’s testimony persuasively supports Petitioner’s argument that offset would have been understood by those of ordinary skill in the art as perturbation or dither. Dr. Holberg, for example, did not take the opportunity during his deposition to explain that Confalonieri’s offset could also be “dither.” Q: . . . Confalonieri does not disclose using CATT for dither, correct?” A: No, he does not. He does not mention dither in-in his patent. Ex. 2018, 74:7-10. As set forth in our claim construction, and based on Dr. Holberg’s testimony and Dr. Moon’s testimony, a person of ordinary skill in the would have understood perturbation not only as “a small change in movement, quality, or behavior of something, especially an unusual change,” but also as describing “the disturbance or agitation of the charge stored on the capacitor array, in a manner that introduces dither into the analog to digital converter.” Section I.G.1. The offset compensation of Confalonieri is “a small change in movement,” and is a “disturbance or agitation of the charge stored on the capacitor array.” The issue is whether the offset compensation is a small change or a disturbance “in a manner that introduces dither.” As discussed above, Dr. Holberg testifies that Confalonieri does not disclose using CATT for dither, and Petitioner has not provided persuasive evidence showing that a person of ordinary skill would have considered that offset compensation introduces dither. Accordingly, we are not persuaded that a person of IPR2020-01559 Patent 7,286,075 B2 23 ordinary skill in the art would have understood Confalonieri’s offset compensation as “perturbation,” or introducing dither in any manner. Even if Confalonieri’s “offset compensation” would have been understood as “perturbation” by a person of ordinary skill in the art, we also find, as discussed below, that Petitioner has not met its burden to show why a person of ordinary skill in the art would have modified Confalonieri to provide perturbation to its circuit after sampling the signal input. (2) Whether a person of ordinary skill in the art would have understood from Confalonieri to apply the offset after sampling the input voltage Claim element 16[c] requires perturbing the charge stored on the switched capacitor array “after sampling.” Ex. 1001, 10:55. Petitioner argues that “[i]t would have been obvious to a skilled artisan to provide the offset either before or after sampling the input signal for use during the SAR bit test . . . as all that is necessary is that the perturbation be provided for the bit test.” Pet. 30. First, as discussed above, we are not persuaded that offset compensation is a known perturbation. Second, assuming for the sake of argument that offset is a perturbation, we agree with Petitioner that Confalonieri does not describe when the offset compensation is applied. See Id. at 28 (“Confalonieri does not contain a detailed discussion of whether the offset perturbation is provided before or after sampling.”). The question remains then, whether Petitioner has shown by a preponderance of the evidence that a person of ordinary skill in the art would have modified Confalonieri to apply the offset, i.e., perturbation, after sampling the input signal onto the lower array. The entirety of Petitioner’s argument, provided in the claim chart in the Petition, is that applying perturbation after sampling “is simply choosing IPR2020-01559 Patent 7,286,075 B2 24 from a finite number of identified predictable solutions, with a reasonable expectation of success.” Id. at 30 (citing Ex. 1003 ¶¶ 79-84). Dr. Holberg testifies that [a]ll that is necessary to make a known perturbation is to establish a first code to the capacitance CATT (i.e., switched capacitor digital to analog converter) during sampling, and then apply a different code to the capacitance CATT after the sampling phase has been completed. Ex. 1003 ¶ 83. This explanation potentially explains how one of skill in art could apply a perturbation, but does not explain why a person of ordinary skill in the art would do so after sampling or why such a person would find the result of applying perturbation after sampling predictable. At best, Dr. Holberg’s testimony describes that a person of ordinary skill in the art could change the offset capacitance code B0, B1 during the course of sampling the input voltage onto the capacitor array and after sampling. And, that this would achieve the claimed perturbation “after . . . sampling.” Id. This explanation, however, describes a result of manipulating Confalonieri’s CATT capacitance circuit and does not articulate sufficient reasoning as to why a person of ordinary skill in the art would have done so. Petitioner’s arguments and Dr. Holberg’s testimony are mostly conclusory and unsupported on this point. First, Petitioner points out what Confalonieri does not expressly disclose, namely “whether the offset perturbation is provided before or after sampling.” Pet. 28 (citing Ex. 1012, 6:28-46; 6:51-55). Second, Dr. Holberg testifies that a perturbation could be effected by “establish[ing] a first code to the capacitance CATT (i.e., switched capacitor digital to analog converter) during sampling, and then apply a different code to the capacitance CATT after the sampling phase has been completed.” Ex. 1003 ¶ 83. However, beyond this statement Dr. IPR2020-01559 Patent 7,286,075 B2 25 Holberg provides no persuasive supporting or evidentiary basis for reaching this conclusion, and no citation to Confalonieri for any disclosure of providing a first offset capacitance code during sampling, then another different capacitance code after sampling. On this point, Petitioner argues that Confalonieri states that “[t]he additional shunt capacitance in the lower array can be used as a component for further functions, such as an offset compensation.” Pet. 26 (citing Ex. 1012, 5:58-60) (emphasis added). In pointing out this language, Petitioner is insinuating that “further functions” includes perturbation. See id. at 28 (Petitioner states that “[t]he provision of offset in Confalonieri discloses the perturbation as claimed.”). We are not persuaded that this is an appropriate reading of Confalonieri. Prior to the language referenced by Petitioner, Confalonieri discusses that “the shunt capacitance operates as a voltage attenuator, so that it is easy to limit the dynamics at the node NSL by a proper selection of this capacitance.” Ex. 1002, 5:46-48. The following paragraph then explains that “[t]he additional shunt capacitance in the lower array can be used as a component for further functions, such as an offset compensation.” Id. at 5:56-58. A plain reading of Confalonieri, in context, is more reasonably understood as indicating that (1) the shunt capacitance CATT “provides a strong improvement of the converter linearity, while the operation speed is as high as the operation speed of the prior art basic design,” (2) “power consumption is also as low as in that prior art design,” and (3) the shunt capacitance can be used for “further functions, such as an offset compensation.” Id. at 5:53-57. Nowhere does Confalonieri indicate that shunt capacitance CATT is considered for perturbation or dithering, or to provide offset during or after the input voltage sample is sampled onto the upper and lower array. Indeed, this interpretation of Confalonieri by IPR2020-01559 Patent 7,286,075 B2 26 Petitioner never references any testimonial support from Dr. Holberg, nor do we find related support in Dr. Holberg’s testimony related to such an interpretation of Confalonieri and claim element 16[c]. See, e.g., Ex. 1003 ¶¶ 79-84. In this way, Petitioner and Dr. Holberg essentially rely on the absence of disclosure in Confalonieri to support their conclusions. We cannot credit Petitioner’s arguments nor Dr. Holberg’s testimony on this matter. Elbit Sys. Of America, LLC v. Thales Visionix, Inc., 881 F.3d 1354, 1358 (Fed. Cir. 2018) (“The PTAB [i]s entitled to weigh the credibility of the witnesses” (alteration in original); quoting Trs. of Columbia Univ. v. Illumina, Inc., 620 F. App’x 916, 922 (Fed. Cir. 2015)). Indeed, the main evidentiary basis and motivation on which Petitioner and Dr. Holberg rely for their conclusion is the express description in the ’075 patent, that is-to apply the perturbation after sampling the input signal. Ex. 1003 ¶ 84 (citing Ex. 1001, 7:46-51, 7:65-8:58, 8:65-9:2). This reliance by Petitioner and Dr. Holberg on the ’075 patent requires some scrutiny. Referring to his prior testimony that it would have been obvious to “establish a first code to the capacitance CATT (i.e., switched capacitor digital to analog converter) during sampling, and then apply a different code to the capacitance CATT after the sampling phase,” Dr. Holberg testifies that The ’075 patent acknowledges this operation. “It is also apparent that during sampling all of the capacitors may be connected to the same reference voltage and that once the sampling phase has been completed, some of the capacitors are switched in response to the pseudorandom number generator.” Id. But this is impermissible hindsight. See Orexo AB v. Actavis Elizabeth LLC, 903 F.3d 1265, 1271 (Fed. Cir. 2018) (“It is inappropriate to use the IPR2020-01559 Patent 7,286,075 B2 27 template provided by the inventor, to render the inventor’s contribution obvious.”); see also Interconnect Planning Corp. v. Feil, 774 F.2d 1132, 1138 (Fed. Cir. 1985) (“The invention must be viewed not with the blueprint drawn by the inventor, but in the state of the art that existed at the time. The invention must be evaluated not through the eyes of the inventor, who may have been of exceptional skill, but as by one of ‘ordinary skill.’”). Here, Petitioner has failed to provide sufficient evidence as to the specific understanding, or principle, within the knowledge of a person of ordinary skill in the art that would have motivated one with no knowledge of the ’075 patent, to perturb the input signal sample “after sampling” onto the switched capacitor array as recited in claim 16. We are also not persuaded that applying perturbation after sampling of an input signal onto a capacitor array of an ADC was one of “a finite number of identified, predictable solutions,” that a person of ordinary skill in the art would have known to pursue, as Petitioner alleges. Pet. 30, see also KSR, 550 U.S. at 421. The ’075 patent explains that known options included conventional dither, as taught for instance by U.S. Patent No. 5,010,339 to Giangano et al. describing applying varying voltage from of a random or sequential number generator to the sampled analog signal prior to its input into the ADC. Ex. 1001, 1:41-55; Ex. 1009, 3:41-4:12. Petitioner has not provided persuasive evidence that perturbing the sampled signal voltage after sampling the input signal onto the capacitor array of the ADC was in any way a known option or obvious to those of ordinary skill in the art at the time of the filing of the application that became the ’075 patent. Based on the complete record now before us, and in answering both questions posed above, we are not persuaded that Petitioner has shown by a preponderance of the evidence that claim 16 is obvious over Confalonieri. IPR2020-01559 Patent 7,286,075 B2 28 b) Claim 17 Claim 17 requires that “the switched capacitor digital to analog converter is an integral part of the switched capacitor array,” and depends directly from independent claim 16. Ex. 1001, 10:60-62. Because we determine that Petitioner has not shown by a preponderance of the evidence that claim 16 is not obvious over Confalonieri we determine that claim 17 is also not obvious over Confalonieri. C. Obviousness over Confalonieri and Hiller, claims 1-7, 9, 10, and 12- 25 Petitioner argues that claims 1-7, 9, 10, and 12-25 would have been obvious over Confalonieri and Hiller. 1. Overview of Hiller (Ex. 1013) Hiller discloses “the use of pseudo-random noise (PRN) as a dither signal for enhancing linearity of an analog-to-digital converter (ADC) by diffusing nonlinearities and discontinuities arising during signal conversion.” Ex. 1013, 1:6-10. Hiller’s Figure 1 is reproduced below. Figure 1 of Hiller, above, illustrates the application of dither by providing PRN source 17 providing dither via DAC 43 to a successive approximation IPR2020-01559 Patent 7,286,075 B2 29 ADC 41 via subtraction of PRN from analog input signal at 44. Id. at 1:12- 17. 2. Claims 16-19 Because we addressed claims 16 and 17 above in view of Confalonieri, for consistency we consider here claims 16-19 in view of Confalonieri and Hiller. a) Whether a person of ordinary skill in the art would have combined Confalonieri and Hiller Considering the teaching of adding offset via shunt capacitor CATT in Confalonieri, Petitioner argues that [a] skilled artisan would have realized that dither as provided in Hiller could be provided in the system of Confalonieri instead of, or in addition to, offset in order to provide the known desirable and well known performance benefits of dither, and would be a “further function” of the additional shunt capacitors, as disclosed in Confalonieri. Pet. 34 (citing Ex. 1003 ¶¶ 155-165). Dr. Holberg testifies that it would have been obvious to one of ordinary skill in the art to provide Hiller’s “PRN source 17 (i.e., sequence generator) to [Confalonieri’s] switches SWC during sampling of the analog input signal onto at least some of capacitors CL0-2, CU3-7 (i.e., the first group of capacitors) or during conversion of a sample of the analog input signal.” Ex. 1003 ¶ 116.9 Dr. Holberg testifies that by adding Hiller’s PRN source 17, “[a]ll that is necessary to apply dither is to establish a first code to the dither DAC during sampling, and then apply a different code to the dither DAC after the sampling phase has been completed.” Id. 9 Dr. Holberg’s testimony regarding claim 16[c] at ¶¶ 158-160 references earlier paragraphs, e.g., ¶¶ 115-117, relating to independent claim 1. IPR2020-01559 Patent 7,286,075 B2 30 It is clear from Hiller that adding dither from a PRN source to the voltage input was known to those of ordinary skill in the art. See Ex. 1013 1:6-10 (Hiller explains that “the use of pseudo-random noise (PRN) as a dither signal for enhancing linearity of an analog-to-digital converter (ADC) by diffusing non-linearities and discontinuities arising during signal conversion is well known.”).10 Importantly, Petitioner does not point us to evidence that Hiller discloses or teaches adding PRN after the input signal is sampled onto the conversion capacitor array. As discussed above, the combined signal in Hiller at node 44 includes the input analog signal 10 minus the dither generated by the PRN. This combined signal is then sampled and quantized by ADC 41 and finally the PRN is subtracted out at summing node 42. Id. at 1:12-15. There is no disclosure in Hiller of applying PRN, and hence dither, to the conversion either during sampling, or after the input signal is sampled onto the conversion array capacitors. See, e.g., id. at 1:62-2:2 (Hiller states that “[i]n the present invention, PRN is introduced via the DAC already presented in a residue class ADC and may be introduced during either first or subsequent passes. . . [a] sample value of PRN is introduced to the input of a DAC. The corresponding analog PRN is then subtracted from the sample and hold output and the result is digitized as the first approximation.”). And, as discussed above with respect to Confalonieri, we find Dr. Holberg’s testimony conclusory, describing simply how a perturbation could be made by “establish[ing] a first code to the capacitance CATT (i.e., switched capacitor digital to analog converter) during sampling, 10 Hiller consistently uses the term “dither” throughout its specification. Therefore, in our discussion of Hiller we refer to the IPR2020-01559 Patent 7,286,075 B2 31 and then apply[ing] a different code to the capacitance CATT after the sampling phase has been completed.” Ex. 1003 ¶ 83. Confalonieri discloses no teaching relative to the functions of perturbation or dither, and Petitioner relies on Hiller’s disclosure for simply teaching a conventional dither technique, adding PRN to an input voltage prior to sampling. Petitioner provides no persuasive explanation that ties together the electronic techniques of offset and dither in the prior art references, except to assert “offset as a known perturbation” which, as discussed above, we do not find persuasive. Pet. 34. Petitioner’s reasoning “that dither as provided in Hiller could be provided in the system of Confalonieri instead of, or in addition to, offset in order to provide the known desirable and well known performance benefits of dither” arguably asserts a desired result, e.g., a more accurate circuit, but does not explain why a person of ordinary skill in the art would have replaced or supplemented offset compensation of an input voltage with dither. Id. This is particularly true where we have persuasive evidence that offset is a different technique and is applied for a different reason and result compared to dither. See Ex. 2017 ¶ 91 (Patent Owner’s declarant, Dr. Moon testifying that “Confalonieri discloses the provision of offset but does not disclose the provision of dither.”); Ex. 2001 ¶ 26 (Dr. Moon testifying that “instead of reducing errors, dither redistributes or smears out the errors.”); Ex. 2018, 74:9-10 (Petitioner’s declarant, Dr. Holberg testifying that Confalonieri “does not mention dither in-in his patent.”). Indeed Dr. Moon provides an explanation of how Confalonieri designed its circuit for improved linearity, as was the state of the art in 2005, not with dither, but by “a circuit design that allows all the capacitors (especially the coupling capacitor) to be sized in integer multiples of a unit IPR2020-01559 Patent 7,286,075 B2 32 capacitance, which improves capacitor matching.” Ex. 2001 ¶ 23 (citing Ex. 1012, 4:36-5:8). Confalonieri expressly discloses any problems of accuracy and linearity related with the dimensioning of the coupling capacitor Cs is solved simply by the addition of a shunt capacitor CATT in the lower array. Since all the capacitors of the converter can be designed as integer numbers of a unit capacitance, all the layout tools normally used for obtaining optimum matching of integrated components can be used. Ex. 1012, 4:65-5:4. Dr. Moon explains further that using capacitance matching for “addressing root causes of DNL directly reduces the DNL errors, dither as described in ’075 patent randomizes the errors. That is[], instead of reducing errors, dither redistributes or smears out the errors. Thus, how dither improves DNL is different than how improving capacitor matching improves DNL.” Ex. 2001 ¶ 26. It is not explained sufficiently by Petitioner, where linearity was already addressed by Confalonieri’s circuit design itself, even if one of ordinary skill in the art could have potentially added dither in an ADC using shunt capacitance CATT instead of, or in addition to compensating for offset, why a skilled artisan would have looked to Hiller’s teaching of dither. Considering the complete record now before us, we are not persuaded that Petitioner has provided sufficient articulated reasoning and supporting evidentiary underpinnings to show that a person of ordinary skill in the art would have been motivated to combine Confalonieri and Hiller. b) Whether Confalonieri and Hiller, even if combined, teach applying a dither to the conversion during sampling of the analog input signal onto a switched capacitor array or during conversion of a sample Even if a person of ordinary skill in the art would have combined Confalonieri and Hiller, we are not persuaded that Petitioner and its IPR2020-01559 Patent 7,286,075 B2 33 Declarant have explained persuasively why a person of ordinary skill in the art would have understood the combination to teach applying a perturbation to the sampled input signal after sampling as claim 16 requires. First, Hiller describes adding dither to an input signal before sampling. Ex. 1013, 1:18- 20, Figs. 1-2. Even assuming that a person of ordinary skill in the art could have applied a perturbation, or dither, via Confalonieri’s shunt capacitance CATT, Petitioner has not pointed to persuasive evidence that Confalonieri discloses or teaches that the perturbation of the sampled input voltage would occur after sampling of the input voltage as called for in claim 16. Second, again considering that Hiller teaches applying dither prior to sampling, we find persuasive Dr. Moon’s testimony that a person of ordinary skill in the art would not have been motivated to replace Confalonieri’s offset compensation, which corrects the converter and the conversion of every sample, with dither because “the Petition’s proposed modification undermines Confalonieri’s goal of obtaining satisfactory conversion linearity, which is also the reason for its designing the coupling capacitor to be an integer multiple of the unit capacitance.” Ex. 2017 ¶ 123 (citing Ex. 1012, 2:65-67). Dr. Moon explains persuasively that “A POSITA would not have been motivated to forfeit offset compensation which corrects the converter and the conversion of every sample, and replace it with dither which corrects no errors and instead averages their effect.” Id. Third, Dr. Holberg’s testimony that a person of ordinary skill in the art could simply add PRN to shunt capacitance CATT does not explain how Confalonieri’s shunt capacitance, or underlying upper and lower capacitor arrays would change, or how this would affect the input sampling and offset procedures being carried out. Dr. Holberg mainly states that “[a]ll that is necessary to apply dither is to establish a first code to the dither DAC during sampling, IPR2020-01559 Patent 7,286,075 B2 34 and then apply a different code to the dither DAC after the sampling phase has been completed.” Ex. 1003 ¶ 116. We have no persuasive evidence or explanation that concomitantly applying, or substituting dither and offset, would have been a simple substitution or how the two separate functions would allocate or alter the shunt capacitance CATT and upper and lower capacitor arrays described in Confalonieri. We credit Dr. Moon’s testimony explaining that adding new components would increase complexity and introduce additional, unwanted sources of noise, just like the prior art (e.g., Giangano) distinguished in the ’075 specification. See, e.g., ’075 patent, 1:53-55. Moreover, if the amount of shunt capacitance is changed (as would be the case under Petitioner’s theory), the size of the coupling capacitor must also change in order to maintain a constant coupling. The resulting coupling capacitor would then no longer be sized to an integer multiple of the unit capacitance, making it so that the coupling capacitor “cannot be designed with the desired accuracy.” Ex. 1012, 3:21. This would undermine Confalonieri’s primary purpose of providing a coupling capacitor of integer multiple unit size. Ex. 2017 ¶ 124. On the complete record before us, we are not persuaded that Petitioner has shown by a preponderance of the evidence that the combination of Confalonieri and Hiller would in fact teach applying perturbation, or dither, to the sampled input voltage, “after sampling” as recited in claim 16. Because claims 17-19 each depend directly from independent claim 16 we determine that Petitioner has not shown by a preponderance of the evidence that claims 17-19 are obvious over Confalonieri. 3. Claims 1-7, 9, 10, and 12-15 Turning now to independent claim 1, limitation 1[c] requires wherein during sampling of the analog input signal onto at least some of the capacitors of the first group of capacitors or during IPR2020-01559 Patent 7,286,075 B2 35 conversion of a sample of the analog input signal an output of the sequence generator is supplied to the switches of the second group of capacitors . . . so as to apply a dither to said conversion. Ex. 1001, 9:53-60. As discussed below, we determine for similar reasons as above that claim 1 is not obvious in view of Confalonieri and Hiller. Petitioner argues that “independent claim[] 1 . . . and dependent claims 2-7, 9, 10, and 12-15, are unpatentable based on Confalonieri and Hiller for essentially the same reasons discussed above with respect to Claim 16.” Pet. 37. Petitioner argues specifically that “a skilled artisan would have realized that dither as provided in Hiller could be provided in the system of Confalonieri instead of, or in addition to, offset in order to provide the known performance benefits of dither.” Id. at 38. As it did for claims 16-19, Petitioner relies on the statement in Confalonieri that “[t]he additional capacitance in the lower array could be used for further functions, such as an offset compensation,” contending that “further functions” means dither. Id. (alteration in original). As we discussed above, we do not find Petitioner’s arguments and evidence persuasive. We are not apprised of sufficient evidence or persuasive testimony that a person of ordinary skill in the art would have simply understood “offset” as adding “dither” to the ADC. Dr. Moon testifies as to a difference between offset and dither being that “[o]ffset compensation corrects the comparison, whereas dither randomizes it yielding an otherwise incorrect result until the dither is subsequently removed.” Ex. 2017 ¶ 119. Dr. Holberg agrees that different from “offset,” for dither “[y]ou’re just randomly varying the signal in the conversion IPR2020-01559 Patent 7,286,075 B2 36 process, somewhere in the conversion process, by a small amount.” Ex. 2018, 28:11-13. And, as discussed above, we are not persuaded that Petitioner has shown by a preponderance of the evidence that a person of ordinary skill in the art would simply have added to, or replaced Confalonieri’s disclosed offset compensation with dither applied through shunt capacitor CATT. We do not understand Confalonieri’s disclosure to teach or disclose that “dither” is a “further function,” where a plain reading of Confalonieri refers to “offset compensation” as the “further function[].” Ex. 1012, 5:58-60. Also, Hiller mainly discloses the conventional addition of dither to an input voltage before sampling, and Petitioner has not pointed to any evidence in Hiller of applying PRN, and hence dither, to the conversion either during sampling, or after the input signal is sampled onto the conversion capacitor array. Ex. 1013, 1:18-20, Figs. 1-2. And, as discussed above with respect to Petitioner’s rationale to combine Confalonieri and Hiller, we find Dr. Holberg’s reasoning and testimony insufficient, describing “[a]ll that is necessary to apply dither is to establish a first code to the dither DAC during sampling, and then apply a different code to the dither DAC after the sampling phase has been completed.” Ex. 1003 ¶ 116. Confalonieri discloses no teaching relative to the functions of perturbation or dither, and Petitioner’s combination relies on Hiller’s disclosure teaching a conventional dither technique, adding PRN to an input voltage prior to sampling. Petitioner’s argument is basically that it would have been a simple substitution to add dither to Confalonieri, or alternatively “[i]f dither was provided instead of offset, the register 10 of Confalonieri would be replaced by a dither generator such as the PRN source 17 of Hiller.” Pet. 34. Petitioner and Dr. Holberg do not provide sufficient IPR2020-01559 Patent 7,286,075 B2 37 explanation or evidence that a person of ordinary skill in the art would simply substitute or add dither to offset compensation except mainly to assert that “[i]t would have been obvious in view of Hiller to provide dither instead of, or in addition to, offset as another known perturbation in the SAR ADC of Confalonieri.” Id. at 38 (citing Ex. 1003 ¶¶ 105-110). Dr. Holberg testifies that a person of ordinary skill in the art would have known to “provide dither instead of, or in addition to, offset for purposes of receiving the known performance benefits of dither, such as improved conversion accuracy.” Ex. 1003 ¶ 105. This asserted reason, however, does not take into account that Confalonieri’s circuit is already improving conversion linearity by compensating for offset and having a coupling capacitor that is an integer multiple of the unit capacitance. See Ex. 1012, 3:25-28 (Confalonieri explaining that “[t]o obtain a satisfactory conversion linearity it is necessary either that the operational amplifier has a low offset, or that a suitable circuit arrangement is provided to cancel the offset.”). Dr. Holberg does not describe why dither would be necessary, i.e., either replacing or complimenting offset compensation, when Confalonieri specifically describes improving conversion accuracy with offset and matching capacitors. Dr. Moon explains persuasively that simply replacing offset with dither undermines Confalonieri’s goal of obtaining satisfactory conversion linearity, which is also the reason for its designing the coupling capacitor to be an integer multiple of the unit capacitance. Id., 2:65-67. A POSITA would not have been motivated to forfeit offset compensation which corrects the converter and the conversion of every sample, and replace it with dither which corrects no errors and instead averages their effect. Ex. 2017 ¶ 123. Dr. Moon testifies that “the main idea in Confalonieri is that the coupling between two segmented capacitor arrays depends on both IPR2020-01559 Patent 7,286,075 B2 38 the size of the coupling capacitor and the amount of shunt capacitance.” Id. ¶ 124. Dr. Moon further testifies that by changing the amount of shunt capacitance CATT in order to add dither, the “coupling capacitor would then no longer be sized to an integer multiple of the unit capacitance, making it so that the coupling capacitor ‘cannot be designed with the desired accuracy.’” Id. (citing Ex. 1012, 3:21). Considering all the evidence of record, we credit Dr. Moon’s testimony and determine that neither Petitioner nor Dr. Holberg have provided a sufficient articulated reasoning supported by evidentiary underpinnings to show by a preponderance of the evidence that a person of ordinary skill in the art, considering Confalonieri, would have looked to Hiller’s teaching of dither for improvement of circuit linearity. Even if it could be done, without a sufficient explanation why a person would have replaced or added dither to Confalonieri’s offset compensation circuit, we are persuaded by Dr. Moon’s testimony that modifying Confalonieri “would undermine Confalonieri’s primary purpose of providing a coupling capacitor of integer multiple unit size.” Id. Even if a person of ordinary skill in the art would have combined Confalonieri and Hiller, we are not persuaded that Petitioner and its Declarant have explained persuasively why a person of ordinary skill in the art would have understood the combination to teach applying dither to the sampled input signal “during sampling,” or alternatively, “during conversion of a sample,” as claim 1 requires. As discussed above, Petitioner admits that “Confalonieri does not contain a detailed discussion of whether the offset perturbation is provided before or after sampling.” Pet. 28 (citing Ex. 1012, 6:28-46; 6:51-55). And, Hiller teaches that it was conventional to apply dither to the input voltage before sampling. See Pet. 40-41 (Petitioner’s IPR2020-01559 Patent 7,286,075 B2 39 claim charts referencing Hiller’s Figures 1 and 2 showing PRN source and DAC 43/23 applying dither to input voltage prior to sampling). Assuming that a person of ordinary skill in the art could have applied dither via Confalonieri’s shunt capacitance CATT, Petitioner has not pointed to persuasive evidence that Confalonieri and Hiller, either together or separately, would have taught or suggested to a person of ordinary skill in the art, that a dither of the sampled input voltage would occur during sampling of the input voltage, or during conversion of a sampled input voltage, as called for in claim 1. Considering that Hiller teaches conventionally applying dither prior to sampling, Petitioner’s declarant, Dr. Holberg testifies that it would have been obvious “to supply an output of the PRN source 17 (i.e., sequence generator) to the switches SWC during sampling of the analog input signal . . . or during conversion of a sample of the analog input signal.” Ex. 1003 ¶ 116. Dr. Holberg testifies further that “[a]ll that is necessary to apply dither is to establish a first code to the dither DAC during sampling, and then apply a different code to the dither DAC after the sampling phase has been completed.” Id. Yet these explanations simply reiterate the claim limitations, essentially stating that a person of ordinary skill in the art, would apply Hiller’s dither via PRN 17, not before sampling as Hiller describes, but during sampling and during conversion as claim 1 calls for. Neither Petitioner nor Dr. Holberg explain persuasively why one of skill in the art would make this change based on Hiller or shown that such a technique was known to those skilled in the art. Essentially, the only explanation we have is Dr. Holberg’s assertion that Confalonieri’s shunt capacitance CATT, is “separate from the capacitors used for testing.” Id. ¶ 118. And, that the capacitors CA0-CA2 in the ’075 patent also are separate, and in the same way do not receive an input voltage, IPR2020-01559 Patent 7,286,075 B2 40 as do the capacitor arrays of the upper and lower array. Indeed, Dr. Holberg relies on the specification of the ’075 patent, testifying that “[t]he ’075 patent acknowledges this operation.” Id. ¶ 117. Dr. Holberg testifies that the ’075 patent explains that “during sampling all of the capacitors may be connected to the same reference voltage and that once the sampling phase has been completed, some of the capacitors are switched in response to the pseudorandom number generator.” By relying on the claims and specification of the ’075 patent to buttress their arguments, Petitioner and Dr. Holberg have ventured into the impermissible territory of hindsight. Even if Petitioner’s comparison of Confalonieri and the ’075 patent is not strictly hindsight, we would expect that there would be stronger evidence from Petitioner detailing how and why dither was known to be used alternatively for, or in conjunction with offset for correcting DNL during or after sampling of the input voltage. What we are left with, however, is mainly Dr. Holberg’s inference that Confalonieri’s shunt capacitance CATT is, on some level, a similar capacitance circuit structure to the ’075 patent, and the insinuation that a person of ordinary skill in the art would have known to operate the circuit in the same way, i.e., to provide offset, or alternatively dither, either during or after sampling of the input voltage onto the upper and lower array, as disclosed and claimed in the ’075 patent. Patent Owner and Dr. Moon persuasively dispute Dr. Holberg’s testimony. PO Resp. 54-60. Patent Owner argues that nowhere in the record, including literature of the time period in which the ’075 patent was filed, is there any disclosure or teaching about using dither at a time besides before sampling onto the switched capacitor arrays in SAR ADCs. Id. at 52. Dr. Moon testifies that “in 2005, researchers in the field of SAR ADCs were IPR2020-01559 Patent 7,286,075 B2 41 focused on improving DNL by addressing the root cause of the problem through improved capacitor and ADC architectures that mitigated the effects of capacitor mismatch.” Ex. 2001 ¶ 16. Dr. Moon points out that a textbook authored by Dr. Holberg and published in 2002, confirms his testimony because the textbook devotes nearly 100 pages to “Digital-Analog and Analog-Digital Converters,” and a significant segment to DNL. See, e.g., Ex. 2014, at 618, 629, 632, 644, 654-57; and Ex. 2015, at 504. In this discussion, much is said about the root causes of DNL with a heavy emphasis on capacitor mismatch - denoted as ΔC. See, e.g., Ex. 2014, at 631-32. In addition to describing how such capacitor errors affect DNL, it also discusses how such errors can be minimized through circuit design. Id., at 644. Id. ¶ 17. Dr. Moon also provides evidence from various sources, including his own research and publication showing “many researchers were working to improve linearity through circuit design, switching configuration, and calibration,” not by using dither. See, e.g., Ex. 2008, 269-272, S.-M. Yoo et al., A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged- capacitor switching, IEEE, TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, vol. 51, no. 5, pp. 269-275, May 2004; see also Ex. 2009 620-621, V. Hariprasath et al., Merged capacitor switching based SAR ADC with highest switching energy-efficiency, ELECTRONICS LETTERS, vol. 46, no. 9, pp. 620-621 (“Hariprasath”). Petitioner responds to Dr. Moon’s evidence asserting that using dither in an SAR ADC was known, for example in U.S. Patent No. 7,015,853 to Wolff, which predates the filing date of the ’075 patent and also discloses “that noise may be stored before or after sampling.” Reply 13, 20 (citing Ex. 1010, 5:13-34, Fig. 11). We recognize that Wolff discloses applying dither with SAR ADCs and that it was not a completely unknown concept. To the IPR2020-01559 Patent 7,286,075 B2 42 extent that Petitioner is using Wolff to argue that a person of ordinary skill in the art would have known to add dither after sampling an input voltage onto a switched capacitor array, Petitioner has not shown where this argument was originally presented in the Petition, and it is therefore a new argument to which Patent Owner has not been given sufficient notice in this proceeding to respond. Petitioner waived this argument because it was not presented in the Petition. See Consolidated Trial Practice Guide, 73 (Nov. 2019) (“Petitioner may not submit new evidence or argument in reply that it could have presented earlier, e.g. to make out a prima facie case of unpatentability.”). Patent Owner’s reliance on Wolff in their Sur-Reply goes to the weight we give Dr. Moon’s testimony in this regard. However, Dr. Moon testifies persuasively that Confalonieri is completely consistent with the techniques addressing the root causes of DNL and capacitor matching shown by the research and references available to those of ordinary skill in the art at the time of the filing of the ’075 patent. Dr. Moon explains that for a person of ordinary skill in the art “during this time, the focus was to address linearity through capacitor matching, circuit topology, and calibration techniques. These approaches were intuitive because they address the root causes of errors, and improve the signal-to-noise ratio, for example.” Ex. 2001 ¶ 25. Dr. Moon’s point, which we find more persuasive, is that dither does not affect the root causes of DNL by reducing errors [i]nstead, it spreads out the errors through randomizing the signal quantization. One effect of randomizing the errors is that noise spurs normally arising from these errors are spread out causing the noise floor to rise with equal energy while reducing the noise spurs and minimizing particularly acute errors. IPR2020-01559 Patent 7,286,075 B2 43 Id. ¶ 27. Based on the complete record before us, we are not persuaded that Petitioner has shown by a preponderance of the evidence that it was an intuitive or a basic inference for a person of ordinary skill in the art, that dither, as taught by Hiller, would have been supplied onto a capacitor array as disclosed by Confalonieri either during sampling onto the switched capacitor array or during conversion of the sample as recited in claim 1. Claims 1-7, 9, 10 and 12-15 depend directly or indirectly from claim 1 and therefore Petitioner has also not shown by a preponderance of the evidence that these claims are unpatentable over Confalonieri and Hiller. 4. Claims 20-23 Independent claim 20 is a method claim but recites similar limitations to claim 1, including: [a] method of applying dither to an analog to digital converter . . . comprising supplying a perturbation control word to the switches of a group of capacitors during sampling of a signal onto at least one capacitor of the array of capacitors or during conversion. Ex. 1001, 11:4-12 (emphasis added). Independent claim 22 is also a method claims and recites: [a] method of adding dither to an input signal to be digitized by an analog to digital converter, . . . wherein after sampling an input signal onto the switched capacitor array the switched capacitor digital to analog converter is operated to make a known perturbation to the charge stored on the switched capacitor array. Ex. 1001, 11:21-12:6 (emphasis added). Petitioner argues that Hiller’s PRN 17 provides a “perturbation control word” and that claims 20 and 22 would have been obvious over Confalonieri and Hiller for the same reasons as claim 1. Pet. 50 (The Petition referencing Petitioner’s arguments for “claims 1[b] and 1[c], above. IPR2020-01559 Patent 7,286,075 B2 44 Pseudo-random noise source method PRN 17 of Hiller provides a perturbation control word.”); see also id. at 37-43, 50-52. For the same reasons as discussed above with respect to claim 1, we are not persuaded that Petitioner has shown by a preponderance of the evidence that independent claims 20 and 22, and also claims 21 and 23 which depend from claim 20, would have been obvious over Confalonieri and Hiller. 5. Claims 24 and 25 Independent claim 24 is somewhat different, in that it includes the limitation of applying dither “to the conversion result.” Ex. 1001, 12:20. In this way, different from claim 22 for instance, the claim does not recite “during,” or “after sampling” but does apply dither to “the conversion result” which nonetheless cannot occur until after the input signal has been sampled. Petitioner argues that claim 24 is essentially obvious for the same reasons as claim 1. See Pet. 57-58 (Petitioner’s claim chart, for claim 24[d], referencing Petitioner’s argument as to claim 1[c]). For the same reasons as discussed above with respect to claim 1, we are not persuaded that Petitioner has shown by a preponderance of the evidence that independent claim 24 and also claim 25 which depends from claim 24, would have been obvious over Confalonieri and Hiller. D. Whether claims 8 and 11 would have been obvious over Confalonieri, Hiller, and Hester, and Confalonieri, Hiller, and Bjornsen Claims 8 and 11 each depend directly upon independent claim 1. Ex. 1001, 10:17-18, 10:27-29. Petitioner’s challenge to claim 8 relies upon the further combination of Confalonieri, Hiller, and Hester, and the challenge to claim 11 relies upon the combination of Confalonieri, Hiller, and Bjornsen. Pet. 59-65. IPR2020-01559 Patent 7,286,075 B2 45 For the same reasons as discussed above with respect to claim 1, we are not persuaded that Petitioner has shown by a preponderance of the evidence that dependent claims 8 and 11, would have been obvious over Confalonieri and Hiller, and Hester, or Confalonieri, Hiller, and Bjornsen. E. Whether claims 1-5, 7, and 9-22 would have been obvious over Cai and Bjornsen Petitioner argues that claims 1-5, 7, and 9-22 would have been obvious over Cai and Bjornsen. Pet. 62-83. 1. Overview of Cai (Ex. 1017) Cai describes “analog to digital conversion systems (A/D converters or ADCs) in which two or more multi-bit successive approximation register (SAR) subconverter stages are cascaded” for “receiving an analog input and providing a digital output.” Ex. 1017, 2:54-59. The “cascaded SAR stages include capacitor arrays and switching systems to selectively couple the capacitors to array inputs, array outputs, or reference voltages for operation in sample, conversion, and residue amplification modes.” Id. at 2:59-62. Cai’s Figure 2A, reproduced below, is a schematic diagram illustrating a pipelined fully differential A/D converter with SAR subconverter stages. Id. at 4:13-16. As shown in Figure 2A, a plurality of cascaded subconverter stages 112, e.g., first subconverter stage 112a and second subconverter IPR2020-01559 Patent 7,286,075 B2 46 stage 112b, receive analog input 132. Id. at 5:10-13. Each SAR stage 112 receives “an analog subconverter stage input signal (e.g., a voltage) 132,144 and provides [a respective] M-bit digital output 120.” Id. at 5:18-21. Digital correction unit 118 receives the respective M-bit “digital output[s] 120 from each of the [subconverter] stages 112 to provide an error corrected N-bit binary digital output 122 corresponding to the analog input signal voltage 132.” Id. at 5:14-18, 5:33-36. Figure 2C, reproduced below, is a schematic diagram detailing an exemplary SAR subconverter stage. Id. at 4:20-22. As shown in Figure 2C, subconverter stage 112 includes a switched capacitor system 160 that has a plurality or array of capacitors 162, a switching system 164, and a mode control system 166. Id. at 6:21-35; see id. at Fig. 2D. For example, “switching system 164 selectively couples individual capacitors in the array 162 to the switched capacitor system input node (VINP or VINM), the switched capacitor system output node (VOUTP IPR2020-01559 Patent 7,286,075 B2 47 or VOUTM), a first reference voltage (VREFP), or a second reference voltage (VREFM).” Id. at 7:44-49; see id. at Fig. 2D. Furthermore, subconverter stage 112 has three modes - sample, conversion, and residue amplification -which sequentially operate to perform various analog to digital conversion steps. Id. at 6:42-47; see id. at 5:54-6:20. In sampling mode, input voltage 132, 144, is received to be “iteratively quantized in the conversion mode.” Id. at 5:59-62. During conversion mode, digital error correction system 118 “corrects for the effects of parasitic capacitances Cp and the offset voltage Vos since the offset voltage and parasitic capacitance effects operate to shift [a] transfer function by a constant amount.” Id. at 5:56-59, 9:28-32; see Fig. 2F. Ultimately, in residue amplification mode, subconverter stage 112 generates “a final digital output 120 (e.g., also M-bit binary) to the subconverter stage digital output correction unit 118 (FIG. 2A).” Id. at 7:20-24. Then, as noted above, “digital correction unit 118 receives the subconverter stage digital outputs 120 from each subconverter stage 112 and generates a digital output of N bits,” i.e., the resultant digital conversion of the original analog signal. Id. at 5:14-18, 5:33-36; see id. at 1:61-66. 2. Overview of Bjornsen (Ex. 1015) Bjornsen describes an analog to digital converter system called a delta-sigma converter, that converts an analog input signal into a digital output signal and includes a noise shaping first stage cascaded with a pipelined second stage.” Ex. 1015, 2:53-56. Bjornsen includes a “digital dither generator . . . to provide a dither signal to the ADC circuit.” Id. at 2:59-60. Figure 1 is a block diagram of an ADC circuit, and is reproduced below. Id. at 2:17-18. IPR2020-01559 Patent 7,286,075 B2 48 As shown in Bjornsen’s Figure 1, above, ADC circuit 10 “converts an analog input signal g(t) into a digital output signal dg(k/N)” in two stages. Id. at 4:44-55. The first stage is a noise shaping stage 12. Id. at 4:47. In that stage, digital dither generator 18 generates dither signal dt(k). Id. at 4:50-51. Analog input signal v(k) is converted into a digital signal d1(k) by ADC1 22; dither signal dt(k) is summed into d1(k) to form combined signal d1t(k). See id. at 4:56-62, 6:60-62. Combined signal d1t(k) is passed to feedback DAC 24 and subtracted from analog input signal g(k) to generate residue signal e(k), fed into noise shaping filter 20. Id. at 6:62-67. In the second stage 14, “noise-shaping filter 20 dithers the input to the ADC2 14, thus improving the overall linearity of the ADC circuit.” Id. at 4:51-53, 5:34-36. Furthermore, dither DAC “includes dither capacitors” to form “digital dither signal dt(k).” Id. at 6:59-6:67. The “magnitude of the dither dt(k) is ¼ of the magnitude of . . . reference voltages. This is achieved by using IPR2020-01559 Patent 7,286,075 B2 49 the dither capacitor 98 equal to ¼ the size of the unit capacitor 96” and “account[s] for the digital dither with ¼ the magnitude of an LSB from the 3.1 bit ADC1 54.” Id. at 7:23-28; see Figs. 5, 6. 3. Independent Claim 1 Considering elements 1[pre]-1[c] of claim 1, as reproduced above, we address below the respective arguments of both parties as to claim 1. a) Petitioner’s Arguments (1) Preamble 1[pre] Petitioner argues “Cai discloses an ADC converter.” Pet. 67 (citing Ex. 1017). (2) Limitation 1[a] Petitioner argues that “Cai discloses a first group of capacitors 162 in switched capacitor system 160 for participation in a successive approximation conversion” and, further, that “[c]apacitors 160 . . . are controllably connected to first and second reference voltages VREFP and VREFM.” Pet. 67-68 (citing Ex. 1017, 2:54-62, 3:6-21, 4:23-27, 5:54-59, 6:21-57, 7:6-65, Figs. 2A-2D). (3) Limitation 1[b] 1[b] a second group of capacitors for applying a dither and having switches for selectively connecting the capacitors to the first reference voltage or the second reference voltage and a sequence generator for generating a sequence of bits, Petitioner argues “Bjornsen discloses a dither DAC 94 including a second group of capacitors 98 controlled by switches 97.” Pet. 68. Petitioner further argues that Bjornsen’s dither generator “provides digital dither signal dt(k)” which is “controlled by a pseudo-random signal.” Id. (citing Ex. 1015, 7:54-57, Fig. 1). Relying on Dr. Holberg, Petitioner asserts that “[o]ne of skill in the art would recognize that a digital dither IPR2020-01559 Patent 7,286,075 B2 50 generator generating a pseudo-random signal generates a sequence of bits.” Pet. 68 (citing Ex. 1003 ¶ ¶ 235-237). Still further, Petitioner argues that Bjornsen discloses selectively connecting the dither capacitors to first and second reference voltages Vr- and Vr+. Id. at 68-69 (citing Ex. 1015, 7:54- 57, Fig. 6). (4) Limitation 1[c] 1[c] wherein during sampling of the analog input signal onto at least some of the capacitors of the first group of capacitors or during conversion of a sample of the analog input signal an output of the sequence generator is supplied to the switches of the second group of capacitors to control whether a given capacitor within the second group is connected by its associated switch to the first reference voltage or to the second reference voltage, so as to apply a dither to said conversion. Petitioner argues that Bjornsen describes switches 97 which “selectively connect the capacitors 98 to the reference voltages Vr- and Vr+ to provide dither.” Pet. 69 (citing Ex. 1015, 6:57-7:38, Fig. 6). Relying on Dr. Holberg, Petitioner argues “[i]t would have been obvious to a skilled artisan to supply the output of the sequence generator of Bjornsen to the switches of the second group of capacitors at any point in time so that the dither will be applied to the conversion, as that is the specific purpose of applying dither.” Id. (citing Ex. 1003 ¶¶ 238-240). Furthermore, Petitioner asserts that, “[i]t would have been obvious to a skilled artisan to provide a switched capacitor dither DAC as disclosed in Bjornsen in the switched capacitor ADC of Cai in order to provide the known desirable benefits of providing dither in an ADC.” Id. at 66. Petitioner explains that the combination of Cai and Bjornsen “is simply combining prior art elements according to known techniques to yield predictable results.” Id. (citing Ex. 1003 ¶¶ 235-237). Petitioner explains IPR2020-01559 Patent 7,286,075 B2 51 that its combination providing Bjornson’s “dither DAC including switched capacitors separate from the SAR capacitors in Cai . . . would facilitate precise control over the provision of dither without interfering with the feedback capacitors.” Id. at 66-67 (citing Ex. 1003 ¶¶ 235-237). b) Patent Owner’s Arguments Patent Owner makes two main arguments. First, Patent Owner argues that Petitioner has not established sufficient motivation to combine Cai and Bjornsen and that the combination is driven by hindsight based on the ’075 patent itself. PO Resp. 29-33. Second, Patent Owner argues that even if Cai and Bjornsen are combined, the combination still would not have disclosed or suggested to those of ordinary skill in the art to apply dither during sampling, during conversion, or after sampling onto a switched capacitor array as required by the claims. Id. at 33-42. We address these arguments and the parties’ evidence below. c) Whether Petitioner has shown sufficiently a reason to combine Cai and Bjornsen Patent Owner argues that a person of ordinary skill in the art would not have combined Cai and Bjornsen because, although dither was known in the context of delta-sigma converters like Bjornsen’s, as well as SAR ADCs like Cai’s, “the problems that delta-sigma converters (like Bjornsen) typically use dither for are not experienced in a SAR ADC like Cai.” PO Resp. 30. According to Patent Owner, for SAR ADCs like Cai’s, a person of ordinary skill in the art understood “that dither could be added to the input signal to randomize quantization errors and to avoid missing codes,” i.e., to improve linearity. Id. at 29. But, as Patent Owner points out, Bjornsen applies dither to perform gain calibration, not for linearity issues because IPR2020-01559 Patent 7,286,075 B2 52 there are no missing codes in delta-sigma converters. Id. at 30 (citing Ex. 1015, 5:52-65). Patent Owner points out also that different from SAR ADCs “dither is conventionally used in delta-sigma architectures to address an issue called ‘idle tones.’” Id. (citing Ex. 2018, 27:6-10). Patent Owner argues specifically that SAR ADCs such as disclosed in Cai, “do not experience the problem of idle tones.” Id. (citing Ex. 2018, 28:6-8). And, Patent Owner argues that neither Petitioner nor Dr. Holberg have explained “how Cai suffers from gain errors, which amplifier in Cai would supposedly benefit from gain calibration, or how the combination would actually provide gain calibration.” Id. (citing Ex. 2017 ¶ 70). Additionally, Patent Owner argues that SAR ADCs, like Cai, do not use integrating DACs as disclosed by Bjornsen. Id. at 31 (citing Ex. 2018, 55:4-10). According to Patent Owner, in order to achieve the combination “Petitioner selectively extracts particular capacitors from the integrating DAC and grafts them into Cai’s SAR ADC to solve a problem (missing codes in a SAR ADC) that Bjornsen doesn’t experience.” Id. (citing Ex. 2017 ¶ 70). Based on these arguments and evidence directed towards substantive differences between the function of SAR ADCs and delta sigma converters, Dr. Moon testifies that “[a] POSITA therefore would not have been inclined to consult teachings of an integrating DAC in a delta-sigma ADC to modify Cai’s SAR ADC, when Cai does not use that type of DAC and is a different type of ADC.” Ex. 2017 ¶ 70. Also, Patent Owner argues that Petitioner has not explained or shown how Cai’s SAR ADC would remove dither from the sampled input signal output. PO Resp. 32. Dr. Moon testifies that “adding dither to a Nyquist IPR2020-01559 Patent 7,286,075 B2 53 rate converter without removing it adds noise to the ADC and materially degrades the ADC performance. This renders the proposed combination worse than Cai alone-noise is added, and no provision is made for removing it.” Ex. 2017 ¶ 71. Petitioner responds, arguing that for both SAR and delta-sigma converters “dither and its benefits are the same for both types of ADCs. Applying dither reduces errors.” Reply 27 (citing Ex. 1025, 26-27; Ex. 1010, 1:67-2:3; Ex. 1016, 2:52-60, 5:34-36; Ex. 1023, 31:21-32:18, 33:2- 18). According to Petitioner, this is because “Cai’s pipelined ADC comprises a residue amplifier 174 in each stage . . . [a] POSITA would understand that an amplifier in a pipelined converter, such as Cai’s residue amplifier 174, is susceptible to gain errors.” Id. at 28 (citing Ex. 1023, 112:9-12). Petitioner points to Dr. Moon’s testimony agreeing that Cai’s residue amplifier 174 would be susceptible to gain errors. Id. (citing Ex. 1023, 112:9-12). Based on these arguments and evidence, Petitioner reasons that “[i]t would have been [o]bvious to combine Bjornsen and Cai in light of this improvement in linearity and correction of gain errors.” Id. With respect to the issue of dither removal following signal conversion, Petitioner argues that “ADI admits that ‘the dither signal is typically not removed because it is just a small test signal with a negligible effect on the output.’” Id. at 29 (quoting PO Resp. 32). Petitioner argues that combining Bjornsen with Cai would function the same way with a dither signal that is ¼ the size of the reference voltages. Id. (citing Ex. 1015, 7:23-24; Pet. 61; Ex. 1003 ¶ 218). Patent Owner responds, arguing that Petitioner has changed its argument from the Petition. PO Sur-Reply 23-24. Patent Owner contends that in the Petition, Petitioner argued for adding Bjornsen’s dither within IPR2020-01559 Patent 7,286,075 B2 54 Cai’s SAR stages. Id. at 24. Now, Patent Owner argues, Petitioner is adding Bjornsen’s dither to the residue amplifier 174 between Cai’s pipeline stages. Id. As a whole, we find Patent Owner and Dr. Moon’s testimony the most persuasive. The Petition states that “[i]t would have been obvious to a skilled artisan to provide a switched capacitor dither DAC as disclosed in Bjornsen in the switched capacitor ADC of Cai in order to provide the known desirable benefits of providing dither in an ADC.” Pet. 66. This is supported by reference to Dr. Holberg’s testimony which explains “Cai discloses a pipelined A/D conversion system comprising a switched capacitor system 160 in each SAR stage 112, so adding additional switched capacitors to apply a dither is applicable to Cai’s system.” Ex. 1003 ¶ 236 (citing Ex. 1017, 6:28-32). We reproduce Cai’s Figure 2C below. IPR2020-01559 Patent 7,286,075 B2 55 Cai’s Figure 2C, above, illustrates switched capacitor system 160 including mode control system 166, switching system 164, and capacitors 162. We agree with Patent Owner that Petitioner’s arguments and evidence in the petition do not explain why Bjornsen’s dither would have been applicable in Cai to address amplifier gain error. Petitioner points to no persuasive evidence in Cai, the Petition, or from Dr. Holberg for that matter, that amplifier gain was a problem in Cai, or of using dither from Bjornsen to address gain errors in Cai. See Reply 27-28 (citing Ex. 1023, 112:9-12) (Petitioner relying mainly on Dr. Moon’s deposition testimony in which he agreed that residue amplifier 174 were susceptible to gain errors). The reason, Dr. Holberg originally testified to was that, “[i]t would have been obvious to a POSITA to combine Cai and Bjornsen to provide dither for purposes of receiving the known performance benefits of dither, such as improved conversion accuracy.” Ex. 1003 ¶ 235. Indeed, Petitioner’s Reply, fails to cite to any persuasive evidence either in the references themselves, or from Dr. Holberg, that a person of ordinary skill in the art would have been motivated to add dither for correcting amplifier gain from Bjornsen’s sigma delta converter, into Cai’s SAR ADC. In fact, Dr. Holberg fails to provide a persuasive rationale or reasoning for adding Bjornsen’s dither to Cai, mainly testifying that “[i]t would have been obvious to a POSITA that Cai’s system, a known device, is ready for improvement, and Bjornsen performs a known technique to achieve that improvement.” Ex. 1003 ¶ 237. This is essentially a simple substitution argument and is not sufficient reasoning in light of the functional and structural differences in the circuits and the evidence that a person of ordinary skill in the art understood that dither is used for different purposes in Cai and Bjornsen. IPR2020-01559 Patent 7,286,075 B2 56 Overall, besides the lack of an articulated reason and supporting evidentiary underpinnings, we find that Petitioner has failed to point to persuasive evidence of motivation to combine Cai and Bjornsen. We are apprised of no teaching in Bjornsen that would have motivated a person of ordinary skill in the art to add dither for improving DNL and conversion accuracy in Cai, and no hint in Cai that there is a necessity for correcting amplifier gain. Based simply on Petitioner and Dr. Holberg’s conclusion that dither could be added to Cai, we are not apprised of a persuasive reason why a person of ordinary skill in the art would have combined Cai and Bjornsen. See Belden Inc. v. Berk-Tek LLC, 805 F.3d 1064, 1073 (Fed. Cir. 2015) (The Federal Circuit explaining that “obviousness concerns whether a skilled artisan not only could have made but would have been motivated to make the combinations or modifications of prior art to arrive at the claimed invention.”). d) Whether Cai and Bjornsen, even if combined, teach applying a dither to the conversion during sampling of the analog input signal or during conversion of a sample Even if Cai and Bjornsen are combined, Patent Owner argues, the limitations of independent claim 1 “distinguish the claims from the known prior art approach to applying dither, where the input signal (rather than the converter) is randomized before sampling the input signal onto the SAR converter’s capacitor array.” PO Resp. 38. Claim 1[c] requires that dither is applied “during sampling of the analog input signal onto at least some of the capacitors of the first group of capacitors or during conversion of a sample of the analog input signal.” Ex. 1001, 9:53-56. Considering the full record now before us, we find persuasive Patent Owner’s position that “[n]o IPR2020-01559 Patent 7,286,075 B2 57 explanation or evidence is provided as to why the specifically recited timing-during or after sampling-is obvious.” PO Resp. 38. Petitioner’s main substantive argument and evidence, that the combination of Cai and Bjornsen meets the limitations of claim 1[c] is the following assertion: [i]t would have been obvious to a skilled artisan to supply the output of the sequence generator of Bjornsen to the switches of the second group of capacitors at any point in time so that the dither will be applied to the conversion, as that is the specific purpose of applying dither. Pet. 69 (citing Ex. 1003 ¶¶ 238-240). First, this is not entirely accurate because, as discussed above, dither can be applied to address gain error as well, as taught by Bjornsen. See Ex. 2017 ¶ 69 (Dr. Moon testifying that “Bjornsen uses its dither not to address missing codes but instead to perform gain calibration.”). Second, Petitioner has pointed to no evidence in either Cai or Bjornsen that these references alone or in combination provide disclosure or discussion relevant to when dither is applied to the conversion. Petitioner relies on Dr. Holberg’s testimony that when considering Bjornsen’s Figure 6, “[i]t would have been obvious to a POSITA that the switches 97 connecting the dither capacitors 98 to the positive reference voltage Vr+ or to the negative reference voltage Vr- would be so as to apply a dither to the conversion.” Bjornsen’s Figure 6 discloses an integrating dither DAC 90. Ex. 1015, 2:29-31. However, we credit the testimony of Patent Owner’s declarant, Dr. Moon, who points out that Cai does not discuss or teach dither, and “that Bjornsen discloses applying dither by combining a dither signal with an analog input signal at a summing node,” not by applying dither to the conversion. Ex. 2017 ¶ 77. Moreover, Dr. Moon provides unrebutted testimony that “SAR ADCs like Cai are IPR2020-01559 Patent 7,286,075 B2 58 fundamentally different architectures from delta-sigma ADCs for many reasons . . . , and further including that SARs do not use integrating DACs.” Id. ¶ 70. For Petitioner, Dr. Holberg testifies that “[a]ll that is necessary to apply dither is to establish a first code to the dither DAC during sampling, and then apply a different code to the dither DAC after the sampling phase has been completed.” Ex. 1003 ¶ 239. Again, the possibility that dither could be provided in Cai’s circuit to the conversion during or after sampling of an input signal onto a capacitor array does not explain why a person of skill in the art would have done so. Belden, 805 F.3d at 1073. Patent Owner’s position is especially persuasive where we have evidence and unrebutted testimony from Dr. Moon that the prior art, like Bjornsen, mainly shows applying dither to an input signal prior to being sampled onto a capacitor array. Ex. 2017 ¶ 63; see also id. ¶¶ 33-34 (Dr. Moon testifying that “conventional dither techniques randomized an input signal by a known random amount. The combined signal is then sampled and quantized, and the dither amount is then removed from the digital result representing the combination of the input signal and dither”) (citing Ex. 1009, 1:41-55, 4:7-22). We find Dr. Moon’s testimony the most persuasive that the applied dither in claim 1 “randomizes the comparison equations during a bit trial and is thus distinguishable from prior art approaches that provide an input signal that has already been randomized prior to entry in the converter.” Id. ¶ 72. Therefore, even if Bjornsen’s dither could be applied in Cai, we are not persuaded that Petitioner has shown by a preponderance of the evidence that a person of ordinary skill in the art would have considered applying dither during sampling or during conversion of the sampled input signal. IPR2020-01559 Patent 7,286,075 B2 59 Claims 2-5, 7, and 9-15 depend directly or indirectly from claim 1 and therefore Petitioner has also not shown by a preponderance of the evidence that these claims are unpatentable over Cai and Bjornsen. 4. Claims 16-19 As discussed above, independent claim 16 recites, in part, making a known perturbation “after sampling an input signal onto the switched capacitor array.” Ex. 1001, 10:55-56. As set forth in our claim construction, perturbation is “a small change in movement, quality, or behavior of something, especially an unusual change,” and “describes the disturbance or agitation of the charge stored on the capacitor array, in a manner that introduces dither” into the analog to digital converter.” Section I.G. In their arguments, the parties do not substantively distinguish the difference between “dither” and “perturbation” with respect to the combination of Cai and Bjornsen. Compare Pet. 78 (Petitioner equating “perturbation (dither)”), with PO Resp. 34 (Patent Owner stating that “[i]ndependent claims 16, 20, 22, and 24 similarly require applying dither to the converter.”). Considering our claim construction and that the parties’ arguments that do not substantively distinguish between the independent claims based on the terms “dither” and “perturbation,” our analyses with respect to the prior art relied on for Petitioner’s challenges in this Decision For the same reasons as discussed above with respect to claim 1, Petitioner has not provided sufficient articulated reasons and evidentiary underpinnings that Cai and Bjornsen are properly combined, and even if they are combined, do not teach or disclose, alone or in combination, that a perturbation is applied “after sampling an input signal.” Accordingly, we are not persuaded that Petitioner has shown by a preponderance of the evidence that a person of ordinary skill in the art would have considered IPR2020-01559 Patent 7,286,075 B2 60 applying dither, or a perturbation, as taught by Bjornsen, after sampling of the input signal, as called for in independent claim 16. Claims 17-19 depend directly from claim 16 are thus not obvious over Cai and Bjornsen. 5. Claims 20-22 Independent claim 20 is a method claim but recites similar limitations to claim 1, including: [a] method of applying dither to an analog to digital converter . . . comprising supplying a perturbation control word to the switches of a group of capacitors during sampling of a signal onto at least one capacitor of the array of capacitors or during conversion. Ex. 1001, 11:4-12 (emphasis added). Independent claim 22 is also a method claims and recites: [a] method of adding dither to an input signal to be digitized by an analog to digital converter, . . . wherein after sampling an input signal onto the switched capacitor array the switched capacitor digital to analog converter is operated to make a known perturbation to the charge stored on the switched capacitor array Ex. 1001, 11:21-12:6 (emphasis added). Petitioner argues that independent claim 20 is obvious for the same reasons as claim 1, and claim 22 is obvious for the same reasons as claim 16. Pet. 80-83. For the same reasons as discussed above with respect to claim 1 and claim 16 we are not persuaded that Petitioner has shown by a preponderance of the evidence that independent claims 20 and 22, and also claim 21 which depends from claim 20, would have been obvious over Cai and Bjornsen. IPR2020-01559 Patent 7,286,075 B2 61 III. CONCLUSION Petitioner has not proved by a preponderance of the evidence that the challenged claims of the ’075 patent would have been obvious. Claims 35 U.S.C. § Reference(s)/ Basis Claims Shown Unpatentable Claims Not Shown Unpatentable 16,17 103 Confalonieri 16, 17 1-7, 9, 10, 12-25 103 Confalonieri and Hiller 1-7, 9, 10, 12-25 8 103 Confalonieri, Hiller and Hester 8 11 103 Confalonieri, Hiller, and Bjornsen 11 1-5, 7, 9-22 10-3 Cai and Bjornsen 1-5, 7, 9-22 8 103 Cai, Bjornsen, and Hester 8 Overall Outcome 1-25 IV. ORDER For the reasons given, it is ORDERED that, based on a preponderance of the evidence claims 1- 25 of the ’075 patent have not been shown to be unpatentable; and FURTHER ORDERED that, because this is a Final Written Decision, any party to the proceeding seeking judicial review of this Decision must comply with the notice and service requirements of 37 C.F.R. § 90.2. IPR2020-01559 Patent 7,286,075 B2 62 PETITIONER: Mehran Arjomand Jean Nguyen Richard Hung Alex Yap Hector Gallegos MORRISON & FOERSTER LLP marjomand@mofo.com jnguyen@mofo.com rhung@mofo.com ayap@mofo.com hgallegos@mofo.com David Fehrman DSA LEGAL SOLUTIONS PC dfehrman@dsa-legal.com PATENT OWNER: Peter Dichiara Scott Bertulli Cynthia Vreeland Brian J. Lambson WILMER CUTLER PICKERING HALE AND DORR, LLP peter.dichiara@wilmerhale.com scott.bertulli@wilmerhale.com cynthia.vreeland@wilmerhale.com Brian.lambson@wilmerhale.com Michael Diener Claire Rollor ANALOG DEVICES, INC. Michael.Diener@analog.com Claire.Rollor@analog.com IPR2020-01559 Patent 7,286,075 B2 63