Analog Devices, Inc.

Patent Trials and Appeals Board

Jan 21, 2022

IPR2020-01210 (P.T.A.B. Jan. 21, 2022)

Trials@uspto.gov Paper No. 30 571-272-7822 Entered: January 21, 2022 UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD., Petitioner, v. ANALOG DEVICES, INC., Patent Owner. ____________ IPR2020-01210 Patent 10,250,250 B2 ____________ Before JEFFREY S. SMITH, SCOTT A. DANIELS, and GEORGIANNA W. BRADEN, Administrative Patent Judges. DANIELS, Administrative Patent Judge. JUDGMENT Final Written Decision Determining All Challenged Claims Unpatentable 35 U.S.C. § 318(a) Denying Motion to Exclude 37 C.F.R § 42.64(c) IPR2020-01210 Patent 10,250,250 B2 2 I. INTRODUCTION A. Background On July 17, 2020, Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. (collectively, “Petitioner”) filed a Petition requesting an inter partes review of claims 1-3, 11-18, and 20-22 of U.S. Patent No. 10,250,250 B2, issued on April 2, 2019 (Ex. 1001, “the ’250 patent”). Paper 2 (“Pet.”). Analog Devices, Inc. (“Patent Owner”) filed a Preliminary Response. Paper 6 (“Prelim. Resp.”). Following our Institution Decision (Paper 9, “Inst. Dec.”), Patent Owner filed a Response. Paper 12 (“PO Resp.”). Petitioner filed a Reply. Paper 15 (“Reply”). Patent Owner filed a Sur-Reply. Paper 18 (“PO Sur- Reply”). A hearing was held on October 26, 2021. A transcript of the hearing has been entered as Paper 29 (“Tr.”). Petitioner filed a Motion to Exclude Evidence, which Patent Owner opposes. Papers 23, 24, 28. We have jurisdiction under 35 U.S.C. § 6. This Final Written Decision is entered pursuant to 35 U.S.C. § 318(a). We determine that claims 1-3, 11-18, and 20-22 are unpatentable. We deny Petitioner’s Motion to Exclude Evidence. B. Additional Proceedings The parties identify the following district court proceeding concerning the ’250 patent: Analog Devices, Inc. v. Xilinx, Inc., No. 1:19-cv-02225- RGA (D. Del.). Pet. 120; Paper 5, 2. C. Real Party-in-Interest The Petition identifies Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. as Real Parties-in-Interest. Pet. 120. Patent Owner identifies itself as the Real Party-in-Interest. Paper 5, 2. IPR2020-01210 Patent 10,250,250 B2 3 D. The ’250 Patent (Ex. 1001) The ’250 patent describes input circuitry for analog to digital converters (ADCs) that convert analog input signals to digital output signals. Ex. 1001, 1:15-17. More specifically, the ’250 patent describes embodiments of bootstrapped switching circuits for use in an ADC to ensure that the ADC’s sampling switch turns on quickly enough to allow for the high-speed sampling (for example, in the range of Giga-samples per second) of input signals such as high speed, wide bandwidth RF signals. See, e.g., id. at codes (54), (57), 2:20-30, 2:49-59, 3:28-36. Figure 2 is reproduced below. Figure 2 of the ’250 patent depicts a bootstrapped switching circuit 200 for turning on transistor MN 108 (sampling switch) quickly enough to allow input signal VINX to be sampled onto a sampling capacitor. Id. at 3:29-31, 3:44-45. Bootstrapped switching circuit 200 includes MN 108, which IPR2020-01210 Patent 10,250,250 B2 4 receives VINX at its source and has a drain connected to one plate of a sampling capacitor. Id. at 3:45-49. Bootstrapped switching circuit 200 also includes a bootstrapped gate voltage generator for generating gate voltage signal VBSTRP for driving the gate of MN 108. Id. at 3:49-53. When clock signal CLK goes low (CLKB and charging phase clock signal CLKBBST are both high), MN 108 is expected to turn off. Id. at 4:14- 15. During this “charging phase,” transistors MN 224 and MN 210 are turned on to charge voltage VBOOT across boot capacitor CBOOT, whose top plate is connected to VDD and bottom plate to VSS. Id. at 4:16-22. Also during this phase, transistor MP 214 is on, its drain (node X) is at VDD, and output transistor MP 202 is off. Id. at 4:28-36. When CLK goes from low to high (and inverted clock signal CLKB from high to low), a positive feedback loop of the bootstrapped gate voltage generator is activated, causing VBSTRP to be driven high quickly and enough voltage VGS across the gate and source for MN 108 to turn on. Id. at 3:65- 67, 4:5-8. More specifically, transistor MP 204 is turned on, pulling the drains of transistors MN 208 and MN 206 high or close to VDD, which makes the VBSTRP node go high. Id. at 4:38-44. VBSTRP drives the gates of transistor MN 216 and input transistor MN 212 (which receives VINX), through which the gate of MP 202 (node X) gets tied to VINX. Id. at 4:45-54. The gate of output transistor MP 202 therefore has a voltage of VINX, and its source has a voltage VINX +VBOOT. MP 202 turns on, making VBSTRP rise to VINX +VBOOT, which increases the voltage across the gate and the source VGS (that is, VBSTRP-VINX =VBOOT) and causes MN 108 to turn on. Id. at 4:57-62. As VBSTRP rises, the positive feedback of VBSTRP rising loops IPR2020-01210 Patent 10,250,250 B2 5 through MN 216 and MN 212, which keeps VBSTRP rising and enables a fast turn on of MN 108. Id. at 4:62-67. The ’250 patent further describes that, at the startup of the positive feedback loop, the gate of MP 202 (node X) may not get tied to VINX quickly enough because MN 216 and MN 212 may be slow to turn on. Id. at 5:1-6. To address this slowdown, the ’250 patent describes a bootstrapped switching circuit including a jump start circuit. Figure 3 of the ’250 patent depicts such a bootstrapped switching circuit and is reproduced below. Figure 3 of the ’250 patent depicts bootstrapped switching circuit 300 including jump start circuit 302. Id. at 5:37-39. As shown in Figure 3, bootstrapped switching circuit 300 builds upon bootstrapped switching circuit 200 of Figure 2 by adding jump start circuit 302 and additional transistor MN 218. See id. at 5:37-7:19. When the positive feedback loop begins and MN 212 is turning on, jump start circuit 302 may turn on MP 202 IPR2020-01210 Patent 10,250,250 B2 6 for a limited period of time. Id. at 6:19-22. Jump start circuit 302 is coupled to the gate of MP 202 (node X) and may output a signal at node X to turn on MP 202 momentarily when CLKB goes low to jump start the positive feedback loop action. Id. at 6:22-28. After the limited period of time, jump start circuit 302 may cease to turn on MP 202 and allow the positive feedback loop to drive MP 202 (bring node X to VINX). Id. at 6:28- 31, 6:34-37. Bootstrapped switching circuit 300 may also include an additional transistor MN 218-its gate connected to CLK, its source connected to the drain of MN 212 and source of MN 216, and its drain connected to node X (gate of MP 202). Id. at 7:4-9. When CLK goes high at the startup of the positive feedback loop, MN 218 is turned on to help tie node X to VINX, in an attempt to overcome the slow turn on MN 216. Id. at 7:9-15. Figures 4A-B of the ’250 patent are reproduced below. Figures 4A-B depict an exemplary implementation for a jump start circuit according to some embodiments of the ’250 patent. Id. at 7:36-38. As shown in Figure 4A, a jump start circuit may include a transistor MN 404 that is turned on for a limited period of time by a delayed version of the inverted clock signal CLKBDEL at the gate that remains high when CLKB at IPR2020-01210 Patent 10,250,250 B2 7 the source goes low. Id. at 7:38-48. When the delay period is over, CLKBDEL goes low to turn MN 404 off. Id. at 7:48-7:50. This jump start circuit therefore pulls node X towards CLKB’s low logic level momentarily before quickly letting go of node X to allow the positive feedback loop to continue its operation. Id. at 7:50-52. As shown in Figures 4B, a jump start circuit may include two inverters for generating CLKBDEL based on CLKB. Id. at 7:56-58. E. Illustrative Claim Of the challenged claims, claims 1, 15, and 20 are independent. Claim 1 is reproduced below, with formatting and bracketed lettering added for clarity and certain disputed limitations highlighted in italics. 1. A bootstrapped switching circuit with accelerated turn on, comprising: [a] a sampling switch to receive a voltage input signal and a gate voltage; [b] a bootstrapped voltage generator comprising a positive feedback loop, wherein the positive feedback loop is activated by a clock signal to generate the gate voltage for turning on the sampling switch, and [c] the positive feedback loop comprises: an output transistor to output the gate voltage of the sampling switch, and an input transistor to receive the voltage input signal and to be driven by the gate voltage as positive feedback; and [d] a jump start circuit to turn on the output transistor, and [e] [the jump start circuit] to cease turning on the output transistor after a limited period of time during a startup of the positive feedback loop to allow the positive feedback loop to continue assisting the output transistor in generating the gate voltage for turning on the sampling switch. Ex. 1001, 23:61-24:12. IPR2020-01210 Patent 10,250,250 B2 8 F. Level of Ordinary Skill in the Art Petitioner proposes that a person of ordinary skill in the art would have at least a Master’s of Electrical Engineering degree and experience with analog circuitry, or a Bachelor’s degree in Electrical Engineering and two years of experience in analog circuit design. Pet. 12 (citing Ex. 1002 ¶¶ 78-80). Patent Owner does not address the level of ordinary skill in its Response. See generally PO Resp. Patent Owner’s declarant, Dr. Pavan Hanumolu, testifies that Petitioner’s proposed level of education and experience for a person of ordinary skill is reasonable. Ex. 2004 ¶ 9. For purposes of this decision, we adopt Petitioner’s proposal because it is consistent with the ’250 patent and the asserted prior art and not disputed by Patent Owner. G. Claim Construction We interpret claims in the same manner used in a civil action under 35 U.S.C. § 282(b) “including construing the claim in accordance with the ordinary and customary meaning of such claim as understood by one of ordinary skill in the art and the prosecution history pertaining to the patent.” See Changes to the Claim Construction Standard for Interpreting Claims in Trial Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg. 51,340, 51,358 (Oct. 11, 2018) (amending 37 C.F.R. §42.100(b) effective November 13, 2018) (now codified at 37 C.F.R. § 42.100(b) (2019)).1 Only terms that are in controversy need to be construed, and then only to the extent necessary to resolve the controversy. Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017). 1 This rule change applies to the instant Petition because it was filed after November 13, 2018. See id. IPR2020-01210 Patent 10,250,250 B2 9 The parties do not dispute Petitioner’s assertion of the meaning and structure corresponding to the means-plus-function limitations in claim 20, as set forth in the Petition. Compare Pet. 13-14, with Prelim. Resp. 17. However, the parties dispute the meaning of two claim terms, “jump start circuit” and “startup.” PO Resp. 15-20; Reply 2-5. 1. jump start circuit Interestingly, the parties’ specific constructions for “jump start circuit” are different, yet neither are incorrect. Considering Figures 2 and 3 of the ’250 patent above, this is because the consequence of jump starting output transistor MP 202, as Patent Owner argues, is that transistor MN 108, the sampling switch also turns on more quickly, as Petitioner argues. Our claim construction is based not so much on an actual dispute over what the parties consider the “jump start circuit” is, or does, but recognizes that both parties consider this limitation important in the analysis and understanding of the claims in terms of the prior art. Patent Owner argues that “jump-start circuit” would be understood by a person of ordinary skill in the art “as circuitry that quickly turns on the output transistor.” PO Resp. 15 (citing Ex. 2009 ¶¶ 28-29; Ex. 2007, 2 (Cambridge Dictionary providing one meaning of “jump-start” as “to start or improve something more quickly by giving it extra help.”)). Patent Owner argues that its proposed construction is consistent with the ’250 patent Specification describing that “the ‘jump start circuit . . . quickly turns on transistor MP 202 (the output transistor) at the startup of the positive feedback loop action.’” Id. (citing Ex. 1001, 5:29-31). Patent Owner contends that, as a whole, the claims “should be interpreted to require a IPR2020-01210 Patent 10,250,250 B2 10 quick or sped-up turn on of the output transistor and, consequently, the bootstrapped switching circuit.” Id. at 16 (citing Ex. 2009 ¶ 31). Petitioner proposes that we construe jump start circuit as, a “circuit that causes the sampling switch to turn on more quickly,” arguing that “[t]he jump start circuit compensates for slow elements in the bootstrapped switching circuit, speeding up the output transistor’s turn on compared to if the jump start circuit were absent.” Reply 2-3 (citing Ex. 1012 ¶ 9). Petitioner offers its construction to clarify Patent Owner’s argument that the claims should be interpreted to require “a quick or sped-up turn on of the output transistor and, consequently, the bootstrapped switching circuit.” Id. at 4 (citing PO Resp. 16). At the outset, it is clear from the ordinary meaning of the claim language, and reading the claims in light of the Specification, that one of ordinary skill in the art would understand within the context of the claims that a jump start circuit would “quickly turn on transistor MP 202 (the output transistor)” in the bootstrap circuit as compared to if the jump start circuit were absent from the bootstrap circuit. Ex. 1001, 5:28-30; see also Apple Inc. v. Koss Corp., IPR2021-00626, Paper 10 at 9 (PTAB Sept. 30, 2021) (“we generally give claim terms their ordinary and customary meaning, as would be understood by a person of ordinary skill in the art at the time of the invention, in light of the language of the claims, the specification, and the prosecution history” (citing Phillips v. AWH Corp., 415 F.3d 1303, 1313-14 (Fed. Cir. 2005) (en banc))). The jump start circuit addresses a problem as shown in the embodiment of Figure 2, that in the circuit “the two transistors MN 216 and MN 212 in the positive feedback loop assisting in the action of bringing node X [closer to VINX], can be slow to turn on.” Id. at 5:3-5, Fig. IPR2020-01210 Patent 10,250,250 B2 11 2. The Specification then explains, relative to bootstrap circuit 300 embodiment in Figure 3, “[t]o address this slowdown of the positive feedback loop, a jump start circuit can be included to quickly turn on transistor MP 202 (the output transistor).” Id. at 5:28-30. Because bootstrap circuits in the embodiments of Figures 2 and 3 are essentially identical except for the addition of jump start circuit 302 and transistor 218 in bootstrap circuit 300, we agree with Petitioner that the function of the jump start circuit includes “compensat[ing] for slow elements in the bootstrapped switching circuit, speeding up the output transistor’s turn on compared to if the jump start circuit were absent.” Reply 2-3 (citing Ex. 1012 ¶ 9). Both parties rely on the same portion of the Specification in column five for support: To address this slowdown of the positive feedback loop, a jump start circuit can be included to quickly turn on transistor MP 202 (the output transistor) at the startup of the positive feedback loop action to allow VINX+ VBOOT to pass through transistor MP 202 towards the gate of transistor MN 108 more quickly, causing VBSTRP to rise more quickly, which in turn can turn on transistors MN 216 and MN 212 faster. The result is a much faster bootstrapped switching circuit. Ex. 1001, 5:28-36. Patent Owner cites to it for support that a jump start circuit speeds up the turn on of output transistor MP 202. PO Resp. 15 (citing Ex. 1001, 5:29-31). Petitioner cites to it for the fact that speeding up output transistor MP 202 invariably leads to “a much faster bootstrapped switching circuit” and hence a faster sampling switch. Reply 3 (citing Ex. 1001, 5:35-36). We determine that both proposed constructions are plausible. IPR2020-01210 Patent 10,250,250 B2 12 Patent Owner’s declarant, Dr. Hanumolu, testifies that a person of ordinary skill in the art “would understand that a ‘jump start circuit’ is a circuit designed to quickly turn on or speed up the turn on of other circuitry, which in the case of the ’250 patent claims is the output transistor outputting the gate voltage to the sampling switch.” Ex. 2009 ¶ 29 (citing Ex. 2007, 2; Ex. 1001, 5:29-31). Petitioner’s declarant, Dr. Holberg, testifies that a person of ordinary skill in the art would understand that a jump start circuit is a “circuit that causes the sampling switch to turn on more quickly.” Ex. 1012 ¶¶ 7-9 (citing Ex. 1001, 5:3-7, 5:28-36). Both declarants agree that the jump start circuit speeds up the turn on of the output transistor, and for support, point to the same portion of the Specification of the ’250 patent describing that the output transistor, the bootstrapped switching circuit, and consequently the sampling switch, would also be faster. Compare Ex. 2009 ¶ 30, with Ex. 1012 ¶ 9. A person of ordinary skill in the art, reading the Specification in context, would understand the written description of a “jump start circuit” as generally consistent with the arguments by both parties and their declarants-that is, the addition of jump start circuit 302 of bootstrap circuit 300 in Figure 3 more quickly turns on output transistor MP 202 enabling a faster reaction of bootstrap circuit 300 in turning on the sampling switch 108. Compare PO Resp. 15-16 (citing Ex. 1001, 5:29-36), with Reply 3 (citing Ex. 1001, 5:28-36). Based on the declarants’ reliance on the same portion of the Specification, and although expressed differently in their testimony, their general agreement as to the function of a “jump start circuit,” we determine that the first sentence of Dr. Hanumolu’s testimony provides the most IPR2020-01210 Patent 10,250,250 B2 13 accurate meaning of “jump start circuit.” Namely, that a person of ordinary skill in the art “would understand that a ‘jump start circuit’ is a circuit designed to quickly turn on or speed up the turn on of other circuitry.” Ex. 2009 ¶ 29. 2. startup Patent Owner argues that “startup” should be construed in accordance with the ’250 patent Specification where it describes as soon as “CLKB goes low at the startup (startup meaning CLKB has just become low, or CLK has just become high).” PO Resp. 19 (citing Ex. 2001, 12-13; Ex. 2009 ¶ 35). Petitioner does not provide a specific construction, but argues that “startup” should be given its plain and ordinary meaning. Reply 4. Petitioner argues that Patent Owner’s construction is flawed because it is based on just one of the multiple disclosed embodiments of the ’250 patent, and that other embodiments discuss different conditions indicating “startup” of the positive feedback loop. Id. at 4-5 (citing Ex. 1001, 6:61-62, 8:21- 40; Ex. 1012 ¶ 12). We do not provide an explicit construction for “startup” because doing so is not necessary for our analysis, nor does our final determination turn on the meaning of this term in this inter partes review. H. Grounds Asserted Petitioner asserts that claims 1-3, 11-18, and 20-22 are unpatentable on the following grounds: IPR2020-01210 Patent 10,250,250 B2 14 Claims Challenged 35 U.S.C. § References 1-3, 11-18, 20-22 102 Kudo2 1-3, 11-18, 20-22 103 Doris3 Petitioner relies on testimony from Dr. Douglas Holberg (Exs. 1002, 1012, “Holberg Decl.”) and Patent Owner relies on the testimony of Dr. Pavan Hanumolu (Exs. 2004, 2009, “Hanumolu Decl”). II. ANALYSIS A. Anticipation by Kudo (Claims 1-3, 11-18, 20-22) 1. Overview of Kudo (Ex. 1004) Kudo describes sampling switches used for analog signal processing that are capable of reducing signal distortion caused by on-resistance. Ex. 1004, 1:14-18. To this end, Kudo describes an embodiment of a sampling switch that has a bootstrap circuit for controlling a gate terminal voltage of a metal-oxide-semiconductor (MOS) transistor and a delay time of the gate terminal voltage relative to the input voltage. E.g., id. at 5:53-57, 5:43- 6:30, Fig. 5. Figure 8 of Kudo is reproduced below. 2 US 7,183,814 B2, issued February 27, 2007. Ex. 1004. 3 US 8,664,979 B2, issued March 4, 2014. Ex. 1005. IPR2020-01210 Patent 10,250,250 B2 15 Figure 8 of Kudo depicts a detailed configuration of a circuit of a sampling switch. Id. at 7:32-34. As shown in Figure 8, the sampling switch comprises MOS transistor 10. Id. at 5:45-46. Kudo describes that an input voltage Vin may be supplied to the source terminal of MOS transistor 10, which may provide an output voltage Vout from its drain terminal. See, e.g., id. at 5:45-49. Kudo describes that MOS transistor 10 is turned off when the value of switching control signal “Not ϕ” is high. Id. at 7:53-55. At this time, transistors 24 and 25 are turned on, node G is grounded, transistors 10 and IPR2020-01210 Patent 10,250,250 B2 16 21 are turned off, and capacitor 12 is charged to supply source voltage Vdd. Id. at 7:63-67. The output of inverter 30 is low, while that of inverter 31 is high, which turns on transistor 22 and grounds node A to voltage Vss. Id. at 7:58-60. The low level output of inverter 30 turns on transistor 29, which makes the potential of node X at voltage Vdd and leaves transistor 23 turned off. Id. at 8:1-4. Transistors 27 and 28 are also turned off because their gate voltages are low. Id. at 8:4-6. Kudo describes that MOS transistor 10 is turned on when Not ϕ is turned low. Id. at 8:7-10. This makes inverter 30 output high, and inverter 31 output low. Id. at 8:10-12. At this time, transistors 22 and 25 are turned off, the gate voltage of transistor 27 is turned to high, thus turning transistor 27 on, and turning node X into conduction with node A. Id. at 8:12-16. The voltage between nodes X and B (the voltage between the gate and source of transistor 23) therefore becomes equal to the supply source voltage when MOS transistor 10 was turned off and capacitor 12 was charged. Id. at 8:17- 21. This turns on transistor 23 and node G into conduction with node B, which also makes transistor 21 turn on as the voltage between its gate and source becomes equal to the charged voltage of capacitance 12 (approximately the same as supply source voltage Vdd). Id. at 8:21-26. The source terminal of MOS transistor 10 therefore is supplied with both input voltage Vin and supply source voltage Vdd (by conduction with node A through transistor 21). Id. at 8:26-29. The potential of node G therefore becomes maintained as the sum of input voltage Vin and supply source voltage Vdd, which turns on MOS transistor 10. Id. at 8:29-32. By arranging and operating the circuit in this manner, Kudo describes that the voltage between the gate and source of MOS transistor 10 will be IPR2020-01210 Patent 10,250,250 B2 17 maintained approximately constant when the transistor is turned on, thereby reducing a dependency of the on-resistance of the sampling switch on input signal voltage Vin. Id. at 8:33-39. Figure 10 of Kudo is a time chart showing an operation of an embodiment and is reproduced below. Ex. 1004, 4:3-4. Figure 10 of Kudo depicts a series of time charts, i.e., a circuit timing diagram, illustrating how the sampling switch of Figure 8 might operate in accordance with the clock over time. Id. at 9:15-16, 9:21-23. IPR2020-01210 Patent 10,250,250 B2 18 2. Claims 1-3, 11-18, 20-22 Petitioner, relying on the testimony of Dr. Douglas Holberg, contends that claims 1-3, 11-18, 20-22 are anticipated by Kudo. Pet. 16-37; Ex. 1002. a. Claim 1 Considering the preamble of claim 1, Petitioner argues that Kudo’s sampling switch discloses a higher speed “bootstrap circuit [(Figure 8)] for controlling a gate terminal voltage of the MOS transistor 10.” Pet. 28 (alteration in original) (quoting Ex. 1004, 5:53-55). The bootstrap circuit speed is increased, Petitioner argues, because Kudo also discloses element 1[d], “a jump start circuit to accelerate the turn on of the bootstrapped switching circuit.” Id. (citing Ex. 1002 ¶¶ 147-151). Petitioner argues that limitation 1[a] is disclosed by Kudo’s “sampling switch compris[ing] a MOS transistor 10 . . . for being applied by an input voltage Vin . . . to the source terminal thereof.” Id. at 29 (quoting Ex. 1004, 5:45-47). With respect to limitation 1[b] Petitioner argues that “Kudo’s Bootstrap Circuit (Figure 8) comprises a loop path (i.e., positive feedback loop) . . . including Boot Capacitance 12 . . . , along with Input Transistor 21 . . . , Output Transistor 23,” and that “Kudo discloses ‘[t]he switching control [(i.e., clock)] signal, Not ϕ, by changing to low . . . turn[s] on the transistor 27.’” Pet. 30-31 (alterations in original) (citing Ex. 1004, Fig. 8, 8:7-16; Ex. 1002 ¶¶ 137, 140). Annotating Kudo’s Figure 8, reproduced below, Petitioner argues that limitation 1[c] is disclosed by “Kudo’s positive feedback loop (pink) (Figure 8 (annotated below)) compris[ing] Output Transistor 23 (blue) . . . . Output IPR2020-01210 Patent 10,250,250 B2 19 Transistor 23 outputs Node G (green), the gate of Sampling Switch 10 (yellow).” Id. at 31. Figure 8 of Kudo, above, as annotated by Petitioner, highlighting output transistor 23 (blue), sampling switch 10 (yellow) and positive feedback loop (pink). Petitioner argues that limitation 1[d], “a jump start circuit to turn on the output transistor,” is disclosed by Kudo’s bootstrap circuit including inverter 30, inverter 31, and transistor 22 which, when gate voltage of transistor 27 is turned high, node X becomes in conduction with node A to “turn on the output transistor [23].” Id. at 34 (citing Ex. 1004, 8:10-16, 8:21-22; Ex. 1002 ¶¶ 147-151). IPR2020-01210 Patent 10,250,250 B2 20 Figure 8 of Kudo, above, as annotated by Petitioner, highlighting inverters 30, 31, and transistor 22 as a “jump start circuit” (orange) for turning on output transistor 23 (blue). Id. at 35. For limitation 1[e], Petitioner argues that Kudo’s transistor 22 turns off, thus “[d]isengaging from the positive feedback loop caus[ing] Kudo’s Jump Start Circuit to cease turning on Output Transistor 23 (blue), between Times T3 - T4.” Id. (citing Ex. 1004 ¶¶ 152-153). Petitioner provides annotated Figure 10, reproduced below, arguing that the jump start circuit operates for “a limited period of time during a startup of the positive feedback loop,” as recited in claim 1. Id. at 37. IPR2020-01210 Patent 10,250,250 B2 21 Kudo’s Figure 10 as annotated by Petitioner, above, illustrates time periods T1 to T4 and operation inverters 30, 31 with respect to clock signal ϕ with those time periods. Id. According to Petitioner’s color coding, when clock signal ϕ goes low starting the positive feedback loop between T2-T3 (blue), inverter 30 goes high, turning on transistor 27 also between T2-T3. Id. at 36 (citing Ex. 1002 ¶¶ 154-156). Then, between T3-T4 (purple), inverter 31’s output goes low turning off transistor 22 and “no longer pulling down (i.e., ceasing to turn on) the gate of Output Transistor 23.” Id. at 37 (citing Ex. 1002 ¶ 156). Petitioner argues that the result of this, after T4, the positive IPR2020-01210 Patent 10,250,250 B2 22 feeback loop alone generates gate voltage G to turn on the sampling switch. Petitioner points to this passage from Kudo explaining: [S]ince the source terminal . . . being supplied with the input voltage . . . and the node A . . . becomes in conduction through the transistor 21, and therefore the potential of the node G . . . becomes maintained at the sum of the input voltage Vin and the supply source voltage Vdd. This of course makes the transistor 10 turned on in the same way as the transistor 21. Id. at 38 (emphasis omitted) (quoting Ex. 1004, 8:26-32; Ex. 1002 ¶¶ 157- 160). Given this disclosure, Petitioner argues “Kudo discloses each and every limitation of claim 1, and thus anticipates it.” Id. at 39. Patent Owner argues that Kudo cannot anticipate the claim because it operates “fundamentally opposite to the claimed ‘jump start circuit,’ and . . . lacks the critical, recited features of the claimed ‘jump start circuit.’” PO Resp. 21. More specifically, Patent Owner argues that Kudo lacks a jump start circuit because it does not (a) “[q]uickly turn on the output transistor to speed up the turn on of the bootstrapped switching circuit;” and does not (b) “[c]ease turning on the output transistor after a limited period of time during a startup of the positive feedback loop.” Id. We address these arguments below. i. Whether Kudo’s jump start circuit quickly turns on the output transistor Consistent with its claim construction, Patent Owner argues that “[t]he challenged claims require a ‘jump start circuit’ that quickly turns on the output transistor.” Id. at 22. Patent Owner relies on the Specification of the ’250 patent which describes the jump start circuit “help[ing] the positive feedback loop move faster during the (short period of) time when transistors MN 216 and MN 212 are slow to turn on.” Ex. 1001, 6:37-41 (emphasis IPR2020-01210 Patent 10,250,250 B2 23 added). The ’250 patent explains that the result of a faster positive feedback loop “is a much faster bootstrapped switching circuit.” Id. at 5:35-36. According to Patent Owner, different from the claimed jump start circuit, Kudo actually “discloses a delayed turn on of its output transistor.” PO Resp. 22 (citing Ex. 2009 ¶ 41). There are two parts to Patent Owner’s initial argument, the first part being whether Kudo discloses a jump start circuit consistent with our claim construction and as would have been understood by one of ordinary skill in that art, and the second part being whether Kudo, in fact, delays turn on of the output transistor. For the reasons discussed below, we determine that Petitioner has shown by a preponderance of the evidence that Kudo does disclose a jump start circuit as properly construed, and does not delay the turn on of the output transistor. Petitioner argues that Kudo’s inverter 30, inverter 31, and transistor 22 which, when gate voltage of transistor 27 is turned high “turn on the output transistor [23],” disclose a jump start circuit, and relies on the testimony of Dr. Holberg in support. Dr. Holberg testifies that “[a] POSITA would have understood Inverter 30, Inverter 31, and Transistor 22 turning on Output Transistor 23 correspond to ‘a jump start circuit to turn on the output transistor.’” Ex. 1002 ¶ 150. In his first declaration, Dr. Holberg did this in the context of the ’250 patent, expressly testifying that “a ‘jump start circuit’ is one that quickly turns on the output transistor at the startup of the positive feedback loop.” Id. ¶ 147 (citing Ex. 1001, 5:28-36). Patent Owner argues that Dr. Holberg failed to do any analysis to show that Kudo’s inverter 30, inverter 31 and transistor 22, would actually make Kudo’s output transistor turn on more quickly. See PO Resp. 25-26 IPR2020-01210 Patent 10,250,250 B2 24 (Patent Owner arguing that “neither Petitioner’s nor Dr. Holberg’s analysis of the claim element actually demonstrates or even address whether Kudo provides a quick turn on or speed up of the output transistor”). This argument, however, takes some liberties with our Institution Decision. In that Decision, we found a reasonable likelihood that Petitioner’s analysis and Dr. Holberg’s testimony established that Kudo discloses a jump start circuit. See Inst. Dec. 25 (“[a]t this stage of the proceeding, and on the current record, we are sufficiently persuaded by Petitioner that Kudo discloses a ‘jump start circuit’”). In light of that determination, Petitioner’s evidence and the Preliminary Response entered by Patent Owner, we specifically identified, and invited the parties to develop the timing issue, and specifically whether or not inverter 30, inverter 31 and transistor 22, would make Kudo’s output transistor turn on more quickly. See id. at 26 (the Board inviting the parties to address “the operation of inverters 30 and 31, transistor 22, and capacitor 13 in the circuit of Kudo (including how those components affect the timing of the turn on of capacitor 23 as compared to, for example, if those components were absent from the circuit in Figure 8)”). As we requested, Dr. Holberg provided in his second declaration a detailed analysis of the circuit of Kudo’s Figure 8, both with, and without the asserted jump start circuit, i.e., inverter 30, inverter 31 and transistor 22. Ex. 1012 ¶¶ 23-30. Dr. Holberg describes that the bootstrap circuit would probably be ineffective if transistor 22 were eliminated. Id. ¶ 25. On the other hand, Dr. Holberg explains that if transistor 22 were reconfigured to turn off before transistor 27 turns on in this circumstance “the capacitance on node A would charge share with the capacitance on node X (which is precharged to VDD) resulting in node A (and node X) being pulled away IPR2020-01210 Patent 10,250,250 B2 25 from VSS.” Id. ¶ 26. The result of eliminating Kudo’s asserted jump start circuit in this way, Dr. Holberg explained, is that “[t]he output transistor 23 would turn on slower because the output transistor’s gate (node X) is pulled to a voltage greater than VSS.” Id. On the other hand, with the asserted jump start circuit engaged, Dr. Holberg explains that by “pulling the output transistor 23’s gate (node X) to VSS, Kudo’s jump start circuit shortens the time window beginning when Not ϕ has just become low (time T2) to when node X goes low (between times T3-T4) to turn on the output transistor 23.” Id. ¶ 27. Dr. Holberg testifies that this “turn[s] on the output transistor more quickly compared to if Kudo’s jump start circuit were absent.” Id. We find Dr. Holberg’s testimony reasonable and persuasive as to the relevant comparison, including his summary of Kudo’s comparative circuit function, that is-“Node X being pulled to VSS creates a larger |VGS|, causing output transistor 23 to turn ‘strongly on.’ Node X being pulled to a voltage greater than zero results in a lower |VGS|, causing the output transistor 23 to turn on more weakly.” Id. ¶ 28. Considering the evidence and arguments of both parties, we credit Dr. Holberg’s testimony that “Kudo’s circuit includes inverter 30, inverter 31, and transistor 22 . . . [t]his circuit is a jump start circuit because it speeds up turn on of the output transistor 23.” Ex. 1012 ¶ 20. We find Dr. Holberg’s analysis of the operation of Kudo’s circuit at Figure 8 with, and without, the jump start circuit persuasive. Dr. Holberg explains persuasively and with significant technical detail that when considering the circuit and timing diagrams of annotated Figure 10, above, “Kudo’s jump start circuit shortens the time window beginning when Not ϕ has just become low (time T2) to when node X goes low (between times T3-T4) to turn on the output IPR2020-01210 Patent 10,250,250 B2 26 transistor 23 - turning on the output transistor more quickly compared to if Kudo’s jump start circuit were absent.” Id. ¶ 27. Therefore, we do not find as Patent Owner argues, that Petitioner or Dr. Holberg have “ignore[d] the ‘jump start’ term.” PO Resp. 23. Dr. Holberg’s testimony and analysis on the operation of Kudo with, and without, the asserted jump start circuit, is mainly unrebutted. Patent Owner does not offer an analysis of Kudo’s bootstrap circuit with, and without, the jump start circuit, or expressly dispute Dr. Holberg’s testimony. See generally PO Resp. 22-42. Patent Owner deflects to a comparison by Dr. Hanumolu of circuit simulations between Kudo and a third reference, Abo (Ex. 1009), an IEEE Journal of Solid-State Circuits paper titled “A 1.5- V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter.” Id. at 27-42. Patent Owner’s main argument is that “Kudo is based on the well- known Abo bootstrap circuit,. . . but is designed to delay operation because doing so would purportedly improve sampling accuracy.” Id. at 27 (citing Ex. 1004, 2:57-63, 3:35-39; Ex. 2009 ¶ 47). In other words, Patent Owner argues that Kudo is simply the Abo circuit, with the addition of a jump start circuit. See id. (Patent Owner arguing “[t]he similarities between Kudo and Abo are self-evident”). And, Patent Owner argues, even with the addition of the jump start circuit Kudo expressly teaches a “delay,” making Kudo’s circuit slower than Abo’s. See id. at 30 (Patent Owner arguing that “Kudo modifies the Abo structure to delay the delivery of the bootstrap control voltage to the gate of the sampling switch”). Patent Owner argues for example that “Kudo’s circuit is based on and has significant correspondence with Abo’s.” Id. at 35. Petitioner and Dr. Holberg, however, point out significant differences, including illustrating the IPR2020-01210 Patent 10,250,250 B2 27 extra circuitry in Abo’s circuit in the annotated comparison of Abo’s Figure 4, and Kudo’s Figure 8 reproduced below. Above is shown Petitioner’s comparison of Abo having extra circuitry shown within the highlighted blue broken-line box, on the left, compared to Kudo’s Figure 8, on the right. Considering this comparison, the Abo circuit is clearly not the same as Kudo, and Patent Owner has not sufficiently explained how it is and why it would function in the same way as Kudo. See PO Resp. 29 (Patent Owner arguing the main difference is that “Kudo modifies the structure of Abo by including a (delay) capacitor 13 to provide a capacitive load on node A”). Considering the evidence from both declarants, we credit Dr. Holberg’s testimony “that Kudo is not simply Abo’s circuit with the addition of its jump start circuit.” Ex. 1012 ¶ 47. Sticking with its comparison of Kudo and Abo, Patent Owner further argues that Kudo “purposefully delays its operations, rather than jump start or accelerate them.” PO Resp. 27. Patent Owner contends that Kudo modifies the structure of Abo by including a (delay) capacitor 13 to provide a capacitive load on node A and thus to IPR2020-01210 Patent 10,250,250 B2 28 delay the delivery of Vin to the bootstrap capacitor, thus delaying the delivery of the bootstrap voltage (Vdd plus Vin) to the gate of the sampling switch 10. Id. at 29. Patent Owner argues that during prosecution “Kudo emphasized its delay feature as its point of novelty over Abo and delay is ultimately why the Kudo patent itself was allowed and issued.” Id. at 31. Dr. Hanumolu testifies that the word “delay,” “appears over three dozen times in Kudo, including the Abstract, Summary, Detailed Description, and all claims.” Ex. 2009 ¶ 52 (citing Ex. 1004, 3:28-39). Dr. Hanumolu testifies further that “Kudo added delay capacitor 13 to inject delay into the Abo circuit to suppress a variation in the on-resistance and thus reduce distortion of the output signal.” Id. ¶ 53 (citing Ex. 1004, 6:16-22). Petitioner disputes this characterization of Kudo, arguing that regardless of any similarity between Kudo and Abo, Kudo’s described “delay” is a propagation voltage input (Vin) delay to the bootstrap circuit that does not have an effect on the output transistor 23 turn on within the bootstrap circuit. Reply 10-11. This is true, Petitioner argues, because Kudo’s input voltage (Vin) delay is based on the “delay time of the output voltage from an input voltage.” Id. at 10-11 (citing Ex. 1004, 3:31-32) (emphasis added). Considering annotated Figure 10, reproduced below, this cannot occur, Petitioner argues, “until input transistor 21 . . . is turned on after time T4 (green, annotated Figure 10 (below)).” Id. at 11 (citing Ex. 1002 ¶ 127; Ex. 1012 ¶ 32). IPR2020-01210 Patent 10,250,250 B2 29 Kudo’s Figure 10, above, is a circuit timing diagram annotated by Petitioner highlighting in green time T4. Dr. Holberg explains that “Kudo’s output transistor 23 turns on between times T3-T4. This occurs before the input transistor 21 turns on (after time T4).” Ex. 1012 ¶ 33 (citing Ex. 1002 ¶¶ 124, 125). Dr. Hanumolu testified similarly during his deposition that “because VGS of transistor 21 is -- is zero, which is less than the threshold voltage, a person of skill in the art would think and understand that transistor 21 is off prior to the time instance marked T4.” Ex. 1014, 72:19-22. Dr. Hanumolu also, somewhat reluctantly, agreed that output transistor 23 turns on prior to T4, between T3-T4. Id. at 73:21-75:11. When asked during his deposition if transistor 23 turned on between T3-T4, Dr. Hanumolu replied IPR2020-01210 Patent 10,250,250 B2 30 “if the magnitude of the threshold voltage of the PMOS transistor is -- is somewhere between Vdd and ground, then, yes, it would start -- it would start turning on somewhere -- somewhere in that time period.” Id. at 75:2-5. Considering the testimony of both declarants, we credit Dr. Holberg’s explanation that [a] “delay” in the delivery of the input voltage (after time T4) is not introduced until after the output transistor 23 has already turned on (between times T3-T4). As a result, Kudo’s “delay” does not slow down the turn on of the output transistor 23, and any improvement in accuracy is not at the expense of the output transistor’s turn on speed. Ex. 1012 ¶ 33. Dr. Holberg also explains, contrary to Patent Owner’s arguments, that “capacitor 13 does not slow down the turn on of the output transistor 23.” Id. ¶ 34 (citing Ex. 2005, 52:6-53:3). Dr. Holberg testifies that “[c]apacitor 13 aids in pulling down node X, thereby turning on output transistor 23. The larger capacitor 13 is, the more quickly it will charge node X.” Id.; see also Ex. 2005, 52:24-53:1 (Dr. Holberg testifying that “the larger C13 is, the more quickly it’s going to charge here until X [is] low.”). We find Dr. Holberg’s testimony consistent, and persuasive, that the “delay” of the delivery of input voltage Vin described by Kudo does not affect the faster turn of output transistor 23 by the jump start circuit. Patent Owner and Dr. Hanumolu also provide simulations, specifically a simulated timing diagram, reproduced below, asserting that Abo’s circuit operates faster than Kudo’s, that for Kudo “at node G when the sampling switch turns on-occur[s] later in time than in the Abo circuit.” PO Resp. 35-37 (citing Ex. 2009 ¶ 61). IPR2020-01210 Patent 10,250,250 B2 31 Patent Owner’s circuit simulation diagram, above, illustrating Abo’s turn on time in dashed lines, as compared to Kudo’s turn on time in solid lines. Id. at 36. Yet, as discussed above, Kudo is not simply Abo’s circuit with a jump start circuit. Patent Owner fails to provide a persuasive explanation or sufficient technical reason for comparing Abo with Kudo, particularly where an analysis of Figure 8 of Kudo with, and without, the asserted jump start circuit is more relevant to the circuit speed inquiry. Id. at 33-35. Indeed, and especially because the circuits are different, Patent Owner has not sufficiently explained why Kudo’s circuit being slower than Abo’s circuit, even if true, has meaningful relevance to the challenged claims as anticipated by Kudo. Given the proper claim construction, namely that a person of ordinary skill in the art would understand “jump start circuit” to be “a circuit designed to quickly turn on or speed up the turn on of other circuitry,” whether or not Kudo’s bootstrap circuit is slower than Abo’s bootstrap circuit, fails to provide persuasive evidence, or perhaps any IPR2020-01210 Patent 10,250,250 B2 32 evidence at all, that Kudo’s jump start circuit would not speed up turn on of output transistor 23 providing faster control of gate terminal voltage of MOS transistor sampling switch 10 as compared to the circumstance if the asserted jump start circuit were absent from Kudo’s bootstrap circuit. Considering the complete record now before us, we are persuaded that Petitioner has shown by a preponderance of the evidence that Kudo discloses a jump start circuit as recited in claim 1. ii. Whether Kudo’s jump start circuit “cease[s] turning on the output transistor after a limited period of time” Petitioner’s position is that Kudo’s jump start circuit includes transistor 22, which turns off, thus “[d]isengaging from the positive feedback loop caus[ing] Kudo’s Jump Start Circuit to cease turning on Output Transistor 23 (blue), between Times T3 - T4.” Pet. 35 (citing Ex. 1004 ¶¶ 152-153). Patent Owner argues to the contrary that Kudo’s circuit, as shown in annotated Figure 8 below, illustrates how Kudo’s inverter 30 (which is a part of the asserted jump start circuit) remains high, and maintains transistor 27 on (receiving clock signal ϕ) for the entire sampling period. PO Resp. 44- 45 (citing Ex. 2005, 56:15-57:2). IPR2020-01210 Patent 10,250,250 B2 33 Kudo’s Figure 8 as annotated by Patent Owner, above, illustrates reliance of transistor 27 on inverter 30. Dr. Hanumolu testifies that “as Kudo confirms, inverter 30’s output remains high for the entire tracking phase (sometimes also referred to as ‘sampling phase’) of Kudo’s circuit, not for a limited period of time during the startup of the positive feedback loop.” Ex. 2009 ¶ 72 (citing Ex. 2005, 56:15-57:2). Dr. Holberg testifies to the contrary that “Kudo discloses its transistor 22, part of its jump start circuit, turning off, causing the jump start circuit to be disengaged from the positive feedback loop at node A.” Ex. 1012 ¶ 49 (citing Ex. 1004, 8:10-13; Ex. 1002 ¶¶ 152, 153). Dr. Holberg does not specifically dispute that inverter 30 continues to pass clock signal ϕ to transistor 27 after transistor 22 is off, but explains that Kudo’s jump start circuit passing the ϕ signal to the positive feedback loop’s additional transistor 27 keeps it on, thereby allowing the positive feedback loop to pass the voltage at node A to the gate of output transistor 23 (node X) . . . . Thus, additional transistor 27 being on -allow[s] the positive feedback loop to continue assisting the output transistor. IPR2020-01210 Patent 10,250,250 B2 34 Id. ¶ 51 (citing Ex. 1004, 8:7-16). The experts do not disagree so much as to the structure and function of Kudo’s circuit, as over the ultimate conclusion of whether Kudo’s asserted jump start circuit, i.e., inverters 30 and 31 and transistor 22, continues pulling down node X and turning on output transistor 23 after transistor 22 is off. We find Dr. Holberg’s testimony the most persuasive. First, Petitioner and Dr. Holberg have been consistent that Kudo’s jump start circuit includes inverter 30, inverter 31 and transistor 22. Ex. 1002 ¶¶ 147- 151; Ex. 1012 ¶ 20. In fact, as Petitioner points out, and as we noted in our Institution Decision, Kudo’s jump start circuit is essentially the same circuit as shown in Figures 4A-B in the ’250 patent illustrating two inverters and transistor MN 404. See Inst. Dec. 25 (Our Institution Decision explaining that there are “similar components in Kudo (inverters 30 and 31 and transistor 22) (Pet. 17-18) that the ’250 patent describes as an exemplary []jump start circuit, namely, two inverters to generate a delayed version of a clock signal CLKBDEL to turn on transistor MN 404 and subsequently turn on output transistor MP 202”). We find less credible Dr. Hanumolu’s assertion that simply because transistor 27 is connected to the output of inverter 30 and continues to receive clock signal ϕ, even when transistor 22 is off, that Kudo’s jump start circuit remains on. It is more persuasive, as Dr. Holberg explains, that “transistor 27 is not part of Kudo’s jump start circuit, but is instead the ‘additional transistor’ that is part of the positive feedback loop.” Ex. 1012 ¶ 50 (citing Ex. 1002 ¶¶ 182-185; Ex. 1001, claim 14). Dr. Holberg is referring here to “additional transistor MN 218” shown in Figure 3 and described and claimed in the ’250 patent. See Ex. 1001, 7:4-6 (the ’250 patent describing “an IPR2020-01210 Patent 10,250,250 B2 35 additional transistor MN 218 (e.g., NMOS transistor), with its gate connected to CLK, its source connected to the drain of input transistor”), see also id. at 25:9-12 (claim 14 reciting “an additional transistor coupled to a gate of the output transistor and a drain of the input transistor, wherein the additional transistor is controlled by the clock signal which activates the positive feedback loop”). Having considered the arguments and evidence from both parties including the testimony of their respective declarants, we determine that Petitioner has shown by a preponderance of the evidence that Kudo’s jump start circuit ceases to turn on, i.e., is no longer pulling down, output transistor 23 when transistor 22 turns off after inverter 31’s output goes low between times T3-T4 as shown, for example, in Petitioner’s annotated Figure 10 from Kudo above. Pet. 36 (citing Ex. 1002 ¶ 156). And, with inverter 31 remaining connected to transistor 27, we also find Dr. Holberg’s testimony persuasive that “passing the ϕ signal to the positive feedback loop’s additional transistor 27 keeps it on, thereby allowing the positive feedback loop to pass the voltage at node A to the gate of output transistor 23 (node X) . . . . Thus, additional transistor 27 being on “allow[s] the positive feedback loop to continue assisting the output transistor.’” Ex. 1012 ¶ 51 (quoting Ex. 1001, 24:9-10) (citation omitted). Having considered the entire record and all the evidence and arguments from both parties, for the reasons explained above we are persuaded that Kudo discloses all the limitations of claim 1. The Petition and supporting testimony of Dr. Holberg has shown by a preponderance of the evidence that claim 1 is anticipated by Kudo. IPR2020-01210 Patent 10,250,250 B2 36 b. Claim 2 Claim 2 depends directly from claim 1, and further recites that “the jump start circuit is coupled to a gate of the output transistor.” Ex. 1001, 24:13-14. Petitioner argues that Kudo’s jump start circuit “is coupled to the gate of Output Transistor 23 (blue) via Node X (purple) and Node A (red),” as shown in Figure 8 of Kudo, as annotated by Petitioner, reproduced below. Pet. 39. Kudo’s Figure 8, above, as annotated by Petitioner to show jump start circuit coupled to gate of output transistor 23. Patent Owner does not argue separately dependent claim 2, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 2, supported by the testimony of Dr. Holberg (Ex. 1002 IPR2020-01210 Patent 10,250,250 B2 37 ¶¶ 161-162), which we credit, is persuasive that Kudo describes the limitations of claim 2. c. Claim 3 Claim 3 depends directly from claim 1, and similar to limitation 1[e] of claim 1, recites “wherein the jump start circuit disengages from the output transistor after the limited period of time.” Ex. 1001, 24:15-17 (emphasis added). Then, claim 3 requires “allow[ing] the positive feedback loop to bring a gate voltage of the output transistor to a voltage level of the voltage input signal.” Id. at 24:17-19. Petitioner argues that “Kudo discloses ‘the potentials of the node-X and -A ascends [sic] from zero volt to Vdd/2.’” Pet. 40 (quoting Ex. 1004, 9:39-40). And, Petitioner points out that Kudo also discloses that “Input Signal ‘Vin is maintained at a half of the supply source voltage Vdd.’” Id. (quoting Ex. 1004, 9:28). Patent Owner does not argue separately dependent claim 3, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 3, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 163-166), which we credit, is persuasive that Kudo describes the limitations of claim 3. d. Claim 11 Claim 11 depends directly from claim 1 and recites “the positive feedback loop comprises a boot capacitor,” and “turn[ing] on the sampling switch by bringing the gate voltage to a boosted voltage generated based on the voltage input signal and a voltage across the boot capacitor.” Ex. 1001, 24:54-59. Petitioner argues that Kudo’s positive feedback loop turns on sampling switch 10 thereby “[m]aintaining the potential of Node G (i.e., gate IPR2020-01210 Patent 10,250,250 B2 38 voltage of the sampling switch) at the sum of Input Voltage Vin (i.e., voltage input signal) and Supply Source Voltage Vdd (i.e., voltage across the boot capacitor).” Pet. 42 (citing Ex. 1004, 8:29-32, Fig. 8; Ex. 1002 ¶¶ 167- 171). Patent Owner does not argue separately dependent claim 11, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 11, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 167-171), which we credit, is persuasive that Kudo describes the limitations of claim 11. e. Claim 12 Claim 12 depends from claim 11 and recites “the input transistor is coupled to a first plate of the boot capacitor; and the output transistor is coupled to a second plate of the boot capacitor.” Ex. 1001, 24:62-65. Petitioner argues that Kudo’s input transistor 21 is connected to one plate of boot capacitor 12, and output transistor 23 is connected to other plate of boot capacitor 12. Pet. 43 (citing Ex. 1004, 6:13-14, 7:48-49, Fig. 8). Patent Owner does not argue separately dependent claim 12, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 12, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 167-171), which we credit, is persuasive that Kudo describes the limitations of claim 12. f. Claim 13 Claim 13 depends directly from claim 1 and requires that 13[a] the input transistor is driven by the gate voltage of the sampling switch; and IPR2020-01210 Patent 10,250,250 B2 39 13[b] the positive feedback loop further comprises a first transistor coupled to a gate of the output transistor and a drain of the input transistor, wherein the first transistor is driven by the gate voltage of the sampling switch. Ex. 1001, 25:1-6. Petitioner argues that Kudo’s sampling switch 10, and input transistor 21 are connected to node G. Pet. 44 (citing Ex. 1004, Fig. 8; Ex. 1002 ¶¶ 175-176). Petitioner argues that Kudo’s transistor 28 in the positive feedback loop is connected to the drain of input transistor 21 and also connected to node G, the gate voltage of sampling switch 10. Pet. 45 (citing Ex. 1004, 8:26-28, Fig. 8; Ex. 1002 ¶¶ 177-181). Patent Owner does not argue separately dependent claim 13, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 13, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 175-181), which we credit, is persuasive that Kudo describes the limitations of claim 13. g. Claim 14 Claim 14 depends from claim 1 further reciting an additional transistor coupled to a gate of the output transistor and a drain of the input transistor, wherein the additional transistor is controlled by the clock signal which activates the positive feedback loop. Ex. 1001, 25:9-12. Petitioner argues that Kudo’s additional transistor 27 is connected between output transistor 23 and input transistor 21. Pet. 46 (citing Ex. 1004, 7:46-48). Petitioner asserts, and as we discussed above, the gate of transistor 27 receives clock signal ϕ from inverter 30’s output which activates the positive feedback loop. Id. at 47 (citing Ex. 1004, 8:27- 28; Ex. 1002 ¶¶ 182-185). IPR2020-01210 Patent 10,250,250 B2 40 Patent Owner does not argue separately dependent claim 14, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 14, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 182-185), which we credit, is persuasive that Kudo describes the limitations of claim 14. h. Claim 15 Independent claim 15 is a method claim reciting limitations similar to claim 1, but mainly in terms of functional language. For example, instead of “[a] bootstrapped switching circuit with accelerated turn on,” as recited in the preamble of claim 1, claim 15 recites “[a] method for accelerated turn on of a sampling switch.” Compare Ex. 1001, 23:61-62, with id. at 25:13-14. Claim 15 requires the step of outputting, by an output transistor of a positive feedback loop, an output voltage of a bootstrapped voltage generator for driving an input transistor of the positive feedback loop as positive feedback and for turning on the sampling switch Id. at 25:15-19. Petitioner argues that the output voltage of Kudo’s bootstrapped voltage generator shown in Figure 8 is the gate voltage of sampling switch 10. Pet. 48 (citing Ex. 1004, Fig. 8; Ex. 1002 ¶¶ 188-190). Claim 15 further requires the step of pulling a gate voltage of the output transistor to an on-voltage level to turn on the output transistor for a period of time after the positive feedback loop is activated; Ex. 1001, 25:20-25. Annotating Kudo’s Figure 10, reproduced below, Petitioner argues that Kudo’s positive feedback loop is activated before clock signal ϕ is low, between T2-T3, and that between T2-T4 where both transistor 22 and additional transistor 27 are on, that is followed by transistor IPR2020-01210 Patent 10,250,250 B2 41 22 being part of Kudo’s Jump Start Circuit, no longer pulling down the gate of output transistor 23. Pet. 49-50 (citing Ex. 1004, Fig. 10; Ex. 1002 ¶¶ 191-195). Kudo’s annotated Figure 10, above, is a circuit timing diagram highlighting times T2-T3 in blue, and T3-T4 in purple. Claim 15 also recites the step of ceasing the pulling of the gate voltage after the period of time, to release the gate voltage back to a voltage being delivered by the input transistor of the positive feedback loop, and to allow the IPR2020-01210 Patent 10,250,250 B2 42 positive feedback loop to continue turning on the sampling switch. Ex. 1001, 25:24-28. Petitioner argues that Kudo discloses transistor 22 that, as part of Kudo’s jump start circuit, turns off, causing the jump start circuit to be disengaged from the positive feedback loop. Pet. 51 (citing Ex. 1004, Fig. 8). Petitioner argues further that when inverter 30’s output is high, the input transistor 21 is supplied with input voltage, Vin, and node A is in conduction through transistor 21. Pet 52 (citing Ex. 1004, 8:26-32). According to Petitioner, as shown in Figure 8 of Kudo, reproduced below, the positive feedback loop turns on the sampling switch “[w]hen both Input Transistor 21 (orange) and Additional Transistor 27 (green) are on, [and] Input Voltage Vin . . . is provided to Node X (purple), the gate terminal of Output Transistor 23 (blue).” Id. at 52 (citing Ex. 1002 ¶¶ 198). IPR2020-01210 Patent 10,250,250 B2 43 Kudo’s Figure 8, above, as annotated by Petitioner to illustrate jump start circuit, highlighted in orange, disengaged from the positive feedback loop and positive feedback loop driving sampling switch 10. Patent Owner does not argue separately independent claim 15, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 15, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 196-200), which we credit, is persuasive that Kudo describes all the limitations of claim 15. i. Claim 16 Claim 16 depends from claim 15 and similar to claim limitation 1[a] requires that “the sampling switch receives a voltage input signal.” Ex. 1001, 25:31. As discussed above, we determined that Kudo discloses “sampling switch comprises a MOS transistor 10 . . . for being applied by an input voltage Vin . . . to the source terminal thereof.” Pet. 29 (quoting Ex. 1004, 5:45-47). Claim 16 also requires the positive feedback loop receives the voltage input signal at the input transistor, and generates a boosted voltage signal based on the voltage input signal as the output voltage of the bootstrapped voltage generator to turn on the sampling switch when the positive feedback loop is engaged. Ex. 1001, 25:32-37. Petitioner argues that, as shown in Kudo’s annotated Figure 10, reproduced below, the “positive feedback loop starts up before Clock Signal Φ (blue) (Figure 10 (annotated below)) is low, between Time T2 - Time T3 (blue).” Pet. 53. IPR2020-01210 Patent 10,250,250 B2 44 Kudo’s annotated Figure 10, above, is a circuit timing diagram highlighting times T2-T3 in blue, and T6. Petitioner argues that Kudo expressly describes that sampling switch 10 turns on when “[t]he potential of node G [(green)] becomes maintained at the sum of the input voltage Vin and the supply source voltage Vdd. This of course makes the transistor 10 turned on.” Id. at 54 (quoting Ex. 1004, 8:29-32) (second alteration in original). Patent Owner does not argue separately claim 16, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 16, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 201-206), which we credit, is persuasive that Kudo discloses the limitations of claim 16. IPR2020-01210 Patent 10,250,250 B2 45 j. Claim 17 Claim 17 depends directly from claim 15 and recites the further steps “wherein: pulling the gate voltage of the output transistor comprises changing the gate voltage from an off-voltage level to an on-voltage level.” Ex. 1001, 25:38-41. Petitioner argues that where the potential of node X is Vdd, the output transistor 23 is turned off. Pet. 55 (citing Ex. 1004, 8:3-4, Fig. 8). Petitioner then relies on Kudo’s written description describing that, “[s]ubsequently, ‘the voltage between nodes X and -B as the voltage between the gate and source of the transistor 23 becomes equal to a supply source voltage . . . thereby turning on the transistor 23.’” Id. (quoting Ex. 1004, 8:17-22). Patent Owner does not argue separately claim 17, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 17, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 207-209), which we credit, is persuasive that Kudo discloses the limitations of claim 17. k. Claim 18 Claim 18 depends directly from claim 15, further requiring after the period of time, allowing the positive feedback loop to bring the gate voltage to a voltage level of a voltage input signal provided to the bootstrapped voltage generator and the sampling switch. Ex. 1001, 26:2-5. Petitioner argues that Kudo’s annotated Figure 8, reproduced below, illustrates Vin (blue) supplied to input transistor 21 (orange) and sampling switch 10 (yellow). IPR2020-01210 Patent 10,250,250 B2 46 Kudo’s Figure 8, above, as annotated by Petitioner to illustrate Vin supplied to input transistor 21 and to sampling switch 10. Patent Owner does not argue separately claim 18, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 18, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 210-212), which we credit, is persuasive that Kudo discloses the limitations of claim 18. l. Claim 20 Independent claim 20 is similar in many respects to claim 1, including many of the same limitations, but reciting certain elements as means-plus- function elements, for example, claim 20 recites a “sampling means,” rather than a “sampling switch” as in claim 1. Ex. 1001, 26:13. IPR2020-01210 Patent 10,250,250 B2 47 Claim 20 recites “sampling means receiving an input signal to be sampled and a control signal which turns the sampling means on and off.” Id. at 26:13-15. Petitioner argues that “Kudo discloses structure (i.e., Sampling Switch 10) that performs the same function as, and is [the] same or equivalent to the corresponding structure (i.e., Sampling Switch MN 108).” Pet. 58 (citing Ex. 1004, Fig. 8). Claim 20 recites “means for generating a boosted voltage based on the input signal.” Ex. 1001, 26:16-17. Petitioner argues that Kudo “discloses structure (i.e., Transistor 24, Boot Capacitance 12, Transistor 22) that performs the same function as, and is the same or equivalent to the corresponding structure (i.e., Charging Transistor MN 210, Boot Capacitor CBOOT, Charging Transistor MN 224)” shown in the ’250 patent. Pet. 59 (citing Ex. 1002 ¶¶ 221-225). Claim 20 also requires an “output transistor for outputting the control signal.” Ex. 1001, 26:18. According to Petitioner, Kudo discloses output transistor 23. Pet. 60 (citing Ex. 1002 ¶¶ 226-227). Clam 20 recites “means for bringing the control signal to the boosted voltage through positive feedback action of the control signal.” Ex. 1001, 26:29-21. Petitioner argues that the claimed “control signal” is similar to “gate voltage” recited in claims 1 and 11, and that the positive feedback loop in Kudo includes “structure (i.e., Boot Capacitance 12, Input Transistor 21, Output Transistor 23, Transistor 27, and Transistor 28) that performs the same function as, and is the same or equivalent to the” claimed “positive feedback action” performed by the “Boot Capacitor CBOOT, Input Transistor MN 212, Output Transistor MP 202, Additional Transistor MN 218, and IPR2020-01210 Patent 10,250,250 B2 48 First Transistor 216)” as described in the ’250 patent. Pet. 60-61 (citing Ex. 1002 ¶¶ 228-233). Claim 20 finally recites means for turning on the output transistor for a limited period of time at a startup of the positive feedback action, and after the limited period of time, letting the positive feedback action bring a gate voltage of the output transistor to a voltage level of the input signal. Ex. 1001, 26:22-26. Petitioner argues that, similar to element 1[c] and claim 3, “Kudo discloses structure (i.e., Inverter 30, Inverter 31, and Transistor 22) that performs the same function as, and is the same or equivalent to the corresponding structure (i.e., Jump Start Circuit 302) of the” ’250 patent. Pet. 62 (citing Ex. 1002 ¶¶ 234-240). Patent Owner does not argue separately independent claim 20, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 20, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 213-240), which we credit, is persuasive that Kudo discloses all the limitations of claim 20. m. Claim 21 Claim 21 depends from claim 20 and recites wherein the means for turning on the output transistor for the limited period of time comprises: means for pulling the gate voltage of the output transistor to a low logic level for a limited period of time to turn on the output transistor. Ex. 1001, 26:27-32. Petitioner argues that Kudo’s jump start circuit “(i.e., Inverter 30, Inverter 31, and Transistor 22) . . . performs the same function as, and is the same or equivalent to the corresponding structure (i.e., Jump IPR2020-01210 Patent 10,250,250 B2 49 Start Circuit 302)” as in the ’250 patent and therefore meets the “means for pulling the gate voltage of the output transistor to a low logic level for a limited period of time” limitation in claim 21. Pet. 63-64. Patent Owner does not argue separately claim 21, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 21, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 241-248), which we credit, is persuasive that Kudo discloses all the limitations of claim 21. n. Claim 22 Claim 22 depends directly from claim 20 and requires wherein the means for turning on the output transistor for the limited period of time comprises: means for ceasing pulling the gate voltage of the output transistor to a low logic level after the limited period of time to let the positive feedback action bring the gate voltage of the output transistor to the voltage level of the input signal. Ex. 1001, 26:33-40. Petitioner argues that for the same reasons as described for independent claims 15 and 20, “Kudo discloses structure (i.e., Inverter 30, Inverter 31, and Transistor 22) that performs the same function as, and is the same or equivalent to the corresponding structure (i.e., Jump Start Circuit 302) of the ‘means for ceasing pulling . . .’ limitation, and thus meets claim 22.” Pet. 65 (citing Ex. 1002 ¶¶ 249-255). Patent Owner does not argue separately claim 22, but instead relies on arguments presented for claim 1, which we find unpersuasive as discussed in our analysis of claim 1 above. Petitioner’s analysis for claim 22, supported by the testimony of Dr. Holberg (Ex. 1002 ¶¶ 241-248), which we credit, is persuasive that Kudo discloses the limitations of claim 22. IPR2020-01210 Patent 10,250,250 B2 50 3. Conclusion as to Anticipation Based on Kudo Based on the complete trial record in the proceeding, for the reasons above we are persuaded that Kudo anticipates claims 1-3, 11-18, and 20- 22. Because we determine that all the challenged claims of the ’250 patent are unpatentable over Kudo, we do not reach Petitioner’s challenge asserting that the same challenged claims would have been obvious based on Doris. III. MOTION TO EXCLUDE EVIDENCE Petitioner filed a Motion to Exclude Evidence seeking to exclude paragraphs 54-64 and Exhibit B of Exhibit 2009. Paper 23. Even without excluding this evidence, we have determined that Petitioner has established, based on a preponderance of the evidence, the unpatentability of claims 1-3, 11-18, and 20-22 of the ’250 patent. Furthermore, Petitioner’s arguments on these items go to the weight to be accorded to the evidence. The Board is capable of determining and assigning the appropriate weight to the evidence. For these reasons, we deny Petitioner’s motion. IV. CONCLUSION Petitioner has proved by a preponderance of the evidence that the challenged claims of the ’250 patent would have been anticipated by Kudo. Claims 35 U.S.C. § Reference(s)/ Basis Claims Shown Unpatentable Claims Not Shown Unpatentable 1-3, 11-18, 20-22 102 Kudo 1-3, 11-18, 20-22 1-3, 11-18, 20-22 103 Doris4 4 This ground was not reached because all challenged claims were determined anticipated by Kudo. IPR2020-01210 Patent 10,250,250 B2 51 Claims 35 U.S.C. § Reference(s)/ Basis Claims Shown Unpatentable Claims Not Shown Unpatentable Overall Outcome 1-3, 11-18, 20-22 V. ORDER For the reasons given, it is ORDERED that, based on a preponderance of the evidence claims 1- 3, 11-18, and 20-22 of the ’250 patent have been shown to be unpatentable; and FURTHER ORDERED that, because this is a Final Written Decision, any party to the proceeding seeking judicial review of this Decision must comply with the notice and service requirements of 37 C.F.R. § 90.2. IPR2020-01210 Patent 10,250,250 B2 52 For PETITIONER: Mehran Arjomand Jean Nguyen Hector G. Gallegos Richard S. J. Hung Alex S. Yap MORRISON & FOERSTER LLP marjomand@mofo.com jnguyen@mofo.com hgallegos@mofo.com rhung@mofo.com ayap@mofo.com For PATENT OWNER: Peter Dichiara Scott Bertulli WILMER CUTLER PICKERING HALE AND DORR, LLP peter.dichiara@wilmerhale.com scott.bertulli@wilmerhale.com Michael Diener Claire Rollor Mihai Murgulescu ANALOG DEVICES, INC. Michael.Diener@analog.com Claire.Rollor@analog.com Mihai.Murgulescu@analog.com