Advanced Micro Devices, Inc. et al.

Patent Trials and Appeals Board

Dec 27, 2021

2020003591 (P.T.A.B. Dec. 27, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/415,823 01/25/2017 Todd Martin AMDATI-160274-
US-UTL2
8657
25310 7590 12/27/2021
Volpe Koenig
DEPT. AMD
30 SOUTH 17TH STREET -18TH FLOOR
PHILADELPHIA, PA 19103
EXAMINER
DEMETER, HILINA K
ART UNIT PAPER NUMBER
2674
NOTIFICATION DATE DELIVERY MODE
12/27/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
eoffice@volpe-koenig.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TODD MARTIN, MANGESH P. NIJASURE,
RANDY W. RAMSEY, MICHAEL MANTOR, and
LAURENT LEFEBVRE
Appeal 2020-003591
Application 15/415,823
Technology Center 2600
Before ELENI MANTIS MERCADER, JUSTIN BUSCH, and
CATHERINE SHIANG, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL

STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–20. We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM IN PART.

1 We use the term Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as Advanced Micro
Devices, Inc. Appeal Br. 3.
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CLAIMED SUBJECT MATTER
Appellant’s invention generally relates “to graphics processing
pipelines, and in particular, to a primitive shader.” Spec. 2. The claimed
subject matter relates to systems and methods in which a first program
performs certain operations (i.e., per-vertex operations, generated culled
primitives, identifying screen subdivisions for those primitives, and
transmitting the culled primitives to screen-space pipelines based on the
identified subdivisions) in a first programmable stage of a graphics
processing pipeline that precedes the screen-space pipeline. Claims 1, 10,
and 18 are independent. Claim 1, reproduced below, is representative of the
claimed subject matter:
1. A method for performing three-dimensional graphics
rendering, the method comprising:
performing per-vertex operations on a set of vertices at a
primitive shader stage of a graphics processing pipeline, with a
primitive shader program executing in parallel processing units;
performing culling operations on a set of primitives
associated with the set of vertices, to generate a set of culled
primitives, the culling operations being performed with the
primitive shader at the primitive shader stage;
identifying one or more screen subdivisions for the set of
culled primitives, with the primitive shader at the primitive
shader stage; and
transmitting the set of culled primitives to a set of screen-
space pipelines based on the identified screen subdivisions of the
set of culled primitives, the transmitting performed with the
primitive shader and via a general purpose local data store
memory,
wherein the primitive shader stage comprises a
programmable stage of the graphics processing pipeline prior to
a screen-space pipeline of the graphics processing pipeline.
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REJECTIONS
Claims 1, 5, 8–10, 14, and 16–18 stand rejected under 35 U.S.C. § 103
as obvious over Rhoades (US 8,704,836 B1; Apr. 22, 2014). Final Act. 3–8.
Claims 2, 3, 11, 12, 19, and 20 stand rejected under 35 U.S.C. § 103
as obvious over Rhoades and Goel (US 2014/0098117 A1; Apr. 10, 2014).
Final Act. 8–11.
Claims 4 and 13 stand rejected under 35 U.S.C. § 103 as obvious over
Rhoades and Engh-Halstvedt (US 2016/0005140 A1; Jan. 7, 2016). Final
Act. 11–12.
Claims 6, 7, and 15 stand rejected under 35 U.S.C. § 103 as obvious
over Rhoades and Danskin (US 7,830,392 B1; Nov. 9, 2010). Final
Act. 13–14.
ANALYSIS
REJECTION OF CLAIMS 1, 5, 8–10, 14, AND 16–18 AS OBVIOUS OVER RHOADES
The Examiner rejects claims 1, 5, 8–10, 14, and 16–18 under
35 U.S.C. § 103 as obvious over Rhoades. Final Act. 3–8. Appellant argues
independent claims 1, 5, 8–10, 14, and 16–18 as a group. See Appeal Br. 15
(arguing that, because the combined teachings of the cited references do not
teach or suggest “every feature of claims 1, 10, or 18,” the rejection of
claims 1, 10, and 18 and every claim dependent therefrom should be
withdrawn). Therefore, we select independent claim 1 as representative of
claims 1, 5, 8–10, 14, and 16–18. See 37 C.F.R. § 41.37(c)(1)(iv).
Arguments Appellant could have made, but chose not to make in the Briefs,
are deemed waived. 37 C.F.R. § 41.37(c)(1)(iv).
Appellant asserts Rhoades does not teach or suggest all of the features
of the independent claims. Appeal Br. 8–15. Appellant contends “[n]o
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combination of the references teaches or suggests a single primitive shader
program or primitive shader stage that performs all of the above tasks”
because Rhoades teaches traditional graphics processing that performs the
recited tasks using “various disparate elements” rather than “a single
primitive shader program executing at a primitive shader stage of a graphics
processing pipeline.” Appeal Br. 9 (emphases added).
More specifically, Appellant argues Rhoades does not disclose that
the same shader program performing the per-vertex operations performs the
other recited functions (i.e., culling, identifying, and transmitting) or that its
viewport scale, cull, and clip unit, which performs culling operations, also
executes shader programs. Appeal Br. 9–10. Appellant furthers asserts
Rhoades teaches that a fixed function hardware, namely work distribution
crossbar interface 330, identifies screen subdivisions and transmits
information from the object-space processing portion of the pipeline to the
screen space processing portion of the pipeline. Appeal Br. 11–12.
Appellant argues this crossbar is different than Rhoades’s shader program,
which performs per-vertex operations, and viewport scale, cull, and clip unit,
which performs culling operations. Appeal Br. 12.
As the Examiner notes, Ans. 4, although Appellant addresses the
various operations separately, Appellant’s arguments do not clearly allege
that Rhoades fails to teach or suggest the particular functions or tasks recited
in the independent claims. Rather, Appellant’s various arguments
considered together merely assert that Rhoades’s shader program, cull and
clip unit, and crossbar do not teach “a single primitive shader program that
executes to perform per-vertex operations, culling operations, identifying
screen subdivision for culled primitives, and transmitting the culled
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primitives to the identified screen-space pipelines,” as required by the
independent claims. Appeal Br. 12.
The Examiner finds Rhoades discloses implementing programmable
processing units (PPUs) and parallel processing memories using
programmable processors. Final Act. 2–3. More specifically, the Examiner
finds Rhoades’s graphics processing pipeline includes PPUs and parallel
processing memories that implement the recited programmable primitive
shader stage. Final Act. 4. The Examiner finds Rhoades discloses that
general processing clusters (GPCs) can be programmed to perform various
tasks or operations, such as those recited in representative claim 1 as being
performed by a primitive shader at a primitive shader stage. Ans. 4–6 (citing
Rhoades 6:20–30, Figs. 2, 4). The Examiner further finds Rhoades’s GPCs
have a similar purpose as the primitive shader stage disclosed in the
Specification. Ans. 4 (citing Spec. ¶ 22).
Appellant asserts Rhoades’s general disclosure of using
programmable processors does not teach the specific features recited in
representative claim 1. Appeal Br. 13. Appellant further argues that,
although Rhoades discloses PPUs that include programmable processors,
that does not mean that a single programmable stage of the processing
pipeline performs all of the recited functions (i.e., per-vertex operations,
culling operations, identifying screen subsections, and transmitting the
culled primitives to the screen-space processing pipelines). Appeal
Br. 12–13. Appellant further argues that each PPU in Rhoades includes
multiple GPCs and each GPC includes “work distribution crossbar interface
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330,” TPCs2, and other elements. Appeal Br. 13. Appellant asserts “[i]t is
the TPCs 310 that actually execute shader programs” and “[t]he other
portions of the GPCs 208, including the work distribution crossbar interface
330 . . . are never described as executing shader programs or instructions.”
Appeal Br. 13–14 (citing Rhoades 7:47–64).
As already noted, Appellant does not argue that Rhoades fails to teach
a graphics processing pipeline performing each of the operations recited in
representative claim 1. Rather, Appellant asserts: Rhoades never states that
the program performing per-vertex operations also performs the culling,
identifying, and transmitting operations; Rhoades’s viewport scale, cull, and
clip unit that performs the culling operations is not “analogous to a primitive
shader executing a primitive shader program”; and Rhoades discloses using
a crossbar to distribute primitives from the object-space processing pipeline
to the screen-space processing pipeline. See Appeal Br. 9–12. We find
these assertions unpersuasive of error because Appellant does not
persuasively explain why the cited disclosures in Rhoades taken together do
not teach or suggests a shader program executing at a shader stage prior to

2 TPC appears to be an acronym in the graphics processing art for a “Texture
Processing Cluster” or a “Texture/Processor Cluster.” Regardless of its
exact meaning, it is clear from the context of Rhoades, that TPCs are
processing units. See, e.g., Rhoades 9:6–8 (“Any number of processing
units, e.g., TPCs 310, setup units 321, rasterizers 322, or preROPs 324 may
be included within a GPC 208.”), 9:58–61 (“The result of the parallel object-
space primitive processing performed by the TPCs 310 is batches of
graphics primitive descriptors . . . .”), 15:9–11 (“For example, one of the
TPCs 310 may be configured to perform the functions of one or more of a
geometry processing unit 425, and a fragment processing unit.”).
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the screen-space pipeline of the graphics processing pipeline that performs
the recited functions as further explained below.
Representative claim 1 recites that each of the operations (i.e., per-
vertex operations, culling, identifying screen subdivisions, and transmitting
culled primitives to screen-space pipelines) are performed with a primitive
shader (program) at the primitive shader stage. However, claim 1’s only
recited requirements regarding the “primitive shader program” are that it
performs the recited operations and executes in parallel processing units.
Appeal Br. 18 (claim 1). Similarly, claim 1 requires only that the “primitive
shader stage of a graphics processing pipeline” is the stage at which the
recited operations are performed and that it “comprises a programmable
stage of the graphics processing pipeline prior to a screen-space pipeline of
the graphics processing pipeline.” Appeal Br. 18 (claim 1).
We first address the stages of the graphics processing pipeline and
whether Rhoades teaches performing the tasks the Examiner finds teach the
recited operations at a primitive shader stage of a graphics processing
pipeline prior to a screen-space pipeline. The Specification discloses that
“[t]he stages represent subdivisions of functionality of the graphics
processing pipeline 134” and that “[e]ach stage is implemented partially or
fully as shader programs executing in the programmable processing units
202, or partially or fully as fixed-function, non-programmable hardware
external to the programmable processing units 202.” Spec. ¶ 23. Figure 4A
“illustrates a modified graphics processing pipeline that allows for more
flexible processing in the world-space pipeline and more flexible
transmission from a world-space pipeline to a screen-space pipeline” in
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accordance with certain embodiments of Appellant’s invention. Spec. ¶ 8.
We reproduce Appellant’s Figure 4A:

Spec., Fig. 4A (depicting details of an exemplary graphics processing
pipeline according to the invention). Of note, depicted primitive shader 404
is the last stage of world-space pipeline 430, and the output from primitive
shader 404 is the input to screen-space pipeline 432.
Rhoades similarly discloses an “object-space processing” pipeline and
a “screen-space processing” pipeline. See, e.g., Rhoades 9:17–10:3
(describing “Distributed Object-Space Processing” operations at a high
level), 10:5–15:2 (describing “Distributed Screen-Space Processing”
operations). Figure 5 depicts method steps in the graphics processing
pipeline for rendering primitives in conjunction with the disclosed PPUs.
Rhoades 17:35–39. We reproduce a portion of Figure 5:

Rhoades, Fig. 5 (excerpt). Notably, the demarcation between the object-
space and screen-space processing is when the processed primitives are
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routed or transmitted via a crossbar to GPCs for screen-space processing.
See, e.g., Rhoades 8:50–55 (“Each TPC 310 outputs a stream of object-space
processed primitive descriptors to the work distribution crossbar interface
330 in order to redistribute the object-space processed primitive descriptors
via the work distribution crossbar fabric 334 to one or more GPCs 208 for
screen-space processing.”), 18:14–17 (“At step 530 each primitive is routed
by the work distribution crossbar interface 330 through the work distribution
crossbar fabric 334 to the GPC(s) 208 that are indicated by the GPC mask
for screen-space processing.”), Fig. 5 (steps 530). Thus, the steps prior to
step 530 are part of the object-space processing pipeline in Rhoades, which
is equivalent to the present invention’s “world-space pipeline.” Spec.
¶¶ 24–28, 32, 41–42.
Appellant agrees that the invention’s world-space pipeline is similar
to Rhoades’s object-space processing. Appeal Br. 12 (“Note, the ‘object
space processing’ of Rhoades is the same as the world-space pipeline
described in the present disclosure”). The Examiner finds various tasks that
Rhoades performs in its object-space processing stage teach the functions
that representative claim 1 recites are performed at a primitive shader stage
“of the graphics processing pipeline [that is] prior to a screen-space pipeline
of the graphics processing pipeline.” See Ans. 4–6. These findings are
consistent with Rhoades’s disclosure that “[t]he object-space primitive
processing comprises geometry processing, including world-to-screen-space
transformation, clipping, culling, and vertex shading operations.” Rhoades
9:55–57 (emphases added). Thus, Rhoades explicitly discloses performing
vertex operations, culling, and world-to-screen-space transformation (i.e.,
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identifying screen subdivisions for the primitives) at an object-space stage
prior to the screen-space stage.
Regarding the transmitting step, Appellant correctly notes that
Rhoades discloses routing or transmitting processed primitives via work
distribution crossbar interface 330 to GPCs for screen-space processing.
See, e.g., Rhoades 8:50–55 (“Each TPC 310 outputs a stream of object-space
processed primitive descriptors to the work distribution crossbar interface
330 in order to redistribute the object-space processed primitive descriptors
via the work distribution crossbar fabric 334 to one or more GPCs 208 for
screen-space processing.”), Fig. 5 (steps 530). However, the screen-space
processing pipeline receives the primitives via work distribution crossbar
interface 330, but it is the TPCs in the object-space processing pipeline that
transmit those primitives.
As discussed above, representative claim 1 requires only that the
primitive shader stage is a stage in the graphics processing pipeline prior to
the screen-space pipeline and is the stage at which the recited operations are
performed. For the reasons discussed above, to the extent Appellant argues
Rhoades does not teach or suggest performing the recited operations in a
graphics processing pipeline stage prior to a screen-space pipeline, we
disagree.
Appellant’s assertion that no “single shader program” in Rhoades
performs all of the recited operations is also unpersuasive. As discussed
above, representative claim 1 defines the recited “primitive shader program”
or “primitive shader” only by the fact that it is the process or program
executing in parallel processing unites that performs the recited operations at
the primitive shader stage. See Appeal Br. 18 (claim 1). For the reasons
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discussed above, we agree with the Examiner that the tasks cited as teaching
the recited operations are performed at the primitive shader stage.
We also agree with the Examiner that the cited tasks in Rhoades are
executed in PPUs (parallel processing units) and that the PPUs include
programmable components such as general processing clusters (GPCs) and
TPCs. Final Act. 4 (citing Rhoades 4:13–17, Fig. 4); see Rhoades 5:8–9
(“Each PPU 202 advantageously implements a highly parallel processing
architecture”), 5:9–11 (“PPU 202(0) includes a processing cluster array 230
that includes a number C of general processing clusters (GPCs)”), 5:17–23
(“For example, in a graphics application, a first set of GPCs 208 may be
allocated to perform tessellation operations . . . and a second set of GPCs
208 may be allocated to perform tessellation shading . . . and to determine
vertex positions and other per-vertex attributes.”). Appellant agrees that
Rhoades’s TPCs execute shader programs but asserts that work distribution
crossbar interface 330, setup unit 321, rasterizer 322, and preROP 324 do
not execute shader programs. Appeal Br. 13–14.
Notably, however, the Examiner does not cite to tasks performed by
these elements of Rhoades’s GPCs as teaching the recited operations.
Rather, Rhoades performs the cited tasks using TPCs. More specifically, as
noted above, the tasks the Examiner cites as teaching the per-vertex
operations, culling operations, identification of screen subdivisions, and
transmitting the primitives to the screen-space pipeline are all performed in
the object-space processing portion of the graphics processing pipeline. See,
e.g., Rhoades 9:55–57. Rhoades further discloses distributing “primitives
for object-space (geometry) processing by the TPCs 310.” Rhoades 7:20–
24; see also Rhoades 7:24–26 (“A pipeline manager 305 within each GPC
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208 distributes the object-space processing tasks to streaming
multiprocessors within each of the TPCs 310.”), 9:35–57 (describing
batching primitives and distributing to TPCs for object-space primitive
processing, which “comprises geometry processing, including world-to-
screen-space transformation, clipping, culling, and vertex shading
operations”). Therefore, Appellant’s assertion that the non-TPC components
do not execute shader programs does not demonstrate error in the
Examiner’s findings that Rhoades’s cited elements that perform vertex and
culling operations, identify screen subdivisions, and transmit primitives to
the screen-space pipeline teach or suggest the recited primitive shader
program.
For these reasons, we find a preponderance of the evidence supports
the Examiner’s finding that Rhoades teaches or suggests the disputed subject
matter recited in representative claim 1. Accordingly, we sustain the
rejection of claim 1 as obvious in view of Rhoades. For the same reasons,
we also sustain the rejection of independent claims 10 and 18 and dependent
claims 5, 8, 9, 14, 16, and 17, none of which Appellant argued separately
with particularity, as obvious in view of Rhoades.
REJECTION OF CLAIMS 2, 3, 11, 12, 19, AND 20
AS OBVIOUS OVER RHOADES AND GOEL
The Examiner rejects claims 2, 3, 11, 12, 19, and 20 as obvious over
Rhoades and Goel. Final Act. 8–11. Appellant does not separately argue
with particularity the patentability of these claims. Regarding these claims,
Appellant raises only the arguments addressed above, which assert Rhoades
fails to teach or suggest the features recited in independent claims 1, 10, and
18. Therefore, for the same reasons as discussed above, we also sustain the
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rejection of claims 2, 3, 11, 12, 19, and 20 under 35 U.S.C. § 103 as obvious
over Rhoades and Goel.
REJECTION OF CLAIMS 4 AND 13 AS OBVIOUS
OVER RHOADES AND ENGH-HALSTVEDT
The Examiner rejects claims 4 and 13 as obvious over Rhoades and
Engh-Halstvedt. Final Act. 11–12. Appellant does not separately argue
with particularity the patentability of these claims. Regarding these claims,
Appellant raises only the arguments addressed above, which assert Rhoades
fails to teach or suggest the features recited in independent claims 1, 10, and
18. Therefore, for the same reasons as discussed above, we also sustain the
rejection of claims 4 and 13 under 35 U.S.C. § 103 as obvious over Rhoades
and Engh-Halstvedt.
REJECTION OF CLAIMS 6, 7, AND 15 AS
OBVIOUS OVER RHOADES AND DANSKIN
The Examiner rejects claims 6, 7, and 15 as obvious over Rhoades and
Danskin. Final Act. 13–14. In addition to raising the arguments addressed
above, which assert Rhoades fails to teach or suggest the features recited in
independent claims 1, 10, and 18, Appellant separately argues the limitations
recited in dependent claims 6 and 15. Appeal Br. 15–16.
Of particular relevance, the Examiner finds Danskin teaches or
suggests transmitting culled primitives to the screen-space pipelines “not via
a fixed function crossbar.” Final Act. 13 (citing Danskin 14:34–56,
17:39–18:3); Ans. 7. The Examiner determines it would have been obvious
to modify Rhoades “to reduce or remove the use of crossbars without
affecting performance” in order to improve “GPU performance, speed and
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cost reduction, given the express suggestion of Danskin.” Final Act. 13–14
(citing Danskin 16:44–50, 17:26–38); Ans. 7.
Appellant argues the cited portions of Danskin teach coupling raster
operation units (ROPs) to pixel shader programs without a crossbar, not
transmitting culled primitives to a set of screen-space pipelines without
using a crossbar, as recited in claims 6 and 15. Appeal Br. 16 (citing
Danskin 14:34–56). Appellant argues that ROPs and pixel shaders are part
of the screen-space pipelines and, therefore, output from pixel shaders do not
transmit anything to a screen-space pipeline. Appeal Br. 16.
We agree with Appellant. Although the Examiner appears to rely on
Danskin merely for a teaching of connecting two stages of a pipeline without
using a crossbar, the claims specifically recites transmitting the culled
primitives to the screen-space pipelines without using the crossbar. Appeal
Br. 19, 22. The Examiner does not respond to Appellant’s assertion that
omitting the crossbar between stages within the screen-space pipeline does
not teach or suggest omitting the crossbar when transmitting from Rhoades’s
object-space pipeline to its screen-space pipeline. Although reasons for
omitting the crossbar in Danskin also may provide a reason a person of
ordinary skill in the art may have wanted to omit a crossbar when
transmitting the culled primitives to the screen-space pipelines, there is no
finding or evidence on this record, and we will not speculate in that regard in
the first instance. For these reasons, we do not sustain the rejection of
claims 6 and 15 under 35 U.S.C. § 103 as obvious over Rhoades and
Danskin. Claim 7 directly depends from, and incorporates the limitations of,
claim 6. Accordingly, we similarly do not sustain the rejection of claim 7 as
obvious over Rhoades and Danskin.
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DECISION SUMMARY
Claims
Rejected
35 U.S.C. § Reference(s) Affirmed Reversed
1, 5, 8–10,
14, 16–18
103 Rhoades 1, 5, 8–10,
14, 16–18

2, 3, 11,
12, 19, 20
103 Rhoades, Goel 2, 3, 11,
12, 19, 20

4, 13 103 Rhoades, Engh-Halstvedt 4, 13
6, 7, 15 103 Rhoades, Danskin 6, 7, 15
Overall
Outcome
1–5, 8–14,
16–20
6, 7, 15
RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended. 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED IN PART