Advanced Micro Devices, Inc.

Patent Trials and Appeals Board

Feb 23, 2022

2021001060 (P.T.A.B. Feb. 23, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 16/127,093 09/10/2018 Adithya Yalavarti 6872-180177 9273 108570 7590 02/23/2022 Park, Vaughan, Fleming & Dowler LLP Anthony Jones 3678 Hastings Ct Lafayette, CA 94549 EXAMINER TSENG, CHENG YUAN ART UNIT PAPER NUMBER 2182 NOTIFICATION DATE DELIVERY MODE 02/23/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): kristin@parklegal.com tony@parklegal.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte ADITHYA YALAVARTI, JOHN KALAMATIANOS, and MATTHEW R. POREMBA ____________ Appeal 2021-001060 Application 16/127,0931 Technology Center 2100 _______________ Before JEAN R. HOMERE, HUNG H. BUI, and CHRISTA P. ZADO, Administrative Patent Judges. BUI, Administrative Patent Judge. DECISION ON APPEAL Appellant seeks our review under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claims 1 and 12. Appeal Br. 13, 16. Claims 2- 11 and 13-22 are conditionally allowed if rewritten in independent form including all limitations of claims 1 and 12 and any intervening claims. Final Act. 3. We have jurisdiction under 35 U.S.C. § 6(b). We affirm.2 1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Advanced Micro Devices, Inc., is identified as the real party in interest. Appeal Br. 1. 2 We refer to Appellant’s Appeal Brief filed September 14, 2020 (“Appeal Br.”); Reply Brief filed November 30, 2020 (“Reply Br.”); Examiner’s Answer mailed October 1, 2020 (“Ans.”); Final Office Action mailed March 31, 2020 (“Final Act.”); and Specification filed September 10, 2018 (“Spec.”). Appeal 2021-001060 Application 16/127,093 2 STATEMENT OF THE CASE Fetch circuitry and branch prediction circuitry are well-known components used in a processor. Spec. [2]-[3]; see also Greenhalgh 1:58- 67. For example, fetch circuitry is typically used to fetch instruction(s) from a cache or memory for execution. Greenhalgh 1:58-62. Branch prediction circuitry is used to predict, for any branch instruction fetched, whether those branch instructions will or will not result in a taken branch when that branch instruction is executed. Greenhalgh 1:62-67. Because “each access of the branch prediction functional block has an associated cost in terms of electrical power consumed,” Appellant’s claimed subject matter seeks “controlling accesses to a branch prediction unit [in a processor, shown in Figure 2] for sequences of fetch groups [in order to avoid needless access of the branch prediction unit].” Spec. ¶ 3; Title. Figure 2, depicting such a processor, is reproduced below: BRANCH PREDICTI ON UNIT 212 SEQUENT IAL PRC>CESSC>R 1 02 TC> MEMC>RV 1 04 Appeal 2021-001060 Application 16/127,093 3 Figure 2 depicts processor 102 as including, among others, (1) branch predict unit 212 to predict a “taken” or “not-taken” resolution of CTIs in fetched groups; and (2) fetch logic 214 to fetch instructions from cache 218, 220 or main memory as a group. Spec. ¶¶ 21, 33-35. According to Appellant, The processor also includes a sequential fetch logic functional block that performs operations for avoiding, when possible, accesses of a branch prediction functional block in the processor for acquiring branch prediction information. In the described embodiments, fetch groups, which are blocks of instructions of a specified size ( e.g., 32 bytes, 64 bytes, etc.), are fetched from a cache memory or main memory as a group and prepared for execution in an instruction execution pipeline in the processor. Spec. ¶ 21. Claims 1 and 12 are independent. Representative claim 1 is reproduced below with disputed limitations emphasized: 1. An electronic device that handles control transfer instructions (CTIs) when executing instructions in program code, the electronic device comprising: a processor that includes: a branch prediction functional block; and a sequential fetch logic functional block; wherein the sequential fetch logic functional block: determines, based on a count of a number of fetch groups that are to be fetched for execution in sequence before a subsequent CTI retires from a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI; and when each of the specified number of fetch groups is fetched and prepared for execution, prevents corresponding accesses of the branch prediction functional block for Appeal 2021-001060 Application 16/127,093 4 acquiring branch prediction information for instructions in that fetch group. Appeal Br. 13 (Claims App.). REJECTION AND REFERENCE Claims 1 and 12 are rejected under 35 U.S.C. § 102(a)(1) as anticipated by Greenhalgh (US 9,477,479 B2; issued Oct. 25, 2016). Final Act. 2-3. ANALYSIS In support of the anticipation rejection, the Examiner finds Greenhalgh discloses each and every element of Appellant’s claims 1 and 12. Final Act. 2-3 (citing Greenhalgh 2:55-3:3, Figs. 1, 2, 3B). Of particular relevance, the Examiner finds Greenhalgh discloses the disputed limitation: when each of the specified number of fetch groups is fetched and prepared for execution, [the sequential fetch logic functional block] prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group. Id. at 3 (citing Greenhalgh 2:55-3:3, Figs. 1, 3B) (emphasis added). Greenhalgh’s Figure 1, depicting processor 102 provided with several well-known components, including: (1) fetch circuitry 15 and (2) branch prediction circuitry 35, is reproduced below with additional markings for illustration: Appeal 2021-001060 Application 16/127,093 5 Greenhalgh’s Figure 1 depicts processor 102 including: (1) fetch circuitry 15 to fetch instructions from instruction cache 20 or main memory for execution, and (2) branch prediction circuitry 35 to predict, for any branch instruction fetched, whether those branch instructions will or will not result in a taken branch when that branch instruction is executed. Greenhalgh 1:58-67. Appellant contends Greenhalgh does not disclose the disputed limitation of Appellant’s claims 1 and 12: when each of the specified number of fetch groups is fetched and prepared for execution, [the sequential fetch logic functional block] prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group. Appeal Br. 7-11 (citing Greenhalgh 2:55-3:3, Figs. 1, 2, 3B) (emphasis added). According to Appellant, Greenhalgh, however, is limited to describing throttling/halting 70 STAGE IF 1 STAGE IF 2 15 20 25 30 FETCH CIRCUITRY INSTRUCTION FETCH QUEUE (ADDRESS - --- CACHE t--- Gl:NERATION) FETCH COUNT 75 THROTTLE 39 ...__ ......... ,......... DISCARD CONTROL 37 TARGET ADDRESS INDICATION FOR TAKEN BRANCH REQUEST COUNT THROTTLE PREDICTION CIRCUITRY FIG. 1 STAGE IF 3 35 BRANCH PREDICTI ON CIRCUITRY 60 TAKEN BRANCH 46 55 45 EXECUTION CIRCUITRY (DECODE / ISSUE / DATAPATH) 50 Appeal 2021-001060 Application 16/127,093 6 instruction fetching circuitry for a specified time (“two cycles”) after encountering INSTN 4. Greenhalgh does not describe or suggest preventing accesses of a branch prediction functional block for acquiring branch prediction information such as in the independent claims. More specifically, Greenhalgh does not describe or suggest at least “when each of the specified number of fetch groups is fetched and prepared for execution, prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group” such as in independent claim 1, or the language of independent claim 12. Id. at 10 (emphasis added). Appellant’s contentions are not persuasive of reversible Examiner error. Instead, we find the Examiner’s findings, including the Examiner’s responses to Appellant’s contentions, are supported by a preponderance of the evidence on this record. Ans. 5-6. As such, we adopt the Examiner’s findings provided therein. Id. As correctly recognized by the Examiner, Greenhalgh discloses 1) CTI instruction INSTN 4, 2) a first group of fetched instructions INSTN1/INSTN2/INSTBN3 performed under branch taken (hit), and 3) a second group of fetched instructions INSTN5/INSTN6/ . . . performed under the branch-not-taken (discard) as shown in figure 3B. In figure 1, Greenhalgh shows the second group of fetched instructions INSTN5/INSTN6/ . . . are prevented from accessing the branch prediction circuitry 35 with discard control 39, and throttled further second group of instructions with throttle prediction circuitry 55. Those discarded/throttled instructions such as INSTN5/INSTN6/ . . . will not arrive branch prediction circuitry 35 for acquiring branch prediction information after being discarded or throttled acquiring branch prediction information after being discarded or throttled. Ans. 6 (emphasis added). Appeal 2021-001060 Application 16/127,093 7 Greenhalgh’s Figure 3B, depicting how access to branch prediction circuitry can be controlled to reduce power consumption, is reproduced below with additional markings for illustration. Greenhalgh’s Figure 3B depicts a specified number of fetch groups (for example, INSTN1/INSTN2/INSTN3/INSTN4/INSTN5/INSTN6) is fetched, via fetch circuitry 15, shown in Figure 2, and prepared for execution, but certain instructions INSTN5/INSTN6 are discarded or prevented from l INSTN 0 INSTN 1] INSTN 2 x16 INSTN 3 INSTN 4 (Branches back to INSTN 1) INSTN 5 INSTN 6 THROTTLE PREDICTIO TABLE STORES COUNT VALUE OF 4 IN ASSOCIATION WITH ADDRESS OF INSTN 4 INSTN 1 I STN 2 INST 3 INSTN 4 INSTN 5 INSTN 6 Tx+3 Tx+4 IF IF2 IF3 IF3 IF2 IF1 HIT IN THROm predic as ttaken t ~ PRED TION TAB E • 1 - DISCARD ~ WITH COU TVALUE=4 IF1 IF2 IF3 IF1 IF2 IF1 -+mat hon count value causes rottle to be asserted to IF1 or 2 cydes Tx+5 Tx+6 IF3 FIG. 3B -~--- -- -- .... IF2 . . ' IF3 '-, X X ,• ------- --?- ---~" po ver s mptio saved by avo· ng fetching INSTN 5 + I S 6 Appeal 2021-001060 Application 16/127,093 8 moving to branch prediction circuitry 35, shown in Figure 2. Greenhalgh 15:36-16:21. According Greenhalgh,. As indicated by the “X” indications associated with instructions 5 and 6 at times Tx+5 and Tx+6, the power consumption that would otherwise have been incurred by accessing the instruction cache for instructions 5 and 6, only for them to then be discarded, will have been avoided. Greenhalgp 16:14-20. In the Reply, Appellant argues that Greenhalgh’s fetching instructions INSTN5/INSTN6 are throttled and are not fetched by fetch circuitry 15, shown in Figure 2, and, as such, “won’t reach branch prediction circuitry,” whereas Appellant’s claims 1 and 12 “prevent access of the branch prediction functional block for fetch groups that have been fetched and are being prepared for execution rather than simply halting the fetching of instructions” and “actually prevent access of the branch prediction functional block for a fetched instruction group, rather than simply not fetching the instruction group.” Reply Br. 3. We do not agree with Appellant that INSTN5/INSTN6 are not fetched. Contrary to Appellant’s arguments, the instructions (INSTN1/INSTN2/INSTN3/INSTN4/INSTN5/INSTN6), shown in Greenhalgh’s Figure 3B, are part of a fetched group that has already been fetched, via fetch circuitry 15, shown in Figure 2. Greenhalgh 12:39-43 (“Once six instructions have been fetched, it asserts the throttle signal for a predetermined number of cycles to prevent the fetch circuitry from fetching any further instructions whilst the throttle signal is asserted.”). Figures 1 and 3B of Greenhalgh are illustrative. Figure 1 shows three pipeline instruction fetch (IF) stages-IF 1, IF 2, and IF 3, wherein instructions are -- Appeal 2021-001060 Application 16/127,093 9 fetched by Fetch Circuitry 15 during stage IF 1, placed in a fetch queue during stage IF 2, and either discarded or forwarded to Branch prediction circuitry 35 at stage IF 3. Id. at 15:54-57, Fig. 1. Greenhalgh discloses, with reference to Figure 3B, that at time Tx, INSTN5 is at stage IF2 and INSTN6 is at stage IF 3. Id. at 15:46-49, Fig. 3B. In other words, INSTN5 and INSTN6 have already passed pipeline stage IF 1, and therefore have been fetched by Fetch Circuitry 15. Id. Figs. 1, 3B. Greenhalgh discloses that at this time, the count value stored in the throttle prediction table is reached, and that INSTN5/INSTN6 therefore are discarded, before reaching branch prediction circuity 35. Id. at 15:54-57. The Examiner correctly finds, therefore, that Greenhalgh shows INSTN5/INSTN6 “are prevented from accessing branch prediction circuitry 35 with discard control 39,” because the discarded instructions will not arrive at branch prediction circuitry 35 after being discarded. Ans. 6. Greenhalgh further discloses that INSTR5/INSTR6, in a subsequent time in the process, are not fetched due to throttling, which is disclosed, for example at Greenhalgh 16:1-21. Appellant’s arguments do not address the Examiner’s findings regarding the disclosure that instructions 5 and 6 are fetched and discarded, but instead address only the portion of Greenhalgh describing subsequent throttling. See, e.g., Appeal Br. 9 (“Greenhalgh therefore uses counts of instructions associated with branch instructions to throttle fetching circuitry” and “Greenhalgh, however, is limited to describing throttling instruction fetching circuitry”); see also id. at 10 (“Greenhalgh, however, is limited to describing throttling/halting instruction fetching circuitry”); Reply Br. 2-4. Nowhere does Appellant substantively address Greenhalgh’s discard control signals over path 39, which causes Appeal 2021-001060 Application 16/127,093 10 INSTN5/INSTN6 to be discarded. Ans. 6; Greenhalgh 15:44-57. In so doing, Appellant fails to address the entirety of the basis of the Examiner’s rejection, and therefore has not satisfied its burden of demonstrating Examiner error. The disputed limitation of Appellant’s claims 1 and 12 only requires that the fetch logic functional block prevents access to the branch prediction functional block when “each of the specified number of fetch groups is fetched and prepared for execution.” Greenhalgh’s former instance in which the instructions INSTR5/INSTR6 are fetched and discarded in the standard manner falls within the scope of Appellant’s claims 1 and 12. For these reasons, Appellant does not persuade us of reversible Examiner error. Accordingly, we sustain the Examiner’s anticipation rejection of claims 1 and 12. CONCLUSION On this record, Appellant does not show the Examiner erred in rejecting claims 1 and 12 under 35 U.S.C. § 102(a)(1) as anticipated by Greenhalgh. DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 12 102 Greenhalgh 1, 12 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED