ADVANCED MICRO DEVICES, INC.

Patent Trials and Appeals Board

Oct 26, 2020

2019000138 (P.T.A.B. Oct. 26, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/723,103 12/20/2012 Gregory W. Smaus 1458-120152 6232
109712 7590 10/26/2020
Advanced Micro Devices, Inc.
c/o Davidson Sheehan LLP
6836 Austin Center Blvd.
Suite 320
Austin, TX 78731
EXAMINER
SUN, SCOTT C
ART UNIT PAPER NUMBER
2181
NOTIFICATION DATE DELIVERY MODE
10/26/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
AMD@DS-patent.com
docketing@ds-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________
Ex parte GREGORY W. SMAUS, FRANCESCO SPANDINI,
MATTHEW A. RAFACZ, MICHAEL ACHENBACH,
CHRISTOPER J. BURKE, EMIL TALPES, and
MATTHEW M. CRUM
____________________

Appeal 2019-000138
Application 13/723,103
Technology Center 2100
____________________

Before JOHN P. PINKERTON, NABEEL U. KHAN, and JOYCE CRAIG,
Administrative Patent Judges.

PINKERTON, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1–6 and 11–23. Claims 7–10 are withdrawn. We
have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM IN PART.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies Advanced Micro Devices, Inc. as the
real party in interest. Appeal Br. 1.
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STATEMENT OF THE CASE
Introduction
Appellant generally describes the disclosed and claimed invention as
relating to store-to-load forwarding for processors. Spec. ¶ 1.2
Illustrative Claims
Claims 1, 11, and 18 are independent claims. With respect to the
Examiner’s rejections under 35 U.S.C. § 102(b) and § 103(a), Appellant
argues these claims as a group, focusing on claim 1. Appeal Br. 3–5, 7–9.
As further discussed below, we note that claim 18 is not commensurate in
scope with claims 1 and 11 because claim 18 does not recite an arithmetic
unit forwarding data associated with a store instruction to satisfy a load
instruction that is dependent on the data “concurrent with moving the data . .
. to the load/store unit.” We select claim 1 as illustrative of claims 1 and 11,
but not claim 18. See 37 C.F.R. § 41.37(c)(1)(iv). Thus, claim 18 does not
rise or fall with claim 1, and is considered separately infra.
Claims 1 and 18 are reproduced below:
1. A method comprising:
forwarding, at an arithmetic unit of an instruction pipeline,
data associated with a store instruction to satisfy a load
instruction that is dependent on the data concurrent with moving
the data to a load/store unit of the instruction pipeline.
18. A non-transitory computer readable medium storing code
to adapt at least one computer system to perform a portion of a
process to fabricate at least part of a processor comprising:

2 Our Decision refers to the Final Office Action mailed Sept. 21, 2017
(“Final Act.”); Appellant’s Appeal Brief filed Apr. 13, 2018 (“Appeal Br.”)
and the Reply Brief filed Oct. 2, 2018 (“Reply Br.”); the Examiner’s Answer
mailed Aug. 2, 2018 (“Ans.”); and the original Specification filed Dec. 20,
2012 (“Spec.”).
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Application 13/723,103

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a cache; and
an instruction pipeline comprising:
a load/store unit to load and store data from and to
the cache; and
an arithmetic unit to forward data associated with a
store instruction to a load instruction that is dependent on the
data.
Appeal Br. 11, 13 (Claims App.).
Rejections on Appeal
Claims 1–6 and 11–23 stand rejected under 35 U.S.C. § 102(b) as
being anticipated by Col et al. (US 2011/0035570 A1; published Feb. 10,
2011).
Claims 1–6 and 11–23 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Mahalingaiah et al. (US 6,085,302; issued July 4,
2000) (“Mahalingaiah”) in view of Luick (US 2007/0288725 A1; published
Dec. 13, 2007).
ANALYSIS
Rejection of Claims 1–6 and 11–17 Under § 102(b)
The dispositive issue raised by the arguments in Appellant’s briefs is
whether Col discloses forwarding data associated with a store instruction to
satisfy a load instruction that is dependent on the data “concurrent with
moving the data to a load/store unit of the instruction pipeline,” as recited in
claim 1, and as similarly recited in claim 11 (hereinafter, “the disputed
limitation”).
The Examiner rejected claim 1 under 35 U.S.C. § 102(b) as being
anticipated by Col. Final Act. 3 (citing Col, Fig. 1, ¶¶ 26, 72). In the
Answer, the Examiner finds that paragraphs 71 and 72 of Col disclose the
disputed limitation. Ans. 8–9. In particular, the Examiner finds that Col
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discloses “moving” data from an ALU to a load/store unit because Col’s
paragraph 71 discloses the load unit 124 performs the ALU operation and
internally forwards the result to itself. Id. (citing Col, Fig. 1, ¶ 72). The
Examiner also finds that claim 1 does not preclude “that the ALU be located
as part of the load/store unit” or “moving data within the units themselves.”
Id. The Examiner also finds that paragraph 72 of Col discloses the store unit
126 forwards data to the load unit 124 because paragraph 72 discloses
forwarding from the load/store units to any other units, as shown in Figure 1
of Col. Id. at 9 (citing Col, Fig. 1, ¶ 72).
“A claim is anticipated only if each and every element as set forth in
the claim is found, either expressly or inherently described, in a single prior
art reference.” Verdegaal Bros., Inc. v. Union Oil Co., 814 F.2d 628, 631
(Fed. Cir. 1987); see also In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir.
2007). “[A]nticipation by inherent disclosure is appropriate only when the
reference discloses prior art that must necessarily include the unstated
limitation . . . .” Transclean Corp. v. Bridgewood Servs., Inc., 290 F.3d
1364, 1373 (Fed. Cir. 2002). “Inherency, however, may not be established
by probabilities or possibilities. The mere fact that a certain thing may result
from a given set of circumstances is not sufficient.” Cont’l Can Co. USA,
Inc. v. Monsanto Co., 948 F.2d 1264, 1269 (Fed. Cir. 1991) (quoting In re
Oelrich, 666 F.2d 578, 581 (CCPA 1981)).
We are persuaded by Appellant’s arguments that the Examiner has
erred. See Appeal Br. 3–5; Reply Br. 2–3. Appellant argues, and we agree,
that “Col is silent regarding any teachings of concurrently forwarding store
data from the arithmetic unit to both a load-store unit and to satisfy the load
instruction.” Reply Br. 2. Appellant also argues, and we agree, that
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paragraph 71 of Col “only relates to internally forwarding load data back to
the load unit and is wholly unrelated to forwarding of store data.” Id.
Appellant further argues, and we agree, that although paragraph 72 of Col
discloses forwarding store data from the store unit 126 to the load unit 124,
Col does not disclose that the forwarding of store data “is concurrent with
forwarding the store data from a store instruction to satisfy a load
instruction.” Id. at 3. Thus, because the Examiner has failed to demonstrate
that Col discloses the disputed limitation of claim 1, we do not sustain the
Examiner’s rejection of claim 1 under 35 U.S.C. § 102(b). For the same
reasons, we do not sustain the Examiner’s rejection of claim 11, and
dependent claims 2–6 and 12–17, under § 102(b).
Rejection of Claims 18–23 Under § 102(b)
Appellant argues that claim 18 “sets forth subject matter that is similar
to the subject matter set forth in claim 1” and, therefore, claim 18 is not
anticipated for the same reasons discussed in regard to claim 1. Appeal Br.
5; Reply Br. 3. As stated above, claim 18 is not commensurate in scope with
claim 1 because it does not recite forwarding store data to satisfy a
dependent load instruction “concurrent with moving the data to a load/store
unit.” Instead, claim 18 recites a cache and an instruction pipeline
comprising “a load/store unit to load and store data from and to the cache”
and “an arithmetic unit to forward data associated with a store instruction to
a load instruction that is dependent on the data.” Accordingly, Appellant’s
arguments regarding claim 1 are not persuasive regarding claim 18 because
the disputed limitation of claim 1—“concurrent with moving the data to a
load/store unit”—is missing from claim 18. See In re Self, 671 F.2d 1344,
1348 (CCPA 1982) (“[A]ppellant’s arguments fail from the outset because. .
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. they are not based on limitations appearing in the claims.”). In addition,
we also determine that Col discloses “an arithmetic unit to forward data
associated with a store instruction to a load instruction that is dependent on
the data,” as recited in claim 18, because, as Appellant acknowledges, Col
discloses in paragraph 72 “that store data (i.e., alu-result 156 from the
arithmetic/logical unit 162 in the [store]3 unit 126) may be forwarded on the
forwarding bus 148 to one of the execution units 122/124/126 (such as load
unit 124).” Reply Br. 3.
For these reasons, we sustain the Examiner’s rejection of independent
claim 18, and dependent claims 19 and 21–23, under § 102(b).
Appellant argues dependent claim 20, and dependent claims 3 and 13,
separately and as a group. Appeal Br. 5–6. Like claims 3 and 13, claim 20
recites “wherein the arithmetic unit is to forward the data in response to the
data having not been moved from the arithmetic unit to a load/store unit of
the instruction pipeline.” For the reasons argued by Appellant in regard to
claim 3, we agree with Appellant that Col does not disclose the limitation of
claim 20. In that regard, although Col discloses “[t]he alu-result 156 is
provided to a store buffer in the memory subsystem 116, to the ROB 114,
and on a forwarding bus 148 to the execution units 122/124/126,” ALU 162
is still internal to the store unit 126, and any forwarding of that store data
(i.e., alu-result 156), including forwarding back to the same store unit 126,
cannot be interpreted to be “in response to the data having not been moved
from the arithmetic unit” without completely ignoring all limitations of

3 Appellant refers to unit 126 as the “load” unit 126. Reply Br. 3.
However, we believe this was a mistake because Figure 1 depicts ALU 162
in “store unit (STU) 126,” and paragraph 72 of Col refers to “store unit 126
of FIG. 1.” See Col, Fig. 1; ¶ 72.
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claim 20, “as the data is already present” at the store unit 126. Id. at 6
(citing Clo ¶¶ 72–73); see also Reply Br. 3–4. Accordingly, we do not
sustain the Examiner’s rejection of claim 20 under § 102(b).
Rejection of Claims 1–6 and 11–23 Under § 103(a)
The Examiner rejects claims 1–6 and 11–23 for obviousness under
35 U.S.C. § 103(a) in view of the combination of Mahalingaiah and Luick.
Final Act. 5–8. The Examiner acknowledges that Mahalingaiah does not
disclose “forwarding, at the aforementioned arithmetic unit, the
aforementioned data to satisfy the aforementioned load instruction
concurrent with moving the data to the aforementioned load/store unit.” Id.
at 5–6. However, the Examiner finds that “Luick discloses of forwarding
data associated with a store instruction to satisfy a load instruction
concurrent with moving the data ([0075], lines 2–10, forwarding data from a
store instruction to a load instruction according to one embodiment of the
invention.” Id. at 6 (citing Luick, Fig. 5, ¶¶ 75–77). In the Answer, the
Examiner finds:
Mahalingaiah teaches an address data is normally received by the
load/store unit 26 in an instruction pipeline (column 12, lines 17-
19). Luick is further relied upon to teach that the address for a
store instruction may be forwarded to another pipeline for a load
instruction (forwarding path 554, figure 5, paragraph 77, 78).
This is performed concurrent to moving to stage 4 of the
execution. The combination of Mahalingaiah with Luick would
result in adding an address forwarding path in addition to the
normal address movement to the load/store unit. Therefore, both
the moving and forwarding are taught by com[bin]ing the two
prior arts. Lastly, Luick explicitly states the store instruction and
the load instruction use the same address data (paragraph 78),
and therefore the load instruction is dependent.
Ans. 10.
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Appellant argues claims 1, 11, and 18 as a group, focusing on claim 1.
As discussed above, we select claim 1 as representative of claims 1 and 11,
but not claim 18 because claim 18 does not recite an arithmetic unit
forwarding data associated with a store instruction to satisfy a load
instruction that is dependent on the data “concurrent with moving the data
. . . to the load/store unit.” See 37 C.F.R. § 41.37(c)(1)(iv).
We are persuaded by Appellant’s arguments that the Examiner has
erred. Appellant acknowledges that Luick teaches “forwarding data from a
store instruction to a load instruction.” Appeal Br. 8 (citing Luick, Fig. 5,
¶¶ 75–77). Appellant also acknowledges Luick mentions that “the
forwarding paths depicted in FIG. 5 are exemplary forwarding paths . . .
Forwarding paths may be provided for other stages of each execution unit
and also from a given execution unit 3100, 3102 back to the same execution
unit 3100, 3102, respectively.” Id. (citing Luick ¶ 76). However, Appellant
argues, and we agree, “Luick is silent regarding any teaching or suggestion
of forwarding data to a [load-store] unit concurrent with those forwarding
paths.” Id. In regard to the Examiner’s citation of paragraphs 77 and 78 of
Luick in the Answer, Appellant argues, and we agree, that Luick merely
teaches that a source register value for a store instruction may be forwarded
to a target register value for a load instruction, if the effective addresses of
the store instruction and the load instruction match, but “provides no
suggestion that such forwarding operations are performed concurrently with
moving to the fourth stage of the execution units completing execution of
load and store instructions (i.e., stages 508, 528 of the execution units 3100,
3102, respectively). Reply Br. 4 (citing Luick ¶ 78). Accordingly, we agree
with Appellant’s argument that the combination of Mahalingaiah and Luick
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fails to teach or suggest the disputed limitation of claim 1, and therefore, we
do not sustain the rejection of claim 1 under § 103(a). For the same reasons,
we do not sustain the rejection of claim 11, and dependent claims 2–6 and
12–17, under § 103(a).
With respect to independent claim 18, Appellant’s arguments
regarding claim 1 are not persuasive because, as discussed above, claim 18
does not recite forwarding store data to satisfy a dependent load instruction
“concurrent with moving the data to a load/store unit.” See Self, 671 F.2d at
1348. Appellant’s arguments are also not persuasive with respect to claim
18 because we agree with the Examiner’s findings that the combination of
Mahalingaiah and Luick teaches or suggests “an arithmetic unit to forward
data associated with a store instruction to a load instruction that is dependent
on the data,” as recited in claim 18. Ans. 10. In that regard, we agree with
the Examiner’s findings that Luick teaches a source register value for a store
instruction may be forwarded to a target register value for a load instruction,
and that the load instruction is dependent on data associated with the store
instruction if “the effective address of the store instruction matches the
effective address of the load instruction.” Id. (citing Luick ¶ 78).
For these reasons, we sustain the Examiner’s rejection of claim 18,
and dependent claims 19–23, which are not argued separately substantively,
under § 103(a). See Appeal Br. 9.
DECISION
We reverse the Examiner’s rejection of the Examiner’s rejection of
claims 1–6 and 11–17 under 35 U.S.C. § 102(b).
We affirm the Examiner’s rejection of claims 18, 19, and 21–23,
under 35 U.S.C. § 102(b).
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We reverse the Examiner’s rejection of claim 20 under 35 U.S.C.
§ 102(b).
We reverse the Examiner’s rejection of claims 1–17 under 35 U.S.C.
§ 103(a).
We affirm the Examiner’s rejection of claims 18–23 under 35 U.S.C.
§ 103(a).

SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–6, 11–23 102(b) Clo 18, 19, 21–
23
1–6, 11–
17, 20
1–6, 11–23 103(a) Mahalingaiah,
Luick
18–23 11–17
Overall
result
18–23 11–17

No period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R.
§ 41.50(f).
AFFIRMED IN PART