ACQIS LLC

Patent Trials and Appeals Board

Sep 14, 2021

IPR2021-00666 (P.T.A.B. Sep. 14, 2021)

Trials@uspto.gov Paper 8
571-272-7822 Entered: September 14, 2021

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

SAMSUNG ELECTRONICS CO., LTD. and
SAMSUNG ELECTRONICS AMERICA, INC.,
Petitioner,
v.
ACQIS LLC,
Patent Owner.
____________

IPR2021-00666
Patent 9,529,768 B2
____________

Before THU A. DANG, JONI Y. CHANG, and SCOTT A. DANIELS,
Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
35 U.S.C. § 314

IPR2021-00666
Patent 9,529,768 B2

2

I. INTRODUCTION
A. Background
Samsung Electronics Co., Ltd. and Samsung Electronics America,
Inc. (collectively, “Petitioner”) filed a Petition requesting an inter partes
review (“IPR”) of claims 1−40 (“the challenged claims”) of U.S. Patent
No. 9,529,768 B2 (Ex. 1001, “the ’768 patent”). Paper 1 (“Pet.”), 3.
ACQIS LLC (“Patent Owner”) filed a Preliminary Response (Paper 7,
“Prelim. Resp.”).
Institution of an inter partes review may not be authorized “unless . . .
the information presented in the petition . . . and any response . . . shows that
there is a reasonable likelihood that the petitioner would prevail with respect
to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a).
Upon consideration of the Petition and the Preliminary Response, we
are not persuaded Petitioner demonstrated a reasonable likelihood of
prevailing in establishing unpatentability of claims 1−40 of the ’768 patent.
Accordingly, no trial is instituted.
B. Related Matters
The parties indicate that the ’768 patent is involved in Acqis LLC v.
Samsung Electronics Co., Ltd., No. 2:20-cv-00295 (EDTX); Acqis LLC v.
MITAC Holding Corporation, et al., No. 6:20-cv-00962 (WDTX);
Acqis LLC v. Inventec Corporation, No. 6:20-cv-00965 (WDTX); Acqis
LLC v. ASUSTek Computer Inc., No. 6:20-cv-00966 (WDTX); Acqis LLC v.
Lenovo Group Ltd., et al., No. 6:20-cv-00967 (WDTX); and Acqis LLC v.
IPR2021-00666
Patent 9,529,768 B2

3

Wistron Corporation, et al., No. 6:20-cv-00968 (WDTX). Pet. 1;
Paper 5, 1–2.
Petitioner also concurrently challenges claims of the ’768 patent in
IPR2021-00605.
C. The ’768 Patent
The ’768 patent, titled “Computer System Including CPU or
Peripheral Bridge Directly Connected to a Low Voltage Differential Signal
Channel that Communicates Serial Bits of a Peripheral Component
Interconnect Bus Transaction in Opposite Directions,” issued on December
27, 2016, from Application No. 14/209,922, filed on March 13, 2014. Ex.
1001, codes (54), (45), (22).
The ’768 patent generally relates to computer interfaces, and
particularly, to “an interface channel that interfaces two computer interface
buses that operate under protocols that are different from that used by the
interface channel.” Ex. 1001, 3:18−22. An illustration of one embodiment
of the ’768 patent’s computer system is depicted in Figure 6, reproduced
below.
IPR2021-00666
Patent 9,529,768 B2

4

Figure 6 shows a block diagram of a computer system using an
interface. Id. at 15:57−59. As shown in Figure 6, computer system 600
includes attached computer module (ACM) 605 and peripheral console 610.
Id. at 15:59−65. ACM 605 and peripheral console 610 are interfaced
through exchange interface system (XIS) bus 615. Id. at 15:65−67. XIS bus
615, which is also referred to as an interface channel, includes power bus
616, video bus 617 and peripheral bus (XP Bus) 618. Id. at 15:67−16:2.
Peripheral controller interconnect (PCI) “signals are encoded into
control bits and the control bits, rather than the control signals that they
IPR2021-00666
Patent 9,529,768 B2

5

represent, are transmitted on the interface channel.” Id. at 5:49–53. “At the
receiving end, the control bits representing control signals are decoded back
into PCI control signals prior to being transmitted to the intended PCI bus.”
Id. at 5:53–55. “The fact that control bits rather than control signals are
transmitted on the interface channel allows using a smaller number of signal
channels and a correspondingly small number of conductive lines in the
interface channel than would otherwise be possible.” Id. at 5:56–60. “This
relatively small number of signal channels used in the interface channel
allows using low [voltage differential signal] (LVDS) channels for the
interface.” Id. at 5:63–65.
In an embodiment, the XP Bus includes bit lines (“bit lines PCK, PD0
to PD3, and PCN”), which are unidirectional LVDS lines for transmitting
clock signals and bits (id. at 22:43–46), wherein “[a] bit based line (i.e., a bit
line) is a line for transmitting serial bits.” Id. at 25:3–4. Bit based lines
“typically transmit bit packets and use a serial data packet protocol,”
wherein examples of bit lines include “an LVDS line, an IEEE 1394 line,
and a Universal Serial Bus (USB) line.” Id. at 25:4–7.
A. Illustrative Claim
Of the challenged claims, claims 1, 4, 7, 10, 13, 18, 22, 27, 30, 33, 36,
and 39 are independent. Claims 2 and 3 depend from claim 1; claims 5 and
6 depend from claim 4; claims 8 and 9 depend from claim 7; claims 11 and
12 depend from claim 10; claims 14–17 depend from claim 13; claims
19–21 depend from claim 18; claims 23–26 depend from claim 22; claims
IPR2021-00666
Patent 9,529,768 B2

6

28 and 29 depend from claim 27; claims 31 and 32 depend from claim 30;
claims 34 and 35 depend from claim 33; claims 37 and 38 depend from
claim 36; and claim 40 depends from claim 39. Claim 1 is illustrative:
1. A computer, comprising:
an integrated central processing unit, interface controller and Phase-
Locked Loop (PLL) clock circuitry in a single chip;
a Low Voltage Differential Signal (LVDS) channel directly extending
from the interface controller to convey address and data bits of a
Peripheral Component Interconnect (PCI) bus transaction in a serial
form, wherein the first LVDS channel comprises a first unidirectional,
differential signal pair to convey data in a first direction and a second
unidirectional, differential signal pair to convey data in a second,
opposite direction; and
wherein the PLL clock circuitry generates different clock
frequencies, and the interface controller conveys the
PCI bus transaction through the LVDS channel based
on the different clock frequencies.
Ex. 1001, 40:37–53.
B. Prior Art Relied Upon
Petitioner relies upon the references listed below (Pet. 6−7):
Name Reference Date Exhibit No.
Gulick U.S. Patent No. 6,690,676 B1 Feb. 10, 2004 1004
Goodrum U.S. Patent No. 5,822,571 Oct. 13, 1998 1006
IPR2021-00666
Patent 9,529,768 B2

7

Name Reference Date Exhibit No.
McAlear U.S. Patent No. 6,389,029 B1 May 14, 2002 1007
Hart U.S. Patent No. 6,041,372 Mar. 21, 2000 1008
Sauber U.S. Patent No. 6,600,747 B1 Jul. 29, 2003 1009

Petitioner also relies on the testimony of Stephen A. Edwards, Ph.D.
Ex. 1003. Patent Owner relies on, inter alia, the testimony of Marc E.
Levitt, Ph.D. Ex. 2001.
C. Asserted Grounds of Unpatentability
Petitioner asserts the following grounds of unpatentability (Pet. 6–7):
Claims Challenged 35 U.S.C. §1 References
1−9, 13−25, 27−33, 35,
39 103(a) Gulick, Goodrum (“Ground 1”)
34, 36–38, 40 103(a) Gulick, Goodrum, McAlear (“Ground 2”)

1 For purposes of this Decision, we assume the challenged claims have an
effective filing date prior to March 16, 2013, the effective date of the Leahy
Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011)
(“AIA”), and we apply the pre-AIA versions of 35 U.S.C. §§ 102, 103 and
112.
IPR2021-00666
Patent 9,529,768 B2

8

Claims Challenged 35 U.S.C. §1 References
10–12 103(a) Hart, Goodrum, McAlear (“Ground 3”)
26 103(a) Gulick, Goodrum, Sauber (“Ground 4”)
II. ANALYSIS
A. Claim Construction
We construe each claim “in accordance with the ordinary and
customary meaning of such claim as understood by one of ordinary skill in
the art and the prosecution history pertaining to the patent.” 37 C.F.R.
§ 42.100(b) (2020). Under this standard, claim terms are generally given
their plain and ordinary meaning as would have been understood by a person
of ordinary skill in the art (POSITA) at the time of the invention and in the
context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d
1303, 1313 (Fed. Cir. 2005) (en banc).
Only those terms in controversy need to be construed, and only to the
extent necessary to resolve the controversy. See Nidec Motor Corp. v.
Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017)
(quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
(Fed. Cir. 1999)).
Petitioner proposes constructions for “peripheral bridge.” Pet. 11–14.
Patent Owner proposes constructions for “terms reciting ‘serial’ data
transmission.” Prelim. Resp. 17–18. For purposes of this Decision, we find
it necessary to address only the claim terms identified below.
IPR2021-00666
Patent 9,529,768 B2

9

1. “serial form,” “serial bit stream,” “serially,” or “using a Universal
Serial Bus (USB) protocol” (all independent claims)
Independent claims 1, 4, 7, 10, 13, 18, 30, and 39 each require an
LVDS channel to convey “address and data bits of a [PCI] bus transaction
in a serial form” or “in a serial bit stream” or a similar limitation. See, e.g.,
Ex. 1001, 40:41−44, 42:12−15 (emphasis added). Independent claims 22,
27, and 30 require a connector adapted to convey “a serial bit stream of
encoded address and data bits of a PCI bus transaction” in, from, or through
an LVDS channel. See, e.g., id. at 43:19–24 (emphasis added). Independent
claim 33 requires an “LVDS channel comprising two sets of unidirectional,
differential signals pairs transmitting data serially.” See id. at 44:43–47
(emphasis added). Independent claim 36 requires an LVDS channel
comprising a “unidirectional, differential signal pair to convey data . . . using
a Universal Serial Bus (USB) protocol.” See id. at 44:63–45:2 (emphasis
added).
Petitioner does not propose express constructions for terms reciting
“serial” transmission or transmitting “serially.” See generally Pet.
However, Patent Owner proposes that “terms reciting ‘serial’ data
transmission have an ordinary meaning,” wherein “[i]n data transmission,
‘serial’ means ‘one bit at a time on a single path.’” Prelim. Resp. 17–18
(quoting Ex. 2002, 11 (IEEE Dictionary) (defining “serial transmission”);
citing Ex. 1001, 25:3−7 (“describing ‘bit based line’ ‘for transmitting serial
bits’”); Ex. 2001 ¶ 76). Based on the evidence before us, we agree with

IPR2021-00666
Patent 9,529,768 B2

10

Patent Owner’s proposed claim construction. Ex. 1001, 25:3−7; Ex. 2001
¶ 76; Ex. 2002, 9, 11.
In particular, Patent Owner’s proposed claim interpretation is
consistent with the term’s “ordinary and customary meaning.” Phillips, 415
F.3d at 1312−13. As Dr. Levitt, testifies, the IEEE Dictionary similarly
defines “serialization” as “the process of transmitting coded characters one
bit at a time,” and defines “serial interface” as “[a]n interface that transmits
data bit by bit rather than in whole bytes.” Ex. 2001 ¶ 76 (citing Ex. 2002,
11) (alteration in original). Dr. Levitt further testifies that the IEEE
Dictionary indicates that “serial” means the opposite of “parallel”
transmission, which “transmits multiple bits simultaneously.” Id. (citing Ex.
2002, 9 (“defining ‘parallel transmission’ as ‘simultaneous transmission of
all the bits making up a character or byte where each bit travels on a
different path’ and contrasting to ‘serial transmission’”), 11 (“defining
‘serial transmission’ and contrasting to ‘parallel transmission’”)).
Further, Patent Owner’s proposed claim construction is also consistent
with the Specification. In particular, the Specification discloses that “[a] bit
based line (i.e., a bit line) is a line for transmitting serial bits,” and that “[b]it
based lines typically transmit bit packets and use a serial data packet
protocol.” Ex. 1001, 25:3−5. The Specification also discloses that
“[e]xamples of bit lines include an LVDS line, an IEEE 1394 line, and a
Universal Serial Bus (USB) line.” Id. at 25:5−7.
In view of the foregoing, for purposes of this Decision, we adopt
Patent Owner’s proposed claim construction—namely, “[i]n data
IPR2021-00666
Patent 9,529,768 B2

11

transmission, ‘serial’ means ‘one bit at a time on a single path.’” Prelim.
Resp. 17. That is, we adopt Patent Owner’s proposed claim construction of
“serial” transmission or transmitting “serially” to mean the opposite of
“parallel” transmission, which “transmits multiple bits simultaneously.” Id.
at 18; Ex. 2001 ¶ 76; Ex. 2002, 9, 11.
2. “graphics subsystem”
Claims 18 and 22 each require “an integrated central processing unit,
graphics subsystem and interface controller in a single chip.” See, e.g., Ex.
1001, 42:45−46 (emphasis added). Claims 27 and 36 recite “an integrated
central processing unit and graphics subsystem in a single chip.” Id., e.g., at
43:45−46 (emphasis added).
In its Petition, Petitioner does not expressly propose a construction for
the term “graphics subsystem.” See generally Pet. In its Preliminary
Response, Patent Owner points out that “[t]he ’768 patent describes the
‘graphics subsystem’ as having graphics processing functionality, not just a
connection to a separate component for processing graphics.” Prelim. Resp.
28. In particular, the Specification repeatedly describes a “graphics
subsystem” as a processing unit having a graphics accelerator and graphics
memory. See, e.g., Ex. 1001, 11:43−45 (disclosing that “the ACM includes
north bridge 215, graphics subsystem 223 (e.g., graphics accelerator,
graphics memory)”), 38:10−13 (“The graphics subsystem can include a
graphics accelerator, graphics memory, and other devices.”).
In light of the Specification and the evidence before us, we construe
“graphics subsystem” as a processing unit having graphics processing
IPR2021-00666
Patent 9,529,768 B2

12

functionality (e.g., producing graphical video output). See Phillips, 415 F.3d
at 1312−13; cf. In re Smith Int’l, Inc., 871 F.3d 1375, 1382−83 (Fed. Cir.
2017) (“The correct inquiry . . . is an interpretation that corresponds with
what and how the inventor describes his invention in the specification, i.e.,
an interpretation that is consistent with the specification.”).
3. “peripheral bridge”
Claims 4 and 10 each require a “peripheral bridge” that is “directly
coupled to the central processing unit without any intervening [PCI] bus.”
See, e.g., Ex. 1001, 40:64−67.
Petitioner points out that “[t]he ’768 patent identifies only one
component as ‘peripheral bridge’ – component 1846 (labeled ‘south
bridge’).” Pet. 11−12 (citing Ex. 1001, 33:66–34:36; Fig. 21). According to
Petitioner, “[c]onsistent with classification as a ‘south bridge,’ the
‘[p]eripheral bridge 1846 couples PCI peripheral bus 1841 with peripheral
buses of other formats.” Pet. 12 (citing Ex. 1001, 34:2–5). Petitioner
contends that bus connections couple peripheral devices to the peripheral
bridge. Id. at 13 (citing Ex. 1001, 33:65–34:23, Fig. 21).
Petitioner takes the position that “[a] ‘peripheral bridge’ is not a north
bridge,” wherein the ’768 patent “makes a clear distinction” between the
north and south bridges. Pet. 13 (citing Ex. 1001, 27:11–13, 35:58–65, Fig.
8; Ex. 1003 ¶¶ 53–54). As Dr. Edward testifies, a person of ordinary skill in
the art would have would have understood that the ’768’s patent’s
“peripheral bridge” is “a component that interfaces with peripheral buses or
IPR2021-00666
Patent 9,529,768 B2

13

peripheral devices,” wherein “‘peripheral bridge’ is not a north bridge.” Ex.
1003 ¶ 53.
We credit Dr. Edward’s testimony that a “peripheral bridge” is not a
north bridge, as it is consistent with the Specification and the general
knowledge of an ordinarily skilled artisan. See, e.g., Ex. 1001, 16:22−36,
Figs. 8 (showing “North Bridge” as a component that links the “CPU” to
“Main Memory” and “Graphic Subsystem,” and “S[outh] Bridge” as a
component that connects to “PCI” and “Other” buses), 8A–8C.
Figure 21 of the ’768 is reproduced below:

Figure 21 of the ’768 patent shows a peripheral console (PCON). Ex.
1001, 32:8–9. As shown in Figure 21, interface and support component
IPR2021-00666
Patent 9,529,768 B2

14

1840 of PCON functional circuitry 1801 comprises peripheral bridge 1846
(shown as “South Bridge”) that couples PCI peripheral bus 1841 with
peripheral busses of other formats such as peripheral busses 1845, 1847. Id.
at 33:65–34:5.
Figure 8 of the ’768 is reproduced below:

Figure 8 of the ’768 patent shows a computer system that includes
North Bridge 805 being connected to a peripheral system that includes South
Bridge 810. Ex. 1001, 8:19–21. As shown, North Bridge 805 is separate
and distinct from South Bridge 810, wherein North Bridge 805 links the
“CPU” to “Main Memory” and “Graphic Subsystem,” while South Bridge
connects to “PCI” and “Other” busses.
IPR2021-00666
Patent 9,529,768 B2

15

In light of the Specification and the evidence before us, for purposes
of this Decision, we construe, “peripheral bridge” as a bridge in a peripheral
system that connects to PCI and other busses, and is not a “north bridge” in a
computer system that links a CPU to main memory and/or a graphic
subsystem. See Phillips, 415 F.3d at 1312−13.
B. Principles of Law
“In an [inter partes review], the petitioner has the burden from the
onset to show with particularity why the patent it challenges is
unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
petitions to identify “with particularity . . . the evidence that supports the
grounds for the challenge to each claim”)); see also 37 C.F.R. § 42.104(b)
(requiring a petition for inter partes review to identify how the challenged
claim is to be construed and where each element of the claim is found in the
prior art patents or printed publications relied on). Petitioner cannot satisfy
its burden of proving obviousness by employing “mere conclusory
statements.” In re Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed.
Cir. 2016).
A claim is unpatentable under 35 U.S.C. § 103 if the differences
between the claimed subject matter and the prior art are such that the subject
matter, as a whole, would have been obvious at the time the invention was
made to a person having ordinary skill in the art to which the subject matter
pertains. KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 406 (2007). The
question of obviousness is resolved on the basis of underlying factual
IPR2021-00666
Patent 9,529,768 B2

16

determinations including (1) the scope and content of the prior art; (2) any
differences between the claimed subject matter and the prior art; (3) the level
of ordinary skill in the art; and (4) objective evidence of nonobviousness.
Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
C. Level of Skill in the Art
In determining the level of ordinary skill in the art, various factors
may be considered, including the “type of problems encountered in the art;
prior art solutions to those problems; rapidity with which innovations are
made; sophistication of the technology; and educational level of active
workers in the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir.
1995)(quoting Custom Accessories, Inc. v. Jeffrey–Allan Indus., Inc., 807
F.2d 955, 962 (Fed. Cir. 1986)). In that regard, relying on the declaration of
Dr. Edward, Petitioner contends that a person of ordinary skill in the art
(“POSITA”) at the time of the ʼ768 patent’s invention would have had “at
least a Master’s degree in, or a Bachelor’s Degree in electrical engineering,
computer science, or a related subject and three years of experience working
with computer architecture, computer busses, and related technologies.” Pet.
11; Ex. 1003 ¶ 45.
In its Preliminary Response, Patent Owner does not dispute
Petitioner’s proposed the level of ordinary skill in the art. See Prelim. Resp.
5. Based on the current record, for purposes of this Decision, we apply
Petitioner’s proposed level of ordinary skill in the art. We also note that the
prior art of record currently in the instant proceeding is consistent with this
level of ordinary skill in the art. See Okajima v. Bourdeau, 261 F.3d 1350,
IPR2021-00666
Patent 9,529,768 B2

17

1354–55 (Fed. Cir. 2001) (holding that absent evidence to the contrary, “the
prior art itself reflects an appropriate level” of ordinary skill in the art).
D. Obviousness Over Gulick and Goodrum
Petitioner alleges that claims 1−9, 13−25, 27−33, 35, and 39 would
have been obvious over Gulick in view of Goodrum (Pet. 14–70); that
claims 34, 36–38, and 40 would have been obvious over Gulick and
Goodrum, in further view of McAlear (id. at 70–78); and claim 26 would
have been obvious over Gulick and Goodrum in further view of Sauber (id.
at 92–94).
1. Gulick
Gulick, titled “Non-Addressed Packet Structure Connecting Dedicated
End Points on a Multi-Pipe Computer Interconnect Bus,” issued on February
10, 2004, from Application No. 09/330,635, filed on June 11, 1999. Ex.
1004, codes (54), (45), (21), (22). Gulick discloses a computer system
having a high speed communication link having multiple pipes operating on
the communication link. Id. at 1:15–18. In particular, Gulick discloses a
“multi-pipe interconnection bus that includes the ability to send a non-
addressed read or write transaction request over one of the pipes of a multi-
pipe computer interconnect bus.” Id. at code (57).
Figure 3 of Gulick, illustrating a portion of a personal computer
system, is reproduced below (id. at 3:7–9):

IPR2021-00666
Patent 9,529,768 B2

18

Figure 3 of Gulick above shows a portion of a personal computer
system that utilizes a communication link. Id. As shown, link 205
communicates between processor module 301 and interface module 303. Id.
at 5:5−8. In the embodiment shown in Figure 3, link 205 has replaced a PCI
bus as the primary interface and also carries both isochronous and
asynchronous data. Id. at 5:15–20.
Bus 205 provides guaranteed bandwidth and latency to each
isochronous stream such as random access memory digital-to-analog
converter (RAMDAC) data, audio data, and IEEE 1394 isochronous streams
while also attempting to minimize latency to asynchronous accesses such as
central processing unit (CPU) initiated accesses and PCI initiated accesses.
Id. at 5:10−14.
IPR2021-00666
Patent 9,529,768 B2

19

Processor module 301 includes link interface 305 which is coupled to
link interface 307 in interface module 303. Id. at 5:8−10. Processor module
301 provides the major process function in the computer system and
includes system memory controller 309, CPU 311, and graphics interface
306. Id. at 5:21−25. “Interface module 303 provides an interface between
various input/output devices such as video monitors, hard drives, scanners,
printers, network connections, modems, and the processor module.” Id. at
5:25−28.
2. Goodrum
Goodrum, titled “Synchronizing Data Between Devices,” issued on
October 13, 1998, from Application No. 659,142, filed on June 5, 1996. Ex.
1006, codes (54), (45), (21), (22). Goodrum discloses transmission of data
between a first device and a second device connected by the
communications channel in a computer system. Id. at code (57). In
particular, Goodrum relates to data synchronization, wherein data
“transferred over a compute bus is synchronized to a bus clock, which
ensures that devices connected to the bus receive valid data.” Id. at 1:6–9.
Figure 1 of Goodrum is reproduced below.
IPR2021-00666
Patent 9,529,768 B2

20

Figure 1 above shows a block diagram of a computer system. Ex.
1006, 2:21. As shown in Figure 1, computer system 10 includes primary
PCI bus 24 interfaced to local bus 22 through system controller/host bridge
circuit 18 that controls access to system memory 20 coupled to local bus 22
along with CPU 14 and level two (L2) cache 16. Id. at 5:7–11. “PCI-
Extended Industry Standard Architecture (EISA) bridge 15 interfaces PCI
bus 24 to EISA bus 17 coupled to keyboard controller 21 and Read Only
Memory (ROM) 23.” Id. at 5:12−15. “PCI bus 24 is coupled to bridge chip
26a and bridge chip 26b, wherein chip 26 is coupled to bridge chip 48a
through cable 31 and bridge chip 26b is coupled to bridge chip 48b through
cable 28.” Id. at 4:65–5:3.
IPR2021-00666
Patent 9,529,768 B2

21

One type of cable 28 that can be used is a cylindrical 50-pair shielded
cable designed to support the High Performance Parallel Interface (HIPPI)
standard. Id. at 57:22−24. Twenty wire pairs of cable 28 are used for
downstream communication and twenty pairs for are used for upstream
communication. Id. at 58:8−9. For the remaining ten pairs in cable 28, error
detection and correction is not implemented. Id. at 58:10−14.
3. McAlear
McAlear, titled “Local Area Network Incorporating Universal Serial
Bus Protocol,” issued on May 14, 2002, from Application No. 09/188,297,
filed on November 10, 1998. Ex. 1007, codes (54), (45), (21), (22).
McAlear discloses local area networks (LAN) comprising a plurality of
outer hub devices connected to a LAN hub and a plurality of universal serial
bus (USB) devices and/or LAN computers connected to the plurality of outer
hub devices, the out end hubs communicating with the USB devices and
LAN computers using USB protocol. Id. at code (57). In one of the
embodiments, McAlear discloses that “LAN computer 130 can also
communicate with a USB device 100 or 180 by addressing the LAN hub 10
in the IP (or Ethernet) protocol and encapsulating the USB protocol within
the IP (or Ethernet) protocol,” i.e., “[a] plurality of USB packets destined to
the USB device 100 or 180 (“USB device packets”) are sent in a plurality of
IP (or Ethernet) packets.” Id. at 40:35-41.
4. Sauber
Sauber, titled “Video Monitor Mutliplexing Circuit,” issued on July
29, 2003, from Application No. 09/156,085, filed on September 17, 1998.
IPR2021-00666
Patent 9,529,768 B2

22

Ex. 1009, codes (54), (45), (21), (22). Sauber discloses a signal connector
that interfaces a computer system to either an analog cathode ray tube (CRT)
display or a digital flat panel (FPD) display, wherein a multiplexer
multiplexes the analog signal and the digital signal supplied by the computer
system and generates an output signal that is suitable for the CRT display or
the FPD display. Id. at code (57). In particular, Sauber discloses “video
controller 109 transmits analog signals by first converting a digital video
signal through a digital-to-analog converter (DAC).” Id. at 3:24−27. Sauber
further discloses digital to differential circuit 220 that includes “a Low
Voltage Differential Signaling (LVDS) transmitter or another suitable
transmitter, such as a transmitter for Transition Minimized Differential
Signaling (TMDS).” Id. at 4:1−10.
5. Analysis
a. Claims 1−9, 13−25, 27−33, 35, and 39 over Gulick
and Goodrum (Ground 1)
i. An LVDS channel “to convey address and data bits of a [PCI] bus
transaction in a serial form” or “in a serial bit stream” or “serially” (all
independent claims)
As discussed above in our claim construction analysis, independent
claims 1, 4, 7, 10, 13, 18, 30, and 39 each requires an LVDS channel to
convey “address and data bits of a [PCI] bus transaction in a serial form” or
“in a serial bit stream” (Ex. 1001, 40:41−44, 42:12−15); independent claims
22, 27, and 30 each requires a connector adapted to convey “a serial bit
stream of encoded address and data bits of a PCI bus transaction” in, from,
or through an LVDS channel (id. at 43:19–24); and independent claim 33
IPR2021-00666
Patent 9,529,768 B2

23

requires an LVDS channel “transmitting data serially” (id. at 44:43–47). By
virtue of their dependency, dependent claims 2, 3, 5, 6, 8, 9, 14−17, 19–21,
23–25, 28, 29, 31, 32, and 35 also require these respective limitations. As
discussed above in our claim construction analysis, we adopt Patent Owner’s
proposed claim construction—namely, “[i]n data transmission, ‘serial’
means ‘one bit at a time on a single path,’” and “serial” transmission means
the opposite of “parallel” transmission, which “transmits multiple bits
simultaneously.” Prelim. Resp. 17–18; Ex. 2001 ¶ 76; Ex. 2002, 9, 11.
In its Petition, Petitioner contends that Gulick discloses “[l]ink 205
[that] is used by the modules 301, 303 to convey PCI transactions,” but
acknowledges that “Gulick does not disclose the link 205 as comprising an
LVDS channel or differential signal pairs.” Pet. 29. Thus, Petitioner relies
on Goodrum to “explicitly” disclose “using LVDS signaling over the cable,”
and “operating in a serial mode.” Id. at 20 (citing Ex. 1006, 6:25−31,
57:45−49, 106:16−31). According to Petitioner, Goodrum discloses
“conveying PCI transactions using differential signaling over a cable (e.g.,
cable 28) connected between cable interfaces (e.g., interfaces 104, 130) of a
PCI-to-PCI bridge,” and that “[t]wenty wire pairs of the cable 28 are used
for downstream communication and 20 more for upstream communication.”
Id. at 30 (citing Ex. 1006, 4:65−5:6, 5:44−51, 6:25−27, 57:30−49, 58:8−9).
According to Petitioner, a POSITA would have understood that “the two sets
of 20 wire pairs could be used as one or more LVDS channels to transmit
data in opposite directions.” Id. (citing Ex. 1003 ¶ 78).
IPR2021-00666
Patent 9,529,768 B2

24

Petitioner further explains that Goodrum discloses that transactions,
including PCI transactions, are encoded into multiple time-multiplexed
messages, wherein “60 bits are multiplexed onto 20 cable lines and are
transmitted each 10 ns over the cable 28.” Id. at 30 (citing Ex. 1006,
50:33−41, 55:14−16). According to Petitioner, “[t]hese bits include address
bits, data bits, and byte enable information bits of a PCI bus transaction.”
Id. (citing Ex. 1006, 55:25−31, 55:65−56:3, Fig. 15A).
Petitioner asserts that a POSITA would have understood that Gulick’s
link interface 305, link 205, link interface 307 could have been modified “to
incorporate Goodrum’s cable interface, cable and LVDS signaling of PCI
bus transactions to achieve a first, or any numbered (e.g., second, third, etc.),
LVDS channel, comprising a first unidirectional, differential signal pair to
convey data in a first direction and a second unidirectional, differential
signal pair to convey data in a second, opposite direction.” Id. at 31−32
(citing Ex. 1003 ¶¶ 79−80).
In its Preliminary Response, Patent Owner counters that the Petition
does not establish a reasonable likelihood that Gulick or Goodrum disclose
“transmitting any address or data bits (or byte enable information bits) ‘in
‘[a] serial form’ or ‘in a serial bit stream.’” Prelim. Resp. 17−22. Patent
Owner points out that “[t]he Petition does not assert that Gulick discloses
transmitting PCI bits in serial form” (id. at 18 (citing Pet. 27−32)), and
contends that “Goodrum does not describe serial transmission for address
and data bits (or byte enable information bits),” wherein “the Petition does
not provide a basis to conclude that it does.” Id. at 21. In fact, according to
IPR2021-00666
Patent 9,529,768 B2

25

Patent Owner, “the Petition does not address Goodrum’s express disclosure
to the contrary, describing a parallel cable interface and not a serial interface
to transmit such bits.” Id. at 21–22. We agree with Patent Owner.
Although Petitioner cites to portions of Goodrum for teaching “a
serial mode” (Pet. 30 (citing Ex. 1006, 6:25−31, 106:16−31)), these portions
disclose transmitting “interrupts” in a serial mode, not address bits, data bits,
or byte enable information bits of a PCI bus transaction, as required by the
challenged claims at issue. See Ex. 1006, 6:25−31 (describing “a serial
stream” for interrupts), 106:16−31 (describing “serial mode” for “interrupt
request signals” on “interrupt request lines”).
Further, although Petitioner contends that Goodrum discloses PCI
transactions that are conveyed “using differential signaling over a cable
(e.g., cable 28) connected between cable interfaces (e.g., interfaces 104, 130)
of a PCI-to-PCI bridge” (Pet. 30), Goodrum discloses that such differential
signaling transmits signals in parallel over a “cable designed to support the
High Performance Parallel Interface (HIPPI) standard” and “the HIPPI
cable specifications.” See Ex. 1006, 57:22−49, 58:8−14, Fig. 16 (emphasis
added). That is, Goodrum makes clear that cable 28 is a “50 pair HIPPI
cable” (a parallel cable). See Ex. 1006, 57:22−24 (“a cylindrical 50-pair
shielded cable designed to support the High Performance Parallel Interface
(HIPPI) standard”), 58:10 (“the 50-pair HIPPI cable 28”). In other words,
the signals do not include address and data bits of a PCI bus transaction
conveyed “in a serial form” or “in a serial bit stream” or “serially” as
required by the challenged claims at issue. Id.
IPR2021-00666
Patent 9,529,768 B2

26

As Patent Owner explains in its Preliminary Response, and as
Dr. Levitt testifies, “Goodrum describes only one embodiment for
transmitting address and data bits,” wherein “Goodrum’s data transfer are
done as parallel transmissions, sending a 60-bit message over the parallel
cable in three time multiplexed phases of 20 parallel bits each.” Prelim.
Resp. 17−22; Ex. 2001 ¶ 79 (citing Ex. 1006, 52:22−45, 55:14−56:3,
57:22−29, Figs. 14, 15A). In particular, “Goodrum promotes the benefits of
its parallel cable interface over ‘serial methods,’ such as fiber optics . . . to
transmit address and data bits.” Ex. 2001 ¶ 79 (citing Ex. 1006, 57:36−39
(“less expensive than fiber optics for this short distance and less complex to
interface than other serial methods”)). Here, Petitioner’s reason to combine
Goodrum with Gulick (Pet. 20 (citing Ex. 1006, 57:30−44) (“less expensive,
better noise immunity, minimized EM radiation etc.”) relies on those
advantages disclosed in Goodrum that are for transmitting data in parallel
over a HIPPI cable, not for serial transmissions as required by the challenged
claims at issue. See Ex. 1006, 57:30–44.
We credit Dr. Levitt’s testimony because it is consistent with
Goodrum’s disclosure and the general knowledge of an ordinarily skilled
artisan. See, e.g., Ex. 1006, 57:22−49, 55:14−56:3, 58:8−14, Figs. 14, 15A
16; Ex. 2002, 9 (defining “parallel transmission” as “[s]imultaneous
transmission of all the bits making up a character or byte where each bit
travels on a different path” and contrasting to “serial transmission”), 11
(defining “serial transmission” as “one bit at a time on a single path” and
IPR2021-00666
Patent 9,529,768 B2

27

“serial interface” as “[a]n interface that transmits data bit by bit rather than
in whole bytes”).
More significantly, neither Petitioner nor Dr. Edwards explains why
one of ordinary skill in the art would have modified Goodrum’s “true
differential” signaling that transmits data in parallel over a HIPPI cable “to
convey address bits, data bits, and byte enable information bits of a [PCI]
bus transaction in a serial bit stream” or “in serial form” or “serially” as
required by the challenged claims at issue. Pet. 16−21, 27−32; Ex. 1003
¶¶ 75−81.
In light of the foregoing, we determine that Petitioner fails to show
that the combinations based on Gulick and Goodrum disclose the above
mentioned “serial” transmission limitation, as required by independent
claims 1, 4, 7, 10, 13, 18, 22, 27, 30, 33 and 39, and their respective
challenged dependent claims by their dependency.
ii. “integrated central processing unit [and] graphics subsystem . . . in
a single chip” (claims 18, 22, and 27)
As discussed above, claims 18 and 22 also require “an integrated
central processing unit, graphics subsystem and interface controller in a
single chip” (Ex. 1001, 42:45−46); and claim 27 also requires “an integrated
central processing unit and graphics subsystem in a single chip.” Id. at
43:45−46. By virtue of their dependency, dependent claims 19−21, 23–25,
and 28−29 also require this limitation. As discussed above in our claim
construction analysis, we construe “graphics subsystem” as a processing unit
IPR2021-00666
Patent 9,529,768 B2

28

having graphics processing functionality (e.g., producing graphical video
output).
In its Petition, Petitioner relies on Gulick’s “graphics [interface] I/F
306” to teach the claimed “graphics subsystem,” citing Dr. Edwards’
testimony for support. Pet. 53−54 (citing Ex. 1004, 5:4–10, Fig. 3; Ex. 1003
¶ 126), 58 (citing Ex. 1003 ¶ 136), 60 (citing Ex. 1003 ¶ 143). However, as
discussed above in our claim construction analysis, in the context of the ’768
patent, a “graphics subsystem” is a processing unit having graphics
processing functionality (e.g., producing graphical video output), and thus,
not merely a graphics interface. As Dr. Levitt testifies, a person of ordinary
skill in the art would have recognized that a graphics interface is not a
graphic subsystem, because “a ‘graphics interface’ is not a ‘graphics
subsystem,’” but instead “is simply the interface for connecting an external
graphics processor to the processor module,” wherein “[t]he graphics
interface itself provides no actual graphics processing functionality.” Ex.
2001 ¶ 72. We credit Dr. Levitt’s testimony as it is consistent with the
Specification and the general knowledge of an ordinarily skilled artisan.
See, e.g., Ex. 1001, 11:43−46, 38:10−13, Figs. 3, 23.
Furthermore, Gulick discloses that a graphics interface, such as
Advanced Graphics Port (AGP) interface, is separate and distinct from a
video/graphics processing unit. Figure 1 of Gulick is reproduced below
(with high-lightings added by Patent Owner). Prelim. Resp. 31.
IPR2021-00666
Patent 9,529,768 B2

29

Figure 1 of Gulick above shows north bridge 103 with AGP interface
(yellow) separate and distinct from the video/graphics processing unit (blue),
the AGP interface and the video/graphics processing unit being connected
by graphics bus 109 (green). See Ex. 1004, 1:25−30.
We also note that Petitioner’s arguments are conclusory, not
supported by sufficient evidence. In particular, neither Petitioner nor
Dr. Edwards explains sufficiently how Gulick’s “graphics interface 306”
provides any graphics processing functionality of a graphics subsystem. Pet.
53−54, 58, 60; Ex. 1003 ¶¶ 126, 136, 143.
IPR2021-00666
Patent 9,529,768 B2

30

Instead, Dr. Edwards’ testimony merely states “Gulick discloses an
integrated central processing unit (CPU 311), graphics subsystem (I/F 306),
and an interface controller (link interface 305) in a single chip (processor
module 301),” without providing any explanation. Ex. 1003 ¶¶ 126, 136,
143 (citing Ex. 1004, 5:4−10, 5:21−25, Fig. 3). Dr. Edwards’ testimony is
inconsistent with Gulick, conflating a graphics interface with a graphics
subsystem. The portions of Gulick relied upon by Dr. Edwards disclose
“graphics interface 306,” not a graphics subsystem. See Ex. 1004, 5:4−10,
5:21−25, Fig. 3. As Patent Owner points out, the portion of Gulick relied
upon by Petitioner “is simply the interface for connecting an external
graphics processor to the processor module,” wherein “the interface itself
has no graphics processing capability.” Prelim. Resp. 30.
In light of the foregoing, we determine that Petitioner fails to show
that the combination of Gulick and Goodrum teaches or suggests “integrated
central processing unit [and] graphics subsystem . . . in a single chip,” as
required by claims 18, 22, and 27.
iii. “peripheral bridge” that is “directly coupled to the central
processing unit without any intervening [PCI] bus” (claim 4)
Claim 4 requires a “peripheral bridge” that is “directly coupled to the
central processing unit without any intervening [PCI] bus.” See Ex. 1001,
40:64−67. By virtue of their dependency, dependent claims 5 and 6 also
require this limitation.
Although Dr. Edward proposes a construction for “peripheral bridge”
as “a component that interfaces with peripheral buses or peripheral devices,”
IPR2021-00666
Patent 9,529,768 B2

31

wherein “‘peripheral bridge’ is not a north bridge” (Ex. 1003 ¶ 53),
Petitioner does not identify any teaching in Gulick or Goodrum of a
“peripheral bridge.” See generally Pet. 34−39. Specifically, although
Petitioner acknowledges that claim 4 requires an integrated “peripheral
bridge,” along with an “interface controller” and an PLL “clock circuitry”
that are “in a single chip, directly coupled to the central processing unit
without any intervening PCI bus,” Petitioner does not address the
“peripheral bridge” limitation, let alone one that is coupled to a CPU without
any intervening PCI bus. Id.
Instead, Petitioner merely argues that Gulick discloses “an integrated
central processing unit (CPU 311) and interface controller (link interface
305) in a single chip (processor module 301).” Id. at 34 (citing Ex. 1004,
5:4−10 (“integrated circuits 301 and 303”), 5:21–25, Fig. 3; Ex. 1003 ¶ 87).
Petitioner then merely contends that “[a] POSITA would have understood
that Gulick’s clocking circuitry could have been improved by employing the
PLLs disclosed by Goodrum,” wherein “[a] POSITA would have recognized
it would be beneficial to include the PLL clock circuitry in the interface
controller that is integrated with the CPU on the single chip.” Id. at 39
(citing Ex. 1003 ¶¶ 88–93).
Here, neither Petitioner nor Dr. Edwards explains sufficiently how
either Gulick or Goodrum provides any “peripheral bridge” that is “directly
coupled to the central processing unit without any intervening [PCI] bus,” as
required by claim 4. See generally Pet. 34−39; Ex. 1003 ¶¶ 87−93.
IPR2021-00666
Patent 9,529,768 B2

32

In light of the foregoing, we determine that Petitioner fails to show
that the combination of Gulick and Goodrum teaches a “peripheral bridge”
that is “directly coupled to the central processing unit without any
intervening [PCI] bus,” as required by claim 4.
iv. Conclusion on obviousness based on Gulick and Goodrum
For the reasons discussed above, we conclude that Petitioner has not
demonstrated a reasonable likelihood of prevailing in showing that claims
1−9, 13−25, 27−33, 35, and 39 are unpatentable under § 103(a) as obvious
over Gulick and Goodrum.
b. Claims 34, 36–38, and 40 over Gulick and Goodrum,
in further view of McAlear (Ground 2)
Petitioner asserts that claims 34, 36–38, and 40 are unpatentable under
§ 103(a) as obvious over Gulick and Goodrum, in further view of McAlear
(Pet. 70–79). By virtue of their respective dependency on claims 33 and 39,
dependent claims 34 and 40 require the respective limitations of claims 33
and 39 described above. Furthermore, independent claim 36 and claims 37
and 38 depending therefrom similarly require “an integrated central
processing unit and graphics subsystem in a single chip” (Ex. 1001,
44:59−60).
Petitioner does not rely on McAlear to remedy the deficiencies
discussed above with respect to Ground 1, but rather relies upon its
arguments in Ground 1 with respect to Gulick. See Pet. 73 (citing Ex. 1003
¶ 179). We already addressed those arguments, and we find those arguments
unavailing here for the reasons stated above. In particular, we find that
IPR2021-00666
Patent 9,529,768 B2

33

Petitioner fails to show that the combinations based on Gulick and Goodrum
disclose an “integrated central processing unit and graphics subsystem in a
single chip,” as recited in the claims.
On this record, we determine that Petitioner has not demonstrated a
reasonable likelihood of prevailing on its assertion that claims 34, 36–38,
and 40 are unpatentable over Gulick and Goodrum in further view of
McAlear.
c. Claim 26 over Gulick, Goodrum, and Sauber
(Ground 4)
Petitioner asserts that claim 26 is unpatentable under § 103(a) as
obvious over Gulick and Goodrum, in further view of Sauber (Pet. 92–94).
By virtue of its respective dependency on claim 22, dependent claim 22
requires the limitations of claim 22 described above. Further Petitioner does
not rely on Sauber to remedy the deficiencies discussed above with respect
to Gulick and Goodrum. See id. We already addressed those arguments,
and we find those arguments unavailing here for the reasons stated above.
On this record, we determine that Petitioner has not demonstrated a
reasonable likelihood of prevailing on its assertion that claim 26 is
unpatentable over Gulick and Goodrum in further view of Sauber.
E. Obviousness Over Hart, Goodrum and McAlear (Ground 3)
Petitioner alleges that claims 10−12 would have been obvious over
Hart, Goodrum and McAlear (Pet. 79–93).

IPR2021-00666
Patent 9,529,768 B2

34

1. Hart
Hart, titled “Method and Apparatus for Providing a Processor Module
for a Computer System,” issued on March 21, 2000, from Application No.
08/774,515, filed on December 30, 1996. Ex. 1008, codes (54), (45), (21),
(22). Hart discloses a “method and apparatus for converting a signal from a
first voltage level to a second voltage level before providing the signal to a
processor.” Id. at code (57). In particular, Hart discloses processor module
220 that “includes a circuit board containing processor 200, voltage
regulator 201, primary bridge A 203, clock 202, and associated signal lines
and interfaces.” Id. at 3:37−42. Figure 2 of Hart is reproduced below.

IPR2021-00666
Patent 9,529,768 B2

35

Figure 2 above shows a block diagram of a computer system. Id. at
2:48–49. As shown, processor 200 is coupled to primary bridge 203 by way
of host bus 208. Id. at 3:49−50. Primary bridge 203 is also coupled to two
other buses, PCI bus 206 and memory bus 209. Id. at 3:53−58.
2. Analysis
Claim 10 requires a “peripheral bridge directly coupled to the [CPU]
without any intervening [PCI] bus,” and an LVDS channel that “conveys
address and data bits of a PCI bus transaction in serial form.” Ex. 1001,
42:53–55, 42:60−61. By virtue of their dependency, dependent claims 11
and 12 also require these limitations.
i. “peripheral bridge directly coupled to the [CPU] without any
intervening [PCI] bus”
In its Petition, Petitioner relies on Hart’s “primary bridge [203]” to
teach the claimed “peripheral bridge,” citing Dr. Edwards’ testimony for
support. Pet. 83−85 (citing Ex. 1008, 3:37–56, 5:8–19, Fig. 2; Ex. 1003
¶¶ 202–203). However, as discussed above in our claim construction
analysis, we construe “peripheral bridge” as a bridge in a peripheral system
that connects to PCI and other busses, and is not a “north bridge” in a
computer system that links a CPU to main memory and/or a graphic
subsystem.
Here, Hart discloses that primary bridge 203 is included in processor
module that is connected a system memory. Ex. 1008, 3:36–48. As Patent
Owner points out, relying on Dr. Levitt’s testimony, “[a] POSITA would
recognize that in Hart Figure 2 . . . , the ‘primary bridge,’ . . . is a north
IPR2021-00666
Patent 9,529,768 B2

36

bridge, not a south bridge.” Prelim. Resp. 64 (citing Ex. 2001 ¶ 111).
According to Patent Owner, Hart’s primary bridge 203 “is used to connect
the processor 200 to memory 204, which indicates to a POSITA that bridge
[] 203 is a north bridge.” Id. In other words, primary bridge 203 “has all the
typical characteristics that a POSITA would recognize correspond to a north
bridge, which Petitioners contend is not the same as the claimed ‘peripheral
bridge’ of the ’768 patent.” Id. at 64–65 (citing Ex. 2001 ¶ 111). We credit
Dr. Levitt’s testimony as it is consistent with the Specification and the
general knowledge of an ordinarily skilled artisan.
In light of our claim construction that “peripheral bridge” is not a
“north bridge” in a computer system that links a CPU to main memory
and/or a graphic subsystem,” we determine that Petitioner fails to show that
the combination of Hart, Goodrum and McAlear teaches a “peripheral bridge
directly coupled to the [CPU] without any intervening [PCI] bus,” as
required by claims 10–12.
ii. an LVDS channel that “conveys address and data bits of a PCI bus
transaction in serial form”
As discussed above in our claim construction analysis, we adopt
Patent Owner’s proposed claim construction that, “[i]n data transmission,
‘serial’ means ‘one bit at a time on a single path,’ wherein “serial”
transmission means the opposite of “parallel” transmission.” Prelim. Resp.
17–18; Ex. 2001 ¶ 76; Ex. 2002, 9, 11.
In its Petition, Petitioner admits that Hart does not disclose “an LVDS
channel comprising two unidirectional, serial channels that transmit data in
IPR2021-00666
Patent 9,529,768 B2

37

opposite directions.” Pet. 86. Petitioner then relies on Goodrum to disclose
“conveying PCI transactions using differential signaling over a cable (e.g.,
cable 28) connected between cable interfaces (e.g., interfaces 104, 130) of a
PCI to PCI bridge,” and that “[t]wenty wire pairs of the cable 28 are used for
downstream communication and 20 more for upstream communication.” Id.
at 86 (citing Ex. 1006, 4:65−5:6, 5:44−51, 6:25−27, 57:30−49, 58:8−9).
According to Petitioner, Goodrum teaches “using LVDS signaling over the
cable” and “operating in a serial mode.” Id. (citing Ex. 1006, 6:25−31,
57:45−49, 106:16−31).
Petitioner contends that Goodrum discloses “how to communicate PCI
bus transactions over LVDS links,” wherein it “is less expensive than fiber
optics,” is “less complicated to interface than other serial methods,”
“provides significant common mode noise immunity,” “is faster than TTL,”
“when using twisted pair and shielding, it minimizes electromagnetic
radiation,” and “when using low voltage swings, it minimizes power
dissipation.” Pet. 81−82 (quoting Ex. 1006, 57:37−45). Petitioner explains
that Goodrum discloses “encoding transactions, including PCI transactions,
into multiple time-multiplexed messages,” wherein “60 bits are multiplexed
onto 20 cable lines and are transmitted each 10 ns over the cable 28.” Id. at
86−87 (citing Ex. 1006, 50:33−41, 55:14−16). According to Petitioner,
“[t]hese bits include address bits, data bits, and byte enable information bits
of a PCI bus transaction.” Id. at 87 (citing Ex. 1006, 55:25−31, 55:65−56:3,
Fig. 15A).
IPR2021-00666
Patent 9,529,768 B2

38

Petitioner asserts that a POSITA would have understood that “Hart’s
link primary bridge 203 and socket interface 223 could have been modified
to incorporate Goodrum’s cable interface, cable and LVDS signaling to
convey address bits, data bits, and byte enable information bits of a PCI bus
transaction in serial form for at least the reasons set forth above.” Id. at 88
(citing Ex. 1003 ¶¶ 203−207).
In its Preliminary Response, Patent Owner counters that the
combination of Hart and Goodrum does not disclose conveying “address and
data bits. . . in serial form” as recited in claim 10. Prelim. Resp. 66. Patent
Owner points out that “[t]he Petition does not assert that Hart discloses
conveying PCI bits in serial form” (id. (citing Pet. 86–88) (“addressing
Hart’s alleged contributions to claim limitation without mentioning serial
transmission”), and also avers that Goodrum does not disclose “conveying
any address or data bits ‘in serial form’ either.” Id. Patent Owner then
points out that “the Petition does not contend that McAlear discloses [] this
limitation.” Id. We agree with Patent Owner.
As we discussed above, the portions of Goodrum cited by Petitioner
for support to teach “a serial mode” (Pet. 86) disclose transmitting
“interrupts,” not for address or data bits of a PCI bus transaction, as required
by the challenged claims at issue. See Ex. 1006, 6:25−31, 106:16−31. In
addition, Goodrum’s differential signaling, relied upon by Petitioner (id. at
86), transmits signals in parallel over a “cable designed to support the High
Performance Parallel Interface (HIPPI) standard” and “the HIPPI cable
specifications,” not “in a serial bit stream” or “in serial form” as required by
IPR2021-00666
Patent 9,529,768 B2

39

the challenged claims at issue. See Ex. 1006, 57:22−49, 58:8−14, Fig. 16
(emphasis added). Goodrum makes clear that cable 28 is a “50 pair HIPPI
cable.” Id. at 57:22−24, 58:10.
Neither Petitioner nor Dr. Edwards explains why one of ordinary skill
in the art would have modified Goodrum’s “true differential” signaling that
transmits data in parallel over a HIPPI cable to convey “address and data bits
of a PCI bus transaction in serial form” as required by claims 10–12. Pet.
80−82, 86−88; Ex. 1003 ¶¶ 194−199, 203–207. Petitioner’s reason to
combine Goodrum with Hart and McAlear relies on those advantages
disclosed in Goodrum that are for transmitting data in parallel over a HIPPI
cable, not for serial transmissions as required by the challenged claims at
issue. Id.
In light of the foregoing, we determine that Petitioner fails to show
that the combination of Hart and Goodrum discloses the above-mentioned
“serial transmission” limitation, as required by claims 10–12.
iii. Conclusion on obviousness based on Hart, Goodrum and McAlear
For the reasons discussed above, we conclude that Petitioner has not
demonstrated a reasonable likelihood of prevailing in showing that claims
10–12 are unpatentable under § 103(a) as obvious over Hart and Goodrum in
further view of McAlear.
IPR2021-00666
Patent 9,529,768 B2

40

III. CONCLUSION
For the foregoing reasons, we conclude that Petitioner has not
demonstrated a reasonable likelihood of prevailing with respect to at least
one claim of the ’768 patent challenged in the Petition.
IV. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that the Petition is denied as to all challenged claims of
the ’768 patent, and no trial is instituted.

IPR2021-00666
Patent 9,529,768 B2

41

FOR PETITIONER:

Gianni Minutolli
Harpreet Singh
Alan Limbach
DLA PIPER LLP (US)
gianni.minutoli@dlapiper.com
harpreet.singh@dlapiper.com
alan.limbach@dlapiper.com

FOR PATENT OWNER:
Cyrus Morton
Derrick Carman
ROBINS KAPLAN LLP
cmorton@robinskaplan.com
dcarman@robinskaplan.com