Owen Martin et al.

Patent Trials and Appeals BoardAug 1, 2019

15071862 - (D) (P.T.A.B. Aug. 1, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/071,862 03/16/2016 Owen Martin 130-145 EMC-15-1105 3602 81435 7590 08/01/2019 Anderson Gorecki LLP 2 Dundee Park, Suite 301A Andover, MA 01810 EXAMINER TRAN, DENISE ART UNIT PAPER NUMBER 2138 NOTIFICATION DATE DELIVERY MODE 08/01/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): handerson@andersongorecki.com jgorecki@andersongorecki.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte OWEN MARTIN, ARIEH DON, and MICHAEL SCHARLAND ____________ Appeal 2018-008362 Application 15/071,862 Technology Center 2100 ____________ Before JOHN A. EVANS, JENNIFER L. McKEOWN, and JASON J. CHUNG, Administrative Patent Judges. EVANS, Administrative Patent Judge. DECISION ON APPEAL Appellants1 seek our review under 35 U.S.C. § 134(a) of the Examiner’s final rejection of Claims 1, 2, 8, 11, 12, and 18. App. Br. 2. Claims 3–7, 9–10, 13–17, 19, and 20 are allowed subject to objection. Id. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE.2 1 Appellants state the real party in interest is EMC IP Holding Company LLC. App. Br. 2. 2 Rather than reiterate the arguments of Appellants and the Examiner, we refer to the Appeal Brief (filed April 30, 2018, “App. Br.”), the Reply Brief (filed August 21, 2018, “Reply. Br.”), the Examiner’s Answer (mailed Appeal 2018-008362 Application 15/071,862 2 STATEMENT OF THE CASE The claims relate to a storage array comprising a compliance manager that causes a first storage group to comply with a first performance objective by reducing input/output access to a second storage group that has a lower level performance objective. App. Br. 2. Invention Claims 1 and 11 are independent. An understanding of the invention can be derived from a reading of Claim 1 which is reproduced below with some formatting added. 1. An apparatus comprising: a storage array comprising a multi-core processor, a memory, at least one data storage component, a first port, a second port, and a compliance manager, wherein the storage array maintains a mapping between a plurality of logical volumes and the at least one data storage component, and wherein the storage array comprises a first storage group comprising a first set of the logical volumes presented on the first port and a second storage group comprising a second set of the logical volumes presented on the second port, the first storage group having a first performance objective and the second storage group having a second performance objective, wherein the first performance objective corresponds to a higher level of performance than the second performance objective, the compliance manager comprising program code stored in the memory and implemented by the multi-core processor to cause August 10, 2018, “Ans.”), the Final Action (mailed March 1, 2018, “Final Act.”), and the Specification (filed March 16, 2016, “Spec.”) for their respective details. Appeal 2018-008362 Application 15/071,862 3 the first storage group to comply with the first performance objective by reducing a rate at which IOs to the second storage group are serviced. References and Rejection3 Claims 1, 2, 8, 11, 12, and 18 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Chambliss (US 2005/0076154 A1; Apr. 7, 2005) and Ganguli (US 2016/0179560 A1; filed Dec. 22, 2014).4 Final Act. 2–7. ANALYSIS CLAIMS 1, 2, 8, 11, 12, AND 18: OBVIOUSNESS OVER CHAMBLISS AND GANGULI. Claim 1 recites, inter alia: a storage array comprising a ... compliance manager comprising program code stored in the memory and implemented by the multicore processor to cause the first storage group to comply with the first performance objective by reducing a rate at which IOs to the second storage group are serviced. The Examiner finds Chambliss teaches the claimed compliance manager as comprising processor-implemented, stored program code to cause 3 The present application was examined under the first inventor to file provisions of the AIA. Final Act. 2. 4 Claims 3–7, 9, 10, 13–17, 19, and 20 are free of the prior art, but are objected to as being dependent upon a rejected base claim. Final Act. 7. Appeal 2018-008362 Application 15/071,862 4 performance gateways to record performance data for I/O commands and to manage I/O paths to delay I/O transmitted through paths that are over- performing associated service level guarantees to improve the performance of I/O paths that are under-performing. Final Act. 5. Appellants contend Chambliss teaches SLA server (16), but not gateways (14a, b) adjusting I/O activity to optimize performance based on information gathered at the gateways. App. Br. 11 (citing Chambliss, ¶ 19). Appellants further contend the claims recite the compliance manager is located within the storage array (i.e., “a storage array comprising a ... compliance manager”). But that Chambliss discloses that the SLA server and gateways 14a, b, are nodes located in the network between the hosts and the storage system (6a, b, c). Id. (citing Chambliss, Fig. 2). In the Answer, the Examiner expands upon the information that is used to regulate I/O performance. The Examiner further quotes Chambliss: When the service level agreement (SLA) server 16 determines that certain service level guarantees are not being satisfied for an application service group (ASG), then the SLA server 16 may apply a predefined throttling policy 24 to alter and effect the performance. This throttling policy may cause the performance gateways 14a, 14b that manage the I/O paths to delay the I/O transmitted through I/O paths that are over performing associated service level guarantees to improve the performance of I/O paths that are underperforming. Ans. 9 (quoting Chambliss, ¶ 47). However, the Answer does not respond to Appellants contention that Chambliss discloses each of the SLA server and the performance gateways are external to the storage array, contrary to the recitations of independent Claim 1. Independent Claim 11 contains Appeal 2018-008362 Application 15/071,862 5 commensurate recitations. We find, contrary to the claims, that the cited portions of Chambliss discloses an SLA server 18 that is not co-located with the storage system 6a–6c. See Chambliss, Figs. 1, 2. In view of the foregoing, we find the prior art fails to teach at least one limitation recited in the independent Claims. We, therefore, decline to sustain the rejection of independent Claims 1 and 11 and of Claims 2, 8, 11, 12, and 18 dependent therefrom. DECISION The rejection under 35 U.S.C. § 103(a) of Claims 1, 2, 8, 11, 12, and 18 is REVERSED. REVERSED