Intel Corporation

Patent Trials and Appeals Board

Sep 29, 2021

2020005126 (P.T.A.B. Sep. 29, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/574,352 12/17/2014 Himanshu Kaul P72419 8419
152398 7590 09/29/2021
Alliance IP, LLC - I
20 E. Thomas Rd.
Suite 2200, PMB 96
Phoenix, AZ 85012
EXAMINER
HUYNH, KIM T
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
09/29/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket@allianceip.com
eofficeaction@appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
_______________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________

Ex parte HIMANSHU KAUL, MARK A. ANDERS,
and GREGORY K. CHEN
_______________

Appeal 2020-005126
Application 14/574,3521
Technology Center 2100
_______________

Before CARL W. WHITEHEAD JR., HUNG H. BUI, and
DAVID J. CUTTITA, II, Administrative Patent Judges.

BUI, Administrative Patent Judge.

DECISION ON APPEAL
Appellant seeks our review under 35 U.S.C. § 134(a) from the
Examiner’s Final rejection of claims 1–24, all the pending claims. (Claims
App.). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.2

1 Appellant refers to “applicant(s)” as defined in 37 C.F.R. § 1.42.
Appellant identifies the real party in interest as Intel Corporation. Appeal
Br. 2.
2 Our Decision refers to Appellant’s Appeal Brief filed March 19, 2020
(“Appeal Br.”); Reply Brief filed June 30, 2020 (“Reply Br.”); Examiner’s
Answer mailed April 30, 2020 (“Ans.”); Final Office Action mailed
September 19, 2019 (“Final Act.”); and original Specification filed
December 17, 2014 (“Spec.”).
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STATEMENT OF THE CASE
Appellant’s claimed subject matter relates to “Networks-on-Chip
(NoCs) for on-die communication between cores [in multi-core processors]
[] for communication with routers to control and arbitrate the flow of data
between communication components.” Spec. ¶ 2.
Claims 1, 15, 20, and 22 are independent. Representative claims 1
and 15 are reproduced below with disputed limitations emphasized and
bracketed numerals added for clarity:
1. A processor comprising:
a first router comprising a plurality of port sets, wherein
the plurality of port sets comprise:
a first port set comprising an input port and an
output port;
a second plurality of port sets, wherein each port set
of the second plurality of port sets comprises:
an input port to be coupled to the output port of the
first port set; and
an output port to be coupled to the input port of the
first port set; and
[1] wherein the input port of the first port set is to
simultaneously provide circuit-switched data from a core of the
processor to each port set of the second plurality of port sets, and
[2] wherein the output port of the first port set is to
simultaneously provide circuit-switched data from each port set
of the second plurality of port sets to the core.

Appeal Br. 15 (Claims App.).
15. An apparatus comprising:
a first port set to comprise an input port and an output port;
a plurality of second port sets, wherein each of the second
port sets comprises:
an input port coupled to the output port of the first
port set;
an output port coupled to the input port of the first
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port set; and
wherein [1] the plurality of second port sets are to each
communicate at a first maximum bandwidth when fully utilized
and [2] the first port set is to communicate at a second maximum
bandwidth when fully utilized, the second maximum bandwidth
higher than the first maximum bandwidth.

Appeal Br. 18 (Claims App.).

REJECTIONS AND REFERENCES
(1) Claims 15–17 and 22 stand rejected under 35 U.S.C.
§ 102(a)(2) as anticipated by Solihin (US 2015/0331831 A1; published Nov.
19, 2015). Final Act. 2–5.
(2) Claims 1–10, 13, 18–21, and 23–24 stand rejected under
35 U.S.C. § 103 as obvious over Solihin and Johnson et al. (US
2008/0273531 A1; published Nov. 6, 2008; “Johnson”). Final Act. 5–15.
(3) Claims 11, 12, and 14 stand rejected under 35 U.S.C. § 103 as
obvious over Solihin, Johnson, and Price et al. (US 2014/0118176 A1;
published May 1, 2014; “Price”). Final Act. 16–17.

ANALYSIS
I. Anticipation of Claims 15–17 and 22 by Solihin
In support of the anticipation rejection, the Examiner finds Solihin
discloses each and every element of Appellant’s claim 15 and, similarly,
claim 22, including the disputed limitations:
wherein the plurality of second port sets are to each communicate
at a first maximum bandwidth when fully utilized and the first
port set is to communicate at a second maximum bandwidth
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when fully utilized, the second maximum bandwidth higher than
the first maximum bandwidth.

Final Act. 2–5 (citing Solihin ¶¶ 26, 30–34, 46, Figure 3).
Appellant contends Solihin does not disclose the disputed limitation
of claims 15 and 22. Appeal Br. 9–10. In particular, Appellant argues
paragraphs 26 and 46 of Solihin merely refer to “reduced bandwidth
utilization associated with circuit switching in some NoCs” and that
“bandwidth utilization can be maximized or otherwise improved in NoCs,”
but “fails to disclose any differences in maximum bandwidth among
individual input ports 310 and output ports 320” much less the disputed
limitation. Appeal Br. 9–10 (citing Solihin ¶¶ 26, 46). Appellant also
argues (1) “Solihin does not discuss relative bandwidth of the ports of a
router 122 (much less “maximum bandwidths” of the ports “when fully
utilized”), but rather is directed to overall improved bandwidth utilization
across the NoC” and (2) “the Examiner has inappropriately construed the
[disputed] limitation at issue [] by ignoring the plain meaning of the claim
and instead limiting the construction of this portion of the claim to the
embodiment described in a few portions of the Specification selected by the
Examiner.” Reply Br. 6–7 (citing Solihin ¶¶ 9, 24–26, 28, 29, 33, 46, 50,
and 52).
Appellant’s arguments are persuasive of Examiner error. Anticipation
under 35 U.S.C. § 102 is a question of fact. Brown v. 3M, 265 F.3d 1349,
1351 (Fed. Cir. 2001). To establish anticipation of a claim, each and every
claim element, arranged as is recited in the claim, must be found in a single
prior art reference. Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359,
1369 (Fed. Cir. 2008); Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d
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1376, 1383 (Fed. Cir. 2001).
The Examiner finds Solihin discloses Appellant’s claimed “apparatus
[router 122, shown in Figure 3]” provided with “a first port set [310A–
320A]” and “a plurality of second port sets [310B–320B, 310C–320, 310D–
320D, 310E–320E].” Final Act. 2–3 (citing Solihin ¶¶ 30–32, Figure 3).
Solihin’s Figure 3 is reproduced below with additional annotated
markings for illustration:

Figure 3 shows network router 122 disposed in a network-on-chip (NoC)
[shown in Figure 1] including a plurality of input ports 310 and output ports
320 “configured as a hybrid router that can implement packet switching as
well as circuit switching.” Solihin ¶ 30. According to Solihin, “network
router 122 may be configured with different numbers of circuit-switched
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virtual channels and packet-switched virtual channels” and “[e]ach of input
ports 310 [as well as output ports 320] may be associated with circuit-
switched virtual channel 311 and packet-switched virtual channel 312.”
Solihin ¶ 31.
For example, “when circuit-switched channel 350 is used [shown in
Figure 3, in response to a memory request and a connection setup message],
no decode and routing operation is necessarily performed” and “virtual
channel allocation, and switch allocation, routing delay may be reduced.”
Solihin ¶ 34. As such, “low bandwidth utilization typically associated with
circuit-switching in a NoC” is achieved in contrast to packet-switching for
the remaining input and output ports where high bandwidth is utilized
because each packet may go through four stages of processing at a router:
(1) decoding and routing, (2) virtual channel allocations, (3) switch
allocation, and (4) switch traversal. Solihin ¶¶ 24, 35.
Because Solihin’s “circuit-switched channel 350” established by the
first port set 310A–320B, shown in Figure 3, to operate at a lower
bandwidth, whereas “[p]acket switching may use a different path [i.e.,
second port sets] according to the routing policy, compared to the path under
circuit-switched connection [at a higher bandwidth]” (Solihin ¶ 43), we
agree with the Examiner that Solihin discloses the relative bandwidth of the
ports of a router 122, i.e., “the bandwidth utilization is different at different
levels.” Ans. 20.
While an ordinarily skilled artisan would reasonably be expected to
infer from Solihin that any combination of circuit-switched channels and
packet-switched channels could be established between the first port set and
the second port sets to operate at different bandwidth utilizations, Solihin’s
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“circuit-switched channel 350” is established by the first port set 310A–
320B to operate specifically at a lower bandwidth (Solihin ¶¶ 34–35, 43)—
opposite of Appellant’s claimed “the first port set is to communicate at a
second maximum bandwidth [higher than the first maximum bandwidth]
when fully utilized” while the “second port sets are to each communicate at
a first maximum bandwidth when fully utilized” recited in claims 15 and 22.
For these reasons, we do not sustain3 the Examiner’s anticipation
rejection of claims 15 and 22, and dependent claims 16 and 17.4

3 In the event of further prosecution, we invite the Examiner to consider
rejecting claims 15 and 22 under 35 U.S.C. § 103 as obvious over Solihin.
Because Solihin’s router 122, shown in Figure 3, could be configured with
different numbers of circuit-switched channels and packet-switched
channels, an ordinarily skilled artisan could reasonably be expected to infer
from Solihin that any combination of circuit-switched channels and packet-
switched channels could be established between the first port set and the
second port sets to operate at different bandwidth utilizations, including
Appellant’s claimed “the first port set [] to communicate at a second
maximum bandwidth [higher than the first maximum bandwidth] when fully
utilized” while the “second port sets [] to each communicate at a first
maximum bandwidth when fully utilized” in the manner recited in claims 15
and 22. Establishing connection between input and output ports of the first
and second port sets, via either “circuit-switched channels” or “packet-
switched channels” would have been either within the skilled level of an
artisan or would have been obvious to those ordinarily skilled artisans.
4 Claim 17 further recites: “a plurality of connections, each connection to
permanently couple the input port of the first port set to a distinct output port
of the second port sets.” Appellant argues Solihin’s Figure 3 shows “a set of
mappings the input ports 310 and the output ports 320” via “a reconfigurable
connection [] rather than a permanent connection” and, as such, does not
disclose the claimed “plurality of connections, each connection to
permanently couple the input port of the first port set to a distinct output port
of the second port sets” recited in claim 17. In response, the Examiner refers
to “Price’s reference for the missing feature.” Ans. 22. However, the
rejection is based on anticipation under § 102, not obviousness under § 103.
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II. Obviousness of Claims 1–10, 13, 18–21, and 23–24 over Solihin and
Johnson
Claim 1 recites a processor provided with a router comprising a
plurality of port sets,
[1] wherein the input port of the first port set is to
simultaneously provide circuit-switched data from a core of the
processor to each port set of the second plurality of port sets,
and
[2] wherein the output port of the first port set is to
simultaneously provide circuit-switched data from each port set
of the second plurality of port sets to the core.

Appeal Br. 15 (Claims App.) (emphasis added).
The Examiner finds Solihin teaches most limitations of Appellant’s
claim 1, except for the “wherein” clauses. Final Act. 5–6 (citing Solihin ¶¶
30–34, Figure 3). The Examiner then relies on Johnson for teaching the
“wherein” clauses to support the conclusion of obviousness, i.e.,
“it would have been obvious . . . to incorporate the teachings of
Johnson with the teachings of Solihin for the purpose of
providing simultaneously switching between source cores and
destination cores and to handle parallel to access the
information through multiple paths so as to incur lower data
transfer latency, high utilization of bandwidth and enhance the
performance in chip multiprocessor design strongly contingent
on energy efficiency of the design.”

Id. at 6 (citing Johnson ¶ 3).
Appellant acknowledges Johnson teaches “a data switch,” i.e., “a
crossbar switch which comprises a number of external input and output port

As such, we agree with Appellant that Solihin does not disclose the disputed
limitation and, therefore, cannot anticipate claim 17. However, it is our
position, that claim 17 should be rejected as obvious over the teachings of
Solihin and Price.
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devices” and that “crossbar switch being able to open any combination of
simultaneous input to output connections as required.” Id. at 5 (citing
Johnson ¶¶ 2, 3). However, Appellant argues Johnson does not teach (1)
“wherein the input port of the first port set is to simultaneously provide
circuit-switched data from a core of the processor to each port set of the
second plurality of port sets,” and (2) “wherein the output port of the first
port set is to simultaneously provide circuit-switched data from each port set
of the second plurality of port sets to the core” recited in claim 1. Id.
Appellant also argues there is no reason to modify Solihin to incorporate
Johnson because (1) “if circuit-switched data from multiple input ports 310
were simultaneously provided to a single output port 320, the integrity of the
data would be compromised when mixed together” and (2) “such a
modification would have been unworkable and inconsistent with the
teachings of Solihin.” Id. at 6–7.
Appellant’s arguments are not persuasive of Examiner error. The test
for obviousness is not whether the claimed invention is expressly suggested
in any one or all of the references, but whether the claimed subject matter
would have been obvious to those of ordinary skill in the art in light of the
combined teachings of those references. In re Keller, 642 F.2d 413, 425
(CCPA 1981). In such an analysis, precise teachings directed to the specific
subject matter of the challenged claim need not be identified because the
inferences and creative steps that a person of ordinary skill in the art would
employ can be taken into account. See KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 418 (2007).
Contrary to Appellant’s arguments, the Examiner finds, and we agree,
that the combination of Solihin and Johnson teaches or suggests all
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limitations of claim 1. For example, Solihin teaches a network router,
shown in Figures 1–3, “configured with different numbers of circuit-
switched virtual channels and packet-switched virtual channels,” including,
for example: “a circuit-switched channel 350 [shown in Figure 3,” whereas
“[p]acket switching may use a different path according to the routing policy,
compared to the path under circuit-switched connection.” Solihin ¶¶ 31, 43.
As a secondary reference, Johnson teaches a “crossbar switch [] able
to open any combination of simultaneous input to output connections as
required.” Johnson ¶¶ 2, 3.
The combined teachings of Solihin and Johnson would suggest to
those skilled in the art to utilize (1) an “input port of the first port set [] to
simultaneously provide circuit-switched data from a processor core to each
port set of the second plurality of port sets,” and (2) an “output port of the
first port set [] to simultaneously provide circuit-switched data from each
port set of the second plurality of port sets to the [processor] core” recited in
claim 1.
When a claimed invention “‘simply arranges old elements with each
performing the same function it had been known to perform’ and yields no
more than one would expect from such an arrangement, the combination is
obvious.” KSR, 550 U.S. at 417. Indeed, “[t]he combination of familiar
elements according to known methods is likely to be obvious when it does
no more than yield predictable results.” KSR, 550 U.S. at 416.
In this case, the Examiner has provided reasoning with rational
underpinning to combine these well-known elements to achieve the claimed
subject matter. Final Act. 5–6; Ans. 20–21. Appellant, on the other hand,
has not explained (1) why the Examiner’s combination of Solihin and
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Johnson would yield unpredictable results or unexpected benefit, or (2) why
the Examiner’s reason for making the combination is erroneous, or (3) why a
person of ordinary skill in the art would not have reached the conclusions
reached by the Examiner.
We are not persuaded that there is no reason to combine Solihin and
Johnson because Johnson suggests that “any combination of simultaneous
input to output connections” could be established as needed. Johnson ¶¶ 2,
3. Nor do we find any evidence in the record to support Appellant’s
argument that (1) “if circuit-switched data from multiple input ports 310
were simultaneously provided to a single output port 320, the integrity of the
data would be compromised when mixed together” and (2) the proposed
modification “would have been unworkable and inconsistent with the
teachings of Solihin.” Final Act. 6–7. Instead, we find the weight of the
evidence shows that the proffered combination is merely a predictable use of
known elements according to their established functions. KSR, 550 U.S. at
415–416.
For these reasons, Appellant has not persuaded us of Examiner error.
Accordingly, we sustain the Examiner’s obviousness rejection of
independent claim 1 and its dependent claims 2–10, 13, 18, 19, which were
not argued separately.
Claim 20 is broader than claim 1, and recites “a non-transitory
machine readable medium including information to represent, when
manufactured, to be configured to:
provide, from a core of a processor, first circuit-switched
data to a first input port of a router; and
simultaneously communicate a first portion of the first
circuit-switched data from the first input port of the router to a
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first output port of the router and a second portion of the first
circuit-switched data from the first input port of the router to a
second output port of the router,
wherein the first portion of the first circuit-switched data
is not communicated to the second output port of the router and
the second portion of the first circuit-switched data is not
communicated to the first output port of the router.”

Appeal Br. 20 (Claims App.) (emphasis added).
Appellant argues the combination of Solihin and Johnson does not
teach or suggest the negative limitation: “‘wherein the first portion of the
first circuit-switched data is not communicated to the second output port of
the router and the second portion of the first circuit-switched data is not
communicated to the first output port of the router’ because, if an input port
of Johnson is simultaneously coupled to multiple output ports (e.g., during a
multicast communication), the data on the input port would be sent to each
of the multiple output ports.” Appeal Br. 8.
We disagree with Appellant. At the outset, we note the negative
limitation was added by amendment during examination. However, this
particular phrase is not described or supported by Appellant’s Specification.
Nor do we find “a reason to exclude the relevant information” from
Appellant’s Specification. See Santarus, Inc. v. Par Pharmaceutical, Inc.,
694 F.3d 1344, 1351 (Fed. Cir. 2012). Because there is no basis in
Appellant’s Specification for adding the negative limitation, the negative
limitation at issue should not have been accorded any patentable weight.
Even if the negative limitation were to be accorded patentable weight
(as we have), an ordinarily skilled artisan would understand that, when a
first portion of the first circuit-switched data is communicated from a first
input port to a first output port of a router, that same portion of the circuit-
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switched data is not communicated to another output port of the router in the
manner recited in claim 20.
For these reasons, we also sustain the Examiner’s obviousness
rejection of independent claim 20 and its dependent claim 21, which was not
argued separately.
With respect to claim 23 which depend from claim 20, Appellant
argues neither Solihin nor Johnson teaches or suggests “the credit-2 packet
system of the output port and the credit-1 packet system of the input port”
recited in claim 23. Appeal Br. 12; Reply Br. 10–11.
The Examiner responds that paragraphs 40–41 of Solihin teach the
disputed limitation. Ans. 17.
We disagree with the Examiner. Paragraphs 40–41 of Solihin
describe the use of a connection setup message used to reserve a circuit-
switched connection between input and output ports of a router. However,
nowhere in Solihin is there any reference to “a credit-1 packet system” or “a
credit-2 packet system” recited in claim 23. For this reason, we do not
sustain the Examiner’s obviousness rejection of claim 23.
With respect to claim 24 which also depend from claim 20, Appellant
argues neither Solihin nor Johnson teaches or suggests the use of
“dedicated” signal lines to carry “circuit-switched data” between input ports
to output ports because Solihin teaches “a reconfigurable connection of
crossbar switched 330 (as opposed to a set of signal lines dedicated to
carrying circuit-switched data from the input port to the output port [as
recited in claim 24]).” Appeal Br. 12–13; Reply Br. 10–11.
The Examiner responds that paragraphs 30–32 and Figure 3 of Solihin
teach the use of “dedicated” signal lines. Ans. 17–18.
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We disagree with the Examiner. As previously discussed, paragraphs
30–32 and Figure 3 of Solihin describe “a hybrid router that can implement
packet switching as well as circuit switching” and “may be configured with
different numbers of circuit-switched virtual channels and packet-switched
virtual channels.” Solihin ¶¶ 30–31. Because Solihin teaches “a
reconfigurable connection,” there is no teaching or suggestion of
“dedicated” signal lines used between input and output ports in the manner
recited in claim 24. For this reason, we do not sustain the Examiner’s
obviousness rejection of claim 24.

III. Obviousness of Claims 11, 12, and 14 over Solihin, Johnson, and Price
Claim 11 depends from claim 1, and further recites:
“wherein the output port of the first port set is further to comprise
a first plurality of flip flops sets, each flip flop set of the first
plurality of flip flop sets to store packet data provided by a
distinct input port of the second plurality of port sets, wherein
each flip flop set of the first plurality of flip flop sets is to be
enabled simultaneously.”

Appeal Br. 17 (Claims App.). Claim 12 depends from claim 11.

Appellant acknowledges Price teaches “a flip-flop to store a
comparison output” (Price ¶ 10), but argues that Price does not teach a “first
plurality of flip flops sets” of an “output port of the first port set,” much less
“each flip flop set of the first plurality of flip flop sets to store packet data
provided by a distinct input port of the second plurality of port sets, wherein
each flip flop set of the first plurality of flip flop sets is to be enabled
simultaneously” as recited in claim 11. Appeal Br. 11.
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In response, the Examiner does not address Appellant’s argument;
instead, the Examiner refers to the “Price’s reference for the missing
feature.” Ans. 21–22.
We agree with Appellant. Nowhere in Price is there any teaching of
the disputed limitation of claim 11. For this reason, we do not sustain the
Examiner’s obviousness rejection of claim 11 and dependent claims 12 and
14.

DECISION
As such, we affirm the Examiner’s rejection of claims 1–10, 13, and
18–21 as obvious over Solihin and Johnson. However, we reverse the
Examiner’s rejection of (1) claims 15–17 and 22 as anticipated by Solihin;
(2) claims 23–24 as obvious over Solihin and Johnson; and (3) claims 11,
12, and 14 as obvious over Solihin, Johnson, and Price.

DECISION SUMMARY
In summary:
Claim(s)
Rejected
35 U.S.C. § Reference(s)/
Basis
Affirmed Reversed
15–17, 22 102 Solihin 15–17, 22
1–10, 13,
18–21, 23–
24
103 Solihin,
Johnson
1–10, 13,
18–21
23, 24
11, 12, 14 103 Solihin,
Johnson,
Price
11, 12, 14
Overall
Outcome
1–10, 13,
18–21
11, 12, 14–
17, 22–24
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART